[PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the orignal SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel --- hw/intc/Kconfig

[PATCH v1 0/3] RISC-V ACLINT Support

series, we require OpenSBI and Linux with ACLINT support which can be found in riscv_aclint_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Anup Patel (3): hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-factor FDT

[PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation

We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 514 ++-- 1 file changed, 320 insertions

[PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine

We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 110 +++- include/hw/riscv/virt.h | 2 + 2 files ch

Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > On Sun, Jun 13, 2021 at 12:08 AM Anup Patel wrote: > > > > The RISC-V ACLINT is more modular and backward compatible with > > original SiFive CLINT so instead of duplicating the orignal > > SiFive CLINT impleme

Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Fri, Jun 18, 2021 at 12:20 PM Alistair Francis wrote: > > On Sun, Jun 13, 2021 at 2:09 AM Anup Patel wrote: > > > > The RISC-V ACLINT is more modular and backward compatible with > > original SiFive CLINT so instead of duplicating the orignal > > SiFive CLINT

Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine

On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel wrote: > > > > We extend virt machine to emulate ACLINT devices only when "aclint=on" > > parameter is passed along with machine name in QEMU command-line.

Re: [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation

On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > On Sun, Jun 13, 2021 at 12:12 AM Anup Patel wrote: > > > > We re-factor and break the FDT generation into smaller functions > > so that it is easier to modify FDT generation for different > > configurations of vi

Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine

On Mon, Jul 12, 2021 at 11:45 AM Bin Meng wrote: > > On Mon, Jul 12, 2021 at 1:39 PM Anup Patel wrote: > > > > On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > > > > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel wrote: > > > > > > >

Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine

On Mon, Jul 12, 2021 at 6:41 PM Bin Meng wrote: > > On Mon, Jul 12, 2021 at 6:54 PM Anup Patel wrote: > > > > On Mon, Jul 12, 2021 at 11:45 AM Bin Meng wrote: > > > > > > On Mon, Jul 12, 2021 at 1:39 PM Anup Patel wrote: > > > > > &g

Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

On Fri, Jul 9, 2021 at 9:01 AM Alistair Francis wrote: > > Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V > CPU GPIO lines to set the timer and soft MIP bits. > > Signed-off-by: Alistair Francis > --- > include/hw/intc/sifive_clint.h | 2 + > hw/intc/sifive_clint.c

Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines

On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis wrote: > > Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V > CPU GPIO lines to set the external MIP bits. > > Signed-off-by: Alistair Francis > --- > include/hw/intc/sifive_plic.h | 4 > hw/intc/sifive_plic.c

Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines

On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis wrote: > > Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V > CPU GPIO lines to set the external MIP bits. > > Signed-off-by: Alistair Francis > --- > include/hw/intc/sifive_plic.h | 4 > hw/intc/sifive_plic.c

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

On Tue, Jun 15, 2021 at 1:41 PM Alistair Francis wrote: > > On Sat, Jun 12, 2021 at 12:04 AM Anup Patel wrote: > > > > On Fri, Jun 11, 2021 at 2:16 PM Alistair Francis > > wrote: > > > > > > On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: >

Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts

On Thu, Sep 9, 2021 at 12:14 PM Alistair Francis wrote: > > On Thu, Sep 2, 2021 at 9:26 PM Anup Patel wrote: > > > > The guest external interrupts for external interrupt controller are > > not delivered to the guest running under hypervisor on time. This > > resu

Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts

On Wed, Sep 15, 2021 at 6:19 AM Alistair Francis wrote: > > On Tue, Sep 14, 2021 at 2:33 AM Anup Patel wrote: > > > > On Thu, Sep 9, 2021 at 12:14 PM Alistair Francis > > wrote: > > > > > > On Thu, Sep 2, 2021 at 9:26 PM Anup Patel wrote: > &g

[PATCH v2 00/22] QEMU RISC-V AIA support

in riscv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Changes since v1: - Revamped whole series and created more granular patches - Added HGEIE and HGEIP CSR emulation for H-extension - Added APLIC emulation - Added IMSIC emulation Anup Patel (22):

[PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts

inject interrupt upon every sret instruction. Signed-off-by: Anup Patel --- target/riscv/op_helper.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..4c995c239e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv

[PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 8 +- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c| 560

[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback

The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 19 +++ target/riscv/cpu_helper.c | 14 ++ 2 files

[PATCH v2 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) di

[PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs

The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 126 + target/riscv

[PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel --- target/riscv/csr.c | 154 + 1 file changed, 154 insertions(+) diff --git a/target/riscv/csr.c b

[PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervsior can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++--- 3 files changed, 16 insertions(+), 8 deletions

[PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation

expects AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel --- target/riscv/cpu.c | 11 +++ target/riscv/cpu.h | 5 + 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0ade6ad144..9dc9d04923 100644 --- a/target/riscv

[PATCH v2 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine

We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel --- hw/riscv/Kconfi

[PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 61 --- target/riscv/cpu.h

[PATCH v2 07/22] target/riscv: Add defines for AIA CSRs

The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 128 1 file changed, 128 insertions(+) diff --git a/target/riscv

[PATCH v2 06/22] target/riscv: Add AIA cpu feature

We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities

. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 19 +++ target/riscv/cpu.h| 12 ++ target/riscv/cpu_helper.c | 241 +- target/riscv/machine.c| 3 + 4 files changed, 245 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.c b/target

[PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs

12 so we add dummy implementation (i.e. read zero and ignore write) of AIA interrupt filtering CSRs. Signed-off-by: Anup Patel --- target/riscv/csr.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7180cc927c..c4057b44cb 1

[PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs

The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel --- target/riscv/csr.c | 199

[PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 7 ++ target/riscv/csr.c

[PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff

[PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 files changed, 6

[PATCH v2 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

SIs to the AIA IMSIC. We also provide "aia-guests=" parameter which can be used to specify number of VS-level AIA IMSIC Guests MMIO pages for each HART. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 430 --

[PATCH v2 22/22] docs/system: riscv: Document AIA options for virt machine

We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel --- docs/system/riscv/virt.rst | 16 1 file changed, 16 insertions(+) diff --git a/docs/system/ris

[PATCH v2 18/22] hw/intc: Add RISC-V AIA APLIC device emulation

adds device emulation for RISC-V AIA APLIC. Signed-off-by: Anup Patel --- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/riscv_aplic.c | 970 ++ include/hw/intc/riscv_aplic.h | 73 +++ 4 files changed, 1047 insertions

[PATCH v2 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation

. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel --- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/riscv_imsic.c | 443 ++ include

Re: [PATCH v2 00/22] QEMU RISC-V AIA support

On Sat, Sep 4, 2021 at 7:21 PM Bin Meng wrote: > > On Thu, Sep 2, 2021 at 7:26 PM Anup Patel wrote: > > > > The advanced interrupt architecture (AIA) extends the per-HART local > > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > > and

RE: [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware

> -Original Message- > From: Qemu-riscv bounces+anup.patel=wdc@nongnu.org> On Behalf Of Palmer Dabbelt > Sent: 06 November 2020 08:19 > To: alistai...@gmail.com > Cc: qemu-ri...@nongnu.org; bmeng...@gmail.com; Alistair Francis > ; qemu-devel@nongnu.org > Subject: Re: [PATCH v2 4/4] h

[PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB

The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel --- hw/riscv/sifive_u.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw

RE: [PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

> -Original Message- > From: Alistair Francis > Sent: 11 June 2020 04:55 > To: Anup Patel > Cc: Peter Maydell ; Palmer Dabbelt > ; Alistair Francis ; Sagar > Karandikar ; Atish Patra > ; open list:RISC-V ; > qemu-devel@nongnu.org Developers ; Anup > Patel

RE: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

> -Original Message- > From: Qemu-riscv bounces+anup.patel=wdc@nongnu.org> On Behalf Of Alistair Francis > Sent: 11 June 2020 04:59 > To: Anup Patel > Cc: Peter Maydell ; open list:RISC-V ri...@nongnu.org>; Sagar Karandikar ; Anup > Patel ; qemu-devel@n

[PATCH v6 0/5] RISC-V multi-socket support

specified - Remove SPIKE_CPUS_PER_SOCKET_MIN and SPIKE_CPUS_PER_SOCKET_MAX in PATCH3 - Remove VIRT_CPUS_PER_SOCKET_MIN and VIRT_CPUS_PER_SOCKET_MAX in PATCH5 Anup Patel (5): hw/riscv: Allow creating multiple instances of CLINT hw/riscv: Allow creating multiple instances of PLIC hw/riscv:

[PATCH v6 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets

limit can be changed in future. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- hw/riscv/spike.c | 237 ++- include/hw/riscv/spike.h | 11 +- 2 files changed, 169 insertions(+), 79 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.

[PATCH v6 1/5] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20

[PATCH v6 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- hw/riscv/Makefile.objs | 1 + hw/riscv/numa.c | 242 include/hw/riscv/numa.h | 113 +++ 3 files changed, 356

[PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

ine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- hw/riscv/virt.c | 530 +++- include/hw/riscv/virt.h | 9 +- 2 files changed, 308 insertions(+), 231 deletions(-) diff --git a/hw/riscv/virt.c b/hw

[PATCH v6 2/5] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c| 2

Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

On Thu, Jun 18, 2020 at 7:15 AM Alistair Francis wrote: > > On Mon, Jun 15, 2020 at 8:24 PM Anup Patel wrote: > > > > We extend RISC-V virt machine to allow creating a multi-socket > > machine. Each RISC-V virt machine socket is a NUMA node having > > a set of HAR

Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

On Thu, Jun 18, 2020 at 7:15 AM Alistair Francis wrote: > > On Mon, Jun 15, 2020 at 8:24 PM Anup Patel wrote: > > > > We extend RISC-V virt machine to allow creating a multi-socket > > machine. Each RISC-V virt machine socket is a NUMA node having > > a set of HAR

Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

On Thu, Jun 18, 2020 at 7:15 AM Alistair Francis wrote: > > On Mon, Jun 15, 2020 at 8:24 PM Anup Patel wrote: > > > > We extend RISC-V virt machine to allow creating a multi-socket > > machine. Each RISC-V virt machine socket is a NUMA node having > > a set of HAR

Re: [PATCH 1/1] hw/intc/riscv_aplic: Fix APLIC in clrip and clripnum write emulation

On Thu, Aug 8, 2024 at 1:51 PM Yong-Xuan Wang wrote: > > In the section "4.7 Precise effects on interrupt-pending bits" > of the RISC-V AIA specification defines that: > > If the source mode is Level1 or Level0 and the interrupt domain > is configured in MSI delivery mode (domaincfg.DM = 1): > The

Re: [PATCH 1/1] goldfish_rtc: keep time offset when resetting

> > Move the synchronization of the RTC with the system clock to the instance > realization. > > Reported-by: Frederik Du Toit Lotter > Signed-off-by: Heinrich Schuchardt LGTM. Reviewed-by: Anup Patel Regards, Anup > --- > hw/rtc/goldfish_rtc.c | 14 +++--- > 1 fil

Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs

f-by: Xu Lu LGTM. Reviewed-by: Anup Patel Regards, Anup > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 8631be97c5..9bebfae3f0 100644 > --- a/target/riscv/csr.c > +++ b/target/

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