On Thu, Aug 8, 2024 at 1:51 PM Yong-Xuan Wang <yongxuan.w...@sifive.com> wrote: > > In the section "4.7 Precise effects on interrupt-pending bits" > of the RISC-V AIA specification defines that: > > If the source mode is Level1 or Level0 and the interrupt domain > is configured in MSI delivery mode (domaincfg.DM = 1): > The pending bit is cleared whenever the rectified input value is > low, when the interrupt is forwarded by MSI, or by a relevant > write to an in clrip register or to clripnum. > > Update the riscv_aplic_set_pending() to match the spec.
Same comments at the kernel patch. https://lore.kernel.org/kvm/caahsdy3nmwbhy9qef9luexfr0ie7wc-u0d_fhzc47pxk-mz...@mail.gmail.com/ Regards, Anup > > Signed-off-by: Yong-Xuan Wang <yongxuan.w...@sifive.com> > --- > hw/intc/riscv_aplic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index c1748c2d17d1..45d8b4089229 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -247,7 +247,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState > *aplic, > > if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) || > (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { > - if (!aplic->msimode || (aplic->msimode && !pending)) { > + if (!aplic->msimode) { > return; > } > if ((aplic->state[irq] & APLIC_ISTATE_INPUT) && > -- > 2.17.1 > >
