[PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs

The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA local interrupt CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 128 1 file changed, 128 insertions(+) diff --git

[PATCH 0/4] AIA local interrupt CSR support

scv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Anup Patel (4): target/riscv: Add defines for AIA local interrupt CSRs target/riscv: Add CPU feature for AIA CSRs target/riscv: Implement AIA local interrupt CSRs hw/riscv: virt: Use AIA IN

[PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

We implement various AIA local interrupt CSRs for M-mode, HS-mode, and VS-mode. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 27 +- target/riscv/cpu.h| 52 +- target/riscv/cpu_helper.c | 245 - target/riscv/csr.c| 1059

[PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs

We add experimental CPU feature to enable AIA CSRs. This experimental feature can be enabled by setting "x-aia=true" for CPU in the QEMU command-line parameters. Signed-off-by: Anup Patel --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 4 +++- 2 files changed, 8 insertions(+),

[PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git

Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang wrote: > > Only support supervisor external interrupt currently. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > hw/intc/sifive_plic.c| 29 - > target/riscv/kvm-stub.c | 5 + > target/riscv/kvm

[PATCH 1/2] hw/riscv: sifive_u: Allow passing custom DTB

Extend sifive_u machine to allow passing custom DTB using "-dtb" command-line parameter. This will help users pass modified DTB or Linux SiFive DTB to sifive_u machine. Signed-off-by: Anup Patel --- hw/riscv/sifive_u.c | 28 1 file changed, 20 insert

[PATCH 2/2] hw/riscv: virt: Allow passing custom DTB

Extend virt machine to allow passing custom DTB using "-dtb" command-line parameter. This will help users pass modified DTB to virt machine. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3

On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis wrote: > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary. > > Signed-off-by: Alistair Francis > --- > .gitmodules | 3 +++ > Makefile| 3 ++- > configure

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware

On Wed, Jun 19, 2019 at 6:21 AM Alistair Francis wrote: > > If the user hasn't specified a firmware to load (with -bios) or > specified no bios (with -bios none) then load OpenSBI by default. This > allows users to boot a RISC-V kernel with just -kernel. > > Signed-off-by: Alistair Francis > ---

Re: [Qemu-devel] [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, Jul 1, 2019 at 6:12 PM Jonathan Cameron wrote: > > On Fri, 28 Jun 2019 09:12:45 -0700 > Alistair Francis wrote: > > > On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron > > wrote: > > > > > > On Thu, 27 Jun 2019 08:20:10 -0700 > > > Palmer Dabbelt wrote: > > > > > > > From: Alistair Franc

Re: [Qemu-devel] [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3

On Tue, Jul 2, 2019 at 2:57 AM Alistair Francis wrote: > > On Mon, 2019-07-01 at 19:13 +0100, Peter Maydell wrote: > > On Mon, 1 Jul 2019 at 19:09, Alistair Francis < > > alistair.fran...@wdc.com> wrote: > > > On Mon, 2019-07-01 at 19:01 +0100, Peter Maydell wrote: > > > > On Mon, 1 Jul 2019 at 18

[PATCH v7 0/3] RTC support for QEMU RISC-V virt machine

Rebased on RTC code refactoring Changes since v1: - Implemented VMState save/restore callbacks Anup Patel (3): hw: rtc: Add Goldfish RTC device riscv: virt: Use Goldfish RTC device MAINTAINERS: Add maintainer entry for Goldfish RTC MAINTAINERS | 8 + h

[PATCH v7 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC

Add myself as Goldfish RTC maintainer until someone else is willing to maintain it. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2a68555ae..492c0d1baa 100644 --- a

[PATCH v7 2/3] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/

[PATCH v7 1/3] hw: rtc: Add Goldfish RTC device

migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/rtc/Kconfig| 3 + hw/rtc/Makefile.objs | 1 + hw/rtc

Re: [PATCH v7 2/3] riscv: virt: Use Goldfish RTC device

On Wed, Nov 6, 2019 at 2:05 PM Anup Patel wrote: > > We extend QEMU RISC-V virt machine by adding Goldfish RTC device > to it. This will allow Guest Linux to sync it's local date/time > with Host date/time via RTC device. > > Signed-off-by: Anup Patel > Reviewed-by:

[PATCH v8 0/3] RTC support for QEMU RISC-V virt machine

to correct location Changes since v3: - Address all nit comments from Alistair Changes since v2: - Rebased on RTC code refactoring Changes since v1: - Implemented VMState save/restore callbacks Anup Patel (3): hw: rtc: Add Goldfish RTC device riscv: virt: Use Goldfish RTC device MA

[PATCH v8 1/3] hw: rtc: Add Goldfish RTC device

migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/rtc/Kconfig| 3 + hw/rtc/Makefile.objs | 1 + hw/rtc

[PATCH v8 2/3] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/

[PATCH v8 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC

Add myself as Goldfish RTC maintainer until someone else is willing to maintain it. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2a68555ae..492c0d1baa 100644 --- a

[PATCH] riscv/virt: Add syscon reboot and poweroff DT nodes

The SiFive test device found on virt machine can be used by generic syscon reboot and poweroff drivers available in Linux kernel. This patch updates FDT generation in virt machine so that Linux kernel can probe and use generic syscon drivers. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 28

RE: [PATCH] riscv/virt: Add syscon reboot and poweroff DT nodes

Correct Palmer's email address. > -Original Message- > From: Anup Patel > Sent: Monday, November 11, 2019 7:08 PM > To: Peter Maydell ; Palmer Dabbelt > ; Alistair Francis ; Sagar > Karandikar > Cc: Atish Patra ; Christoph Hellwig ; > Anup Patel ; qemu

RE: [PATCH] riscv/virt: Add syscon reboot and poweroff DT nodes

> -Original Message- > From: Bin Meng > Sent: Monday, November 11, 2019 8:58 PM > To: Anup Patel > Cc: Peter Maydell ; Alistair Francis > ; Sagar Karandikar ; > Palmer Dabbelt ; qemu-devel@nongnu.org; Atish > Patra ; qemu-ri...@nongnu.org; Christoph Hellwig &

RE: [PATCH v4 1/2] hw: rtc: Add Goldfish RTC device

> -Original Message- > From: Alistair Francis > Sent: Friday, October 25, 2019 5:40 AM > To: Anup Patel > Cc: Peter Maydell ; Palmer Dabbelt > ; Alistair Francis ; Sagar > Karandikar ; Bastian Koppelmann > ; Atish Patra ; > qemu-ri...@nongnu.org; qemu-d

[PATCH v5 2/2] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/

[PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

orrect location Changes since v3: - Address all nit comments from Alistair Changes since v2: - Rebased on RTC code refactoring Changes since v1: - Implemented VMState save/restore callbacks Anup Patel (2): hw: rtc: Add Goldfish RTC device riscv: virt: Use Goldfish RTC device h

[PATCH v5 1/2] hw: rtc: Add Goldfish RTC device

migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel --- hw/rtc/Kconfig| 3 + hw/rtc/Makefile.objs | 1 + hw/rtc/goldfish_rtc.c | 288

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis wrote: > > On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > > > > This series adds RTC device to QEMU RISC-V virt machine. We have > > selected Goldfish RTC device model for this. It's a pretty simple >

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Sat, Nov 2, 2019 at 4:44 AM Palmer Dabbelt wrote: > > On Fri, 01 Nov 2019 08:40:24 PDT (-0700), a...@brainfault.org wrote: > > On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis > > wrote: > >> > >> On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > >

[PATCH v6 0/3] RTC support for QEMU RISC-V virt machine

or Goldfish RTC Changes since v4: - Fixed typo in trace event usage - Moved goldfish_rtc.h to correct location Changes since v3: - Address all nit comments from Alistair Changes since v2: - Rebased on RTC code refactoring Changes since v1: - Implemented VMState save/restore callbacks Anup Patel

[PATCH v6 1/3] hw: rtc: Add Goldfish RTC device

migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/rtc/Kconfig| 3 + hw/rtc/Makefile.objs | 1 + hw/rtc

[PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC

Add myself as Goldfish RTC maintainer until someone else is willing to maintain it. Signed-off-by: Anup Patel --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2a68555ae..f200e985da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -558,6

[PATCH v6 2/3] riscv: virt: Use Goldfish RTC device

We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/

Re: [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device

On Wed, Nov 6, 2019 at 4:54 AM Philippe Mathieu-Daudé wrote: > > Hi Anup, > > On 11/3/19 8:55 AM, Anup Patel wrote: > > This patch adds model for Google Goldfish virtual platform RTC device. > > > > We will be adding Goldfish RTC device to the QEMU RISC-V virt machi

[PATCH 3/4] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel --- hw/riscv/sifive_e.c| 2 +- hw/riscv/sifive_plic.c | 24

[PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets

HARTs per socket. In future, this limits can be changed. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 206 --- include/hw/riscv/spike.h | 8 +- 2 files changed, 133 insertions(+), 81 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spik

[PATCH 0/4] RISC-V multi-socket support

: https://github.com/avpatel/linux.git Anup Patel (4): hw/riscv: Allow creating multiple instances of CLINT hw/riscv: spike: Allow creating multiple sockets hw/riscv: Allow creating multiple instances of PLIC hw/riscv: virt: Allow creating multiple sockets hw/riscv/sifive_clint.c

[PATCH 1/4] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel --- hw/riscv/sifive_clint.c | 20 hw/riscv/sifive_e.c | 2

[PATCH 4/4] hw/riscv: virt: Allow creating multiple sockets

minimum 2 HARTs per socket. In future, this limits can be changed. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 495 ++-- include/hw/riscv/virt.h | 12 +- 2 files changed, 283 insertions(+), 224 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/vir

RE: [PATCH 0/4] RISC-V multi-socket support

> -Original Message- > From: Alistair Francis > Sent: 20 May 2020 02:50 > To: Anup Patel > Cc: Peter Maydell ; Palmer Dabbelt > ; Alistair Francis ; Sagar > Karandikar ; Atish Patra ; > open list:RISC-V ; qemu-devel@nongnu.org > Developers ; Anup Patel >

Re: [PATCH v2 1/2] target/riscv: Emulate TIME CSRs for privileged mode

On Thu, Jan 30, 2020 at 8:14 PM Palmer Dabbelt wrote: > > On Wed, 22 Jan 2020 11:30:31 GMT (+0000), Anup Patel wrote: > > Currently, TIME CSRs are emulated only for user-only mode. This > > patch add TIME CSRs emulation for privileged mode. > > > > For privileged m

Re: [PATCH v2 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

On Thu, Jan 30, 2020 at 8:19 PM Palmer Dabbelt wrote: > > On Wed, 22 Jan 2020 11:30:36 GMT (+0000), Anup Patel wrote: > > This patch extends CLINT emulation to provide rdtime callback for > > TCG. This rdtime callback will be called wheneven TIME CSRs are > >

[PATCH v3 0/2] RISC-V TIME CSR for privileged mode

-v0.5.1 branch of https://github.com/kvm-riscv/qemu.git and can be found in riscv_time_csr_v3 branch of same repo. Changes since v2: - Register CLINT rdtime callback only for QEMU RISC-V virt machine Changes since v1: - Use braces for single-line if-statements Anup Patel (2): target/riscv

[PATCH v3 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation

This patch extends CLINT emulation to provide rdtime callback for TCG. This rdtime callback will be called wheneven TIME CSRs are read in privileged modes. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/sifive_clint.c | 6 +- hw/riscv/sifive_e.c

[PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode

not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 5 +++ target/riscv

RE: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.

Hi, Yes, indeed this has to be fixed in QEMU, Xvisor and KVM. Before fixing Xvisor and KVM, we have to first fix this in QEMU. For Xvisor RISC-V, feel free to send patch to xvisor-de...@googlegroups.com For KVM RISC-V, I will update it in v11 patch series and KVM RISC-V git repo as well. Regar

RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets

> -Original Message- > From: Palmer Dabbelt > Sent: 22 May 2020 01:46 > To: Anup Patel > Cc: Peter Maydell ; Alistair Francis > ; sag...@eecs.berkeley.edu; Atish Patra > ; a...@brainfault.org; qemu-ri...@nongnu.org; > qemu-devel@nongnu.org; Anup Patel >

RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets

> -Original Message- > From: Alistair Francis > Sent: 27 May 2020 06:08 > To: Anup Patel > Cc: Palmer Dabbelt ; Peter Maydell > ; qemu-ri...@nongnu.org; > sag...@eecs.berkeley.edu; a...@brainfault.org; qemu-devel@nongnu.org; > Atish Patra ; Alistair Francis >

RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets

> -Original Message- > From: Alistair Francis > Sent: 27 May 2020 09:00 > To: Anup Patel > Cc: Palmer Dabbelt ; Peter Maydell > ; qemu-ri...@nongnu.org; > sag...@eecs.berkeley.edu; a...@brainfault.org; qemu-devel@nongnu.org; > Atish Patra ; Alistair Francis >

[PATCH v2 2/5] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20

[PATCH v2 5/5] hw/riscv: virt: Allow creating multiple sockets

ut this limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 498 ++-- include/hw/riscv/virt.h | 10 +- 2 files changed, 284 insertions(+), 224 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 421815081d..0c04a5

[PATCH v2 0/5] RISC-V multi-socket support

sub-option was specified - Remove SPIKE_CPUS_PER_SOCKET_MIN and SPIKE_CPUS_PER_SOCKET_MAX in PATCH3 - Remove VIRT_CPUS_PER_SOCKET_MIN and VIRT_CPUS_PER_SOCKET_MAX in PATCH5 Anup Patel (5): hw: Add sockets_specified field in CpuTopology hw/riscv: Allow creating multiple instances of CLINT

[PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology

"sockets" sub-option is not specified. To achieve this, we add boolean flag sockets_specified in struct CpuTopology which tells machine emulation whether the "sockets" sub-option was specified in command-line. Signed-off-by: Anup Patel --- hw/core/machine.c | 2 ++ includ

[PATCH v2 4/5] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c| 2

[PATCH v2 3/5] hw/riscv: spike: Allow creating multiple sockets

be changed in future. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 210 --- include/hw/riscv/spike.h | 6 +- 2 files changed, 136 insertions(+), 80 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d5e0103d89..e0bff23a23 1

RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology

> -Original Message- > From: Daniel P. Berrangé > Sent: 27 May 2020 14:16 > To: Anup Patel > Cc: Eduardo Habkost ; Marcel Apfelbaum > ; Peter Maydell ; > Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Atish Patra ; qemu-ri...@nongnu.org; qemu- >

RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology

> -Original Message- > From: Daniel P. Berrangé > Sent: 27 May 2020 15:21 > To: Anup Patel > Cc: Eduardo Habkost ; Marcel Apfelbaum > ; Peter Maydell ; > Palmer Dabbelt ; Alistair Francis > ; Sagar Karandikar ; > Atish Patra ; qemu-ri...@nongnu.org; qemu- >

RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology

> -Original Message- > From: Daniel P. Berrangé > Sent: 27 May 2020 16:12 > To: Anup Patel > Cc: Peter Maydell ; qemu-ri...@nongnu.org; > Eduardo Habkost ; Sagar Karandikar > ; Anup Patel ; qemu- > de...@nongnu.org; Atish Patra ; Alistair Francis > ; Pa

[PATCH v3 0/4] RISC-V multi-socket support

in PATCH3 - Remove VIRT_CPUS_PER_SOCKET_MIN and VIRT_CPUS_PER_SOCKET_MAX in PATCH5 Anup Patel (4): hw/riscv: Allow creating multiple instances of CLINT hw/riscv: spike: Allow creating multiple sockets hw/riscv: Allow creating multiple instances of PLIC hw/riscv: virt: Allow creating multipl

[PATCH v3 2/4] hw/riscv: spike: Allow creating multiple sockets

-smp" command-line option. Currently, we only allow creating upto maximum 4 sockets but this limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 269 ++- include/hw/riscv/spike.h | 13 +- 2 files changed, 195 insertions(+

[PATCH v3 1/4] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20

[PATCH v3 3/4] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c| 2

[PATCH v3 4/4] hw/riscv: virt: Allow creating multiple sockets

"-smp" command-line option. Currently, we only allow creating upto maximum 4 sockets but this limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 523 +++- include/hw/riscv/virt.h | 11 +- 2 files changed, 31

RE: [PATCH v3 4/4] hw/riscv: virt: Allow creating multiple sockets

> -Original Message- > From: Atish Patra > Sent: 28 May 2020 07:14 > To: Anup Patel > Cc: Peter Maydell ; Palmer Dabbelt > ; Alistair Francis ; Sagar > Karandikar ; Atish Patra ; > qemu-ri...@nongnu.org; qemu-devel@nongnu.org; Anup Patel > > Subject: Re:

[PATCH v4 0/4] RISC-V multi-socket support

ed PATCH1 for knowning whether "sockets" sub-option was specified - Remove SPIKE_CPUS_PER_SOCKET_MIN and SPIKE_CPUS_PER_SOCKET_MAX in PATCH3 - Remove VIRT_CPUS_PER_SOCKET_MIN and VIRT_CPUS_PER_SOCKET_MAX in PATCH5 Anup Patel (4): hw/riscv: Allow creating multiple instances of CLINT

[PATCH v4 2/4] hw/riscv: spike: Allow creating multiple NUMA sockets

ample2: For two NUMA nodes with 3 and 5 CPUs, append following to command-line options: "-smp 8 -numa node,cpus=0-2 -numa node,3-7" Signed-off-by: Anup Patel --- hw/riscv/spike.c | 381 +-- include/hw/riscv/spike.h | 15 +- 2 files changed, 29

[PATCH v4 1/4] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20

[PATCH v4 3/4] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c| 2

[PATCH v4 4/4] hw/riscv: virt: Allow creating multiple NUMA sockets

quot; Example2: For two NUMA nodes with 3 and 5 CPUs, append following to command-line options: "-smp 8 -numa node,cpus=0-2 -numa node,3-7" Signed-off-by: Anup Patel --- hw/riscv/virt.c | 634 +--- include/hw/riscv/virt.h | 13 +- 2 files c

Re: [PATCH v4 2/4] hw/riscv: spike: Allow creating multiple NUMA sockets

On Thu, May 28, 2020 at 8:35 PM Igor Mammedov wrote: > > On Thu, 28 May 2020 18:59:57 +0530 > Anup Patel wrote: > > > We extend RISC-V spike machine to allow creating a multi-socket machine. > > Each RISC-V spike machine socket is a NUMA node having a set of HARTs, >

[PATCH v5 0/5] RISC-V multi-socket support

t;sockets" sub-option was specified - Remove SPIKE_CPUS_PER_SOCKET_MIN and SPIKE_CPUS_PER_SOCKET_MAX in PATCH3 - Remove VIRT_CPUS_PER_SOCKET_MIN and VIRT_CPUS_PER_SOCKET_MAX in PATCH5 Anup Patel (5): hw/riscv: Allow creating multiple instances of CLINT hw/riscv: Allow creating multiple in

[PATCH v5 1/5] hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 20

[PATCH v5 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets

limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 268 ++- include/hw/riscv/spike.h | 11 +- 2 files changed, 187 insertions(+), 92 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d5e0103d89..b8373eb1eb

[PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel --- hw/riscv/Makefile.objs | 1 + hw/riscv/numa.c | 242 include/hw/riscv/numa.h | 51 + 3 files changed, 294 insertions(+) create mode 100644 hw

[PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets

ine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 530 +++- include/hw/riscv/virt.h | 9 +- 2 files changed, 308 insertions(+), 231 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 42181508

[PATCH v5 2/5] hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c| 2

Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

On Wed, Jul 14, 2021 at 11:41 AM Alistair Francis wrote: > > On Tue, Jul 13, 2021 at 2:06 PM Anup Patel wrote: > > > > On Fri, Jul 9, 2021 at 9:01 AM Alistair Francis > > wrote: > > > > > > Instead of using riscv_cpu_update_mip() let's instead use

[PATCH v2 0/4] QEMU RISC-V ACLINT Support

: - Split PATCH1 into two patches where one patch renames CLINT sources and another patch updates the implementation - Addressed comments from Alistar and Bin Anup Patel (4): hw/intc: Rename sifive_clint sources to riscv_aclint sources hw/intc: Upgrade the SiFive CLINT implementation to

[PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation

We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 521 ++-- 1 file changed, 324 insertions

[PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources

We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel --- hw/intc/Kconfig| 2 +- hw/intc/meson.build| 2 +- hw/intc/{sifive_cl

[PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel --- hw/intc/riscv_aclint.c

[PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine

We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel --- hw/riscv/virt.c | 113 +++- include/hw/riscv/virt.h | 2 + 2 files ch

Re: [PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Fri, Aug 6, 2021 at 7:55 AM Bin Meng wrote: > > On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote: > > > > The RISC-V ACLINT is more modular and backward compatible with > > original SiFive CLINT so instead of duplicating the original > > SiFive CLINT impleme

Re: [PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine

On Fri, Aug 6, 2021 at 8:00 AM Bin Meng wrote: > > On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote: > > > > We extend virt machine to emulate ACLINT devices only when "aclint=on" > > parameter is passed along with machine name in QEMU command-line.

[PATCH v3 0/4] QEMU RISC-V ACLINT Support

: - Addresed nit comments in PATCH2 - Update SSWI device emulation to match final ACLINT draft specification Changes since v1: - Split PATCH1 into two patches where one patch renames CLINT sources and another patch updates the implementation - Addressed comments from Alistar and Bin Anup

[PATCH v3 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources

We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/Kconfig| 2 +- hw/intc/meson.

[PATCH v3 3/4] hw/riscv: virt: Re-factor FDT generation

We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/virt.c | 521

[PATCH v3 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel --- hw/intc/riscv_aclint.c

[PATCH v3 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine

We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/riscv/virt.rst | 10 hw/riscv/virt.c

Re: [PATCH v3 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Mon, Aug 30, 2021 at 11:29 AM Alistair Francis wrote: > > On Sun, Aug 29, 2021 at 3:01 PM Anup Patel wrote: > > > > The RISC-V ACLINT is more modular and backward compatible with > > original SiFive CLINT so instead of duplicating the original > > SiFive CLINT

[PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources

We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/Kconfig| 2 +- hw/intc/meson.

[PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

[PATCH v4 0/4] QEMU RISC-V ACLINT Support

e one patch renames CLINT sources and another patch updates the implementation - Addressed comments from Alistar and Bin Anup Patel (4): hw/intc: Rename sifive_clint sources to riscv_aclint sources hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-facto

[PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation

We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/virt.c | 527

[PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine

We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/riscv/virt.rst | 10 hw/riscv/virt.c

Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs

On Fri, Jun 11, 2021 at 4:46 AM Alistair Francis wrote: > > On Sat, May 15, 2021 at 12:35 AM Anup Patel wrote: > > > > We add experimental CPU feature to enable AIA CSRs. This experimental > > feature can be enabled by setting "x-aia=true" for CPU in th

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis wrote: > > On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: > > > > We implement various AIA local interrupt CSRs for M-mode, HS-mode, > > and VS-mode. > > > > Signed-off-by: Anup Patel > >

Re: [PATCH 0/4] AIA local interrupt CSR support

Hi Alistair, On Fri, May 14, 2021 at 8:03 PM Anup Patel wrote: > > The advanced interrupt architecture (AIA) extends the per-HART local > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > and Advanced PLIC (wired interrupt controller). > > Th

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

On Fri, Jun 11, 2021 at 2:16 PM Alistair Francis wrote: > > On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: > > > > On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis > > wrote: > > > > > > On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: >

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