This series adds emulation of TIME CSRs for privileged mode. With this series, we see approximately 25+% improvement in hackbench numbers for non-virtualized (or Host) Linux and 40+% improvement in hackbench numbers for Guest/VM Linux.
These patches are based on mainline/alistair/riscv-hyp-ext-v0.5.1 branch of https://github.com/kvm-riscv/qemu.git and can be found in riscv_time_csr_v3 branch of same repo. Changes since v2: - Register CLINT rdtime callback only for QEMU RISC-V virt machine Changes since v1: - Use braces for single-line if-statements Anup Patel (2): target/riscv: Emulate TIME CSRs for privileged mode hw/riscv: Provide rdtime callback for TCG in CLINT emulation hw/riscv/sifive_clint.c | 6 ++- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 9 ++-- hw/riscv/virt.c | 2 +- include/hw/riscv/sifive_clint.h | 3 +- target/riscv/cpu.h | 5 ++ target/riscv/cpu_helper.c | 5 ++ target/riscv/csr.c | 86 +++++++++++++++++++++++++++++++-- 9 files changed, 108 insertions(+), 12 deletions(-) -- 2.17.1
