[PATCH 0/5] Nested virtualization fixes for QEMU

This series mainly includes fixes discovered while developing nested virtualization running on QEMU. These patches can also be found in the riscv_nested_fixes_v1 branch at: https://github.com/avpatel/qemu.git Anup Patel (5): target/riscv: Typo fix in sstc() predicate target/riscv: Update VS

[PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions

as zero in htinst CSR for guest MMIO emulation which makes MMIO emulation in hypervisor slow and also breaks nested virtualization. Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") Signed-off-by: Anup Patel --- target/riscv/insn_trans/trans_rva.c.in

[PATCH 1/5] target/riscv: Typo fix in sstc() predicate

We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP

Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 2 -- ta

[PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX

The time CSR will wrap-around immediately after reaching UINT64_MAX so we don't need to re-start QEMU timer when timecmp == UINT64_MAX in riscv_timer_write_timecmp(). Signed-off-by: Anup Patel --- target/riscv/time_helper.c | 8 1 file changed, 8 insertions(+) diff --git a/t

[PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes

The htimedelta[h] CSR has impact on the VS timer comparison so we should call riscv_timer_write_timecmp() whenever htimedelta changes. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel --- target/riscv/csr.c | 16 1 file changed, 16

Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote: > > On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis wrote: > > > > On Thu, May 26, 2022 at 8:12 PM Anup Patel wrote: > > > > > > We should write transformed instruction encoding of the trapped > >

Re: [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Mon, Jun 6, 2022 at 7:25 AM Alistair Francis wrote: > > On Thu, May 26, 2022 at 8:09 PM Anup Patel wrote: > > > > We should disable extensions in riscv_cpu_realize() if minimum required > > priv spec version is not satisfied. This also ensures that machines with >

Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Tue, Jun 7, 2022 at 8:31 AM Anup Patel wrote: > > On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote: > > > > On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis > > wrote: > > > > > > On Thu, May 26, 2022 at 8:12 PM Anup Patel > > >

[PATCH v4 1/4] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v4 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Pat

[PATCH v4 0/4] QEMU RISC-V nested virtualization fixes

sfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): target/riscv: Don't force update priv spec version to latest target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher target/riscv: Update [m|h]tinst CSR in riscv_cpu_d

[PATCH v4 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 3 + target/riscv/cpu_helper.c | 231

[PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match

o the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 57 ++ 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f9c27a3f5..953ba2e445 100644 --- a/target/riscv/cpu.c ++

Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Wed, Jun 8, 2022 at 10:23 PM Richard Henderson wrote: > > On 6/8/22 09:14, Anup Patel wrote: > > +struct isa_ext_data isa_edata_arr[] = { > > static const? Using const is fine but we can't use "static const" because the "struct isa_ext_data" has

[PATCH v5 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which is always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off

[PATCH v5 1/4] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v5 0/4] QEMU RISC-V nested virtualization fixes

patches in this series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): target/riscv: Don't force update priv spec version to latest ta

[PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 3 + target/riscv/cpu_helper.c | 231

[PATCH v5 4/4] target/riscv: Force disable extensions if priv spec version does not match

gs to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 57 ++ 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f9c27a3f5..e7eb65d708 100644 --- a/target/riscv/cpu.c ++

Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Thu, Jun 9, 2022 at 7:28 PM Richard Henderson wrote: > > On 6/8/22 20:16, Anup Patel wrote: > > On Wed, Jun 8, 2022 at 10:23 PM Richard Henderson > > wrote: > >> > >> On 6/8/22 09:14, Anup Patel wrote: > >>> +struct isa_ext_data isa_edata

Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Fri, Jun 10, 2022 at 3:00 PM dramforever wrote: > > Hi Anup Patel, > > I think there are some misunderstandings of the privileged spec with regards > to > [m|h]tinst handling. Here are some possible issues I've found: > > > +case OPC_RISC_C_FUNC

Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Fri, Jun 10, 2022 at 5:20 PM dramforever wrote: > > > > >> In addition, the various V-extension vector load/store instructions do not > >> have > >> defined transformations, so they should show up in [m|h]tinst as all zeros. > > Okay, I will update. > Just a clarification/suggestion: It might

[PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 3 + target/riscv/cpu_helper.c | 214

[PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match

gs to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 144 +++-- 1 file changed, 88 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8db0f0bd49..a17bc98662 100644 --- a/target/riscv/cpu.c ++

[PATCH v6 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which is always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off

[PATCH v6 1/4] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v6 0/4] QEMU RISC-V nested virtualization fixes

new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): target/riscv: Don't force update priv spec version to latest target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() targe

[PATCH 2/2] target/riscv: Update default priority table for local interrupts

(not mandatory) priority assignments. We update the default priority table and hviprio mapping as-per above. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 2 +- target/riscv/cpu_helper.c | 134 ++ 2 files changed, 66 insertions(+), 70

[PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V

can be found at: riscv_aia_update_v1 branch of https://github.com/avpatel/opensbi.git riscv_aia_v1 branch of https://github.com/avpatel/linux.git Anup Patel (2): target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits target/riscv: Update default priority table for local

[PATCH 1/2] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits

software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC CSR emulation as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 24 +-- target

Re: [PATCH v5 2/3] target/riscv: Add stimecmp support

On Thu, Jun 16, 2022 at 8:08 AM Alistair Francis wrote: > > On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra wrote: > > > > On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis > > wrote: > > > > > > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote: > > > > > > > > On Thu, Jun 2, 2022 at 12:02 AM

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > should call riscv_timer_write_timecmp() whenever htimedelta changes. > > &g

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis wrote: > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > > > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis > > wrote: > > > > > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel > > &g

Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test

On Thu, Dec 22, 2022 at 6:27 PM Bin Meng wrote: > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > wrote: > > > > > > > > On 12/22/22 07:24, Bin Meng wrote: > > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > > wrote: > > >> This test is used to do a quick sanity check t

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote: > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote: > > > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis > > wrote: > > > > > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: >

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

Hi Alistair, On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote: > > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote: > > > > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis > > wrote: > > > > > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel &

Re: [PATCH v2 1/2] target/riscv: Convert sdtrig functionality from property to an extension

On Wed, Jan 17, 2024 at 7:54 PM Himanshu Chauhan wrote: > > The debug trigger (sdtrig) capability is controlled using the debug property. > The sdtrig is an ISA extension and should be treated so. The sdtrig extension > may or may not be implemented in a system. Therefore, it must raise an illegal

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

On Sun, Mar 6, 2022 at 11:06 AM Frank Chang wrote: > > On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra wrote: >> >> >> >> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote: >>> >>> Hi, >>> >>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra: >>> > On Fri, Feb 25, 2022 at 11:46

Re: QEMU+KVM on RISC-V + Hypervisor Extension

On Tue, Mar 15, 2022 at 12:18 PM Alistair Francis wrote: > > On Sun, Mar 13, 2022 at 12:12 PM Ralf Ramsauer > wrote: > > > > Hi, > > > > I'm trying to run Linux/QEMU+KVM inside an emulated > > qemu-system-riscv64 VM (x86 host). On latest&greatest QEMU (1416688c53), > > I run Linux inside QEMU. On

Re: [EXT] Re: QEMU+KVM on RISC-V + Hypervisor Extension

On Tue, Mar 15, 2022 at 5:47 PM Ralf Ramsauer wrote: > > > > On 15/03/2022 09:33, Anup Patel wrote: > > On Tue, Mar 15, 2022 at 12:18 PM Alistair Francis > > wrote: > >> > >> On Sun, Mar 13, 2022 at 12:12 PM Ralf Ramsauer > >> wrote: > >

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

On Wed, Feb 16, 2022 at 9:18 PM Christoph Muellner wrote: > > The RISC-V base cache management operation ISA extension has been > ratified. This patch adds support for the defined instructions. > > The cmo.prefetch instructions are nops for QEMU (no emulation of the memory > hierarchy, no illegal

Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension

+Atish On Mon, Jul 18, 2022 at 9:23 AM Jim Shu wrote: > > RISC-V priv spec v1.12 permits 2 PTE-update schemes of A/D-bit > (Access/Dirty bit): HW update or SW update. RISC-V profile defines the > extension name 'Ssptwad' for HW update to PTE A/D bits. > https://github.com/riscv/riscv-profiles/blo

Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension

ancis might have better suggestions on this ? Regards, Anup > > Regards, > Jim Shu > > On Mon, Jul 18, 2022 at 12:02 PM Anup Patel wrote: >> >> +Atish >> >> On Mon, Jul 18, 2022 at 9:23 AM Jim Shu wrote: >> > >> > RISC-V priv spec v1.12

Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

On Tue, May 24, 2022 at 3:22 AM Alistair Francis wrote: > > On Fri, May 20, 2022 at 1:07 AM Anup Patel wrote: > > > > On Tue, May 17, 2022 at 5:46 AM Alistair Francis > > wrote: > > > > > > On Thu, May 12, 2022 at 12:52 AM Anup Patel > > >

Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Tue, May 24, 2022 at 3:08 AM Alistair Francis wrote: > > On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote: > > > > We should write transformed instruction encoding of the trapped > > instruction in [m|h]tinst CSR at time of taking trap as defined > > by the R

[PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v3 0/4] QEMU RISC-V nested virtualization fixes

series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): target/riscv: Don't force update priv spec version to latest target/riscv: Add dum

[PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match

o the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 56 +- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b086eb25da..e6e878ceb3 100644 --- a/target/riscv/cpu.c ++

[PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 210 +- target/riscv

[PATCH v3 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Pat

Re: [PATCH] target/riscv: fix priv enum

On Thu, May 26, 2022 at 2:15 PM Nikita Shubin wrote: > > From: Nikita Shubin > > Add PRIV_VERSION_UNKNOWN to enum, otherwise PRIV_VERSION_1_10_0 will > be overwritten to PRIV_VERSION_1_12_0 in riscv_cpu_realize. > > Fixes: a46d410c5c ("target/riscv: Define simpler privileged spec version > numbe

Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts

On Fri, Oct 15, 2021 at 11:54 AM Alistair Francis wrote: > > On Thu, Sep 16, 2021 at 11:42 PM Anup Patel wrote: > > > > On Wed, Sep 15, 2021 at 6:19 AM Alistair Francis > > wrote: > > > > > > On Tue, Sep 14, 2021 at 2:33 AM Anup Patel wrote: >

Re: [PATCH v3] hw/riscv: virt: Exit if the user provided -bios in combination with KVM

user. > > Signed-off-by: Ralf Ramsauer Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > hw/riscv/virt.c | 14 ++ > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index da50cbed43..0960

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis wrote: > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > From: Frank Chang > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > Signed-off-by: Frank Chang > > Reviewed-by: Jim Shu > > --

Re: [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > linux-headers/

Re: [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

is Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > meson.build | 2 + > target/riscv/kvm.c | 133 +++ > target/riscv/meson.build | 1 + > 3 files changed, 136 insertions(+) > create mode 100644 target/r

Re: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis > --- > target/riscv/kvm.c | 150 - > 1

Re: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis > --- > target/riscv/kvm.c | 141 - > 1 fi

Re: [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Get kernel and fdt start address in virt.c, and pass them to KVM > when cpu reset. In addition, add kvm_riscv.h to place riscv specific > interface. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis

Re: [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Extend riscv_cpu_update_mip() to support setting external interrupt > by KVM. It will call kvm_riscv_set_irq() to change the IRQ state in > the KVM module When kvm is enabled and the MIP_SEIP bit is set in "mask" > > In addition, bacause targe

Re: [PATCH v1 09/12] target/riscv: Add host cpu type

Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > target/riscv/cpu.c | 15 +++ > target/riscv/cpu.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a464845c99..6512182c62 100644 &

Re: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote: > > Add kvm_riscv_get/put_regs_timer to synchronize virtual time context > from KVM. > > To set register of RISCV_TIMER_REG(state) will occur a error from KVM > on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter > that ada

Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback

On Thu, Nov 4, 2021 at 10:23 AM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 6:00 PM Anup Patel wrote: > > > > The AIA device emulation (such as AIA IMSIC) should be able to set > > (or provide) AIA ireg read-modify-write callback for each privilege &g

Re: [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

On Thu, Nov 4, 2021 at 10:13 AM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 5:10 PM Anup Patel wrote: > > > > The AIA specification adds new CSRs for RV32 so that RISC-V hart can > > support 64 local interrupts on both RV32 and RV64. > > > > Signed-off

Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs

On Thu, Nov 4, 2021 at 10:19 AM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 5:39 PM Anup Patel wrote: > > > > The AIA hvictl and hviprioX CSRs allow hypervisor to control > > interrupts visible at VS-level. This patch implements AIA hvictl > > and hvipri

Re: [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs

On Thu, Nov 4, 2021 at 10:26 AM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 6:08 PM Anup Patel wrote: > > > > The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs > > which allow indirect access to interrupt priority arrays and per-HART > &g

[PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2

[PATCH v5 00/23] QEMU RISC-V AIA support

msic" are not valid vendor names required by Linux DT schema checker. Changes since v2: - Update PATCH4 to check and inject interrupt after V=1 when transitioning from V=0 to V=1 Changes since v1: - Revamped whole series and created more granular patches - Added HGEIE and HGEIP CSR emulati

[PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 61

[PATCH v5 06/23] target/riscv: Add AIA cpu feature

We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3

[PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 13 +++-- 1 file changed, 11

[PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++--- 3 files changed, 16

[PATCH v5 07/23] target/riscv: Add defines for AIA CSRs

The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 127 1 file changed, 127 insertions(+) diff --git a/target/riscv

[PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 126 + target/riscv

[PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts

console input and other I/O events. To solve this, we check and inject interrupt after setting V=1. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv

[PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 23 +++ target/riscv/cpu_helper.c | 14 ++ 2

[PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel --- hw/riscv/Kconfi

[PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c| 560

[PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

devices expect AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 +++ target/riscv/cpu.h | 5 + 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities

. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 19 target/riscv/cpu.h| 12 ++ target/riscv/cpu_helper.c | 231 ++ target/riscv/machine.c| 3 + 4 files changed, 244 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.c b

[PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel --- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/riscv_imsic.c | 447 ++ include

[PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 7 ++ target/riscv/csr.c

[PATCH v5 22/23] docs/system: riscv: Document AIA options for virt machine

We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- docs/system/riscv/virt.rst | 16 1 file changed, 16 insertions(+)

[PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs

12 so we add dummy implementation (i.e. read zero and ignore write) of AIA interrupt filtering CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c

[PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel --- target/riscv/csr.c | 155 + 1 file changed, 155 insertions(+) diff --git a/target/riscv/csr.c b

[PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel --- hw

[PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs

The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel --- target/riscv/csr.c | 202

[PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 + target/riscv/cpu.

[PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

adds device emulation for RISC-V AIA APLIC. Signed-off-by: Anup Patel --- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/riscv_aplic.c | 970 ++ include/hw/intc/riscv_aplic.h | 79 +++ 4 files changed, 1053 insertions

[PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

SIs to the AIA IMSIC. We also provide "aia-guests=" parameter which can be used to specify number of VS-level AIA IMSIC Guests MMIO pages for each HART. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 434 --

Re: [PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Get isa info from kvm while kvm init. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- >

Re: [PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis Looks good to me. Reviewed-by: Anup Patel Regards, Anup >

Re: [PATCH v2 05/12] target/riscv: Implement kvm_arch_put_registers

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis Looks good to me. Reviewed-by: Anup Patel Regards, Anup >

Re: [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Get kernel and fdt start address in virt.c, and pass them to KVM > when cpu reset. In addition, add kvm_riscv.h to place riscv specific > interface. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis

Re: [PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > When KVM is enabled, set the S-mode external interrupt through > kvm_riscv_set_irq function. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 6 +- > target

Re: [PATCH v2 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Use char-fe to handle console sbi call, which implement early > console io while apply 'earlycon=sbi' into kernel parameters. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li Looks good to me. Revie

Re: [PATCH v2 12/12] target/riscv: Support virtual time context synchronization

= { > &vmstate_hyper, > &vmstate_vector, > &vmstate_pointermasking, > +&vmstate_kvmtimer, > NULL > } > }; > -- > 2.19.1 > > > -- > kvm-riscv mailing list > kvm-ri...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv Otherwise, it looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 11/12] target/riscv: Implement virtual time adjusting with vm state changing

t and kvm_timer should be restored. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > target/riscv/kvm.c | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git a/target/r

Re: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote: > > Add kvm_riscv_get/put_regs_timer to synchronize virtual time context > from KVM. > > To set register of RISCV_TIMER_REG(state) will occur a error from KVM > on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter > that ada

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