On Thu, Nov 4, 2021 at 10:26 AM Alistair Francis <alistai...@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 6:08 PM Anup Patel <anup.pa...@wdc.com> wrote:
> >
> > The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> > which allow indirect access to interrupt priority arrays and per-HART
> > IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
> >
> > Signed-off-by: Anup Patel <anup.pa...@wdc.com>
> > ---
> > target/riscv/cpu.h | 7 ++
> > target/riscv/csr.c | 174 +++++++++++++++++++++++++++++++++++++++++
> > target/riscv/machine.c | 3 +
> > 3 files changed, 184 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 21d9c536ef..bf688eb1ea 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -183,6 +183,10 @@ struct CPURISCVState {
> > uint8_t miprio[64];
> > uint8_t siprio[64];
> >
> > + /* AIA CSRs */
> > + target_ulong miselect;
> > + target_ulong siselect;
> > +
> > /* Hypervisor CSRs */
> > target_ulong hstatus;
> > target_ulong hedeleg;
> > @@ -212,6 +216,9 @@ struct CPURISCVState {
> > target_ulong vstval;
> > target_ulong vsatp;
> >
> > + /* AIA VS-mode CSRs */
> > + target_ulong vsiselect;
> > +
> > target_ulong mtval2;
> > target_ulong mtinst;
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 69e857d1e5..e72220fd0f 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -854,6 +854,168 @@ static int read_mtopi(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_cpu_virt_enabled(env)) {
> > + return csrno;
> > + }
> > +
> > + switch (csrno) {
> > + case CSR_SISELECT:
> > + return CSR_VSISELECT;
> > + case CSR_SIREG:
> > + return CSR_VSIREG;
> > + default:
> > + return csrno;
> > + };
> > +}
> > +
> > +static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + target_ulong *iselect;
> > +
> > + /* Translate CSR number for VS-mode */
> > + csrno = aia_xlate_vs_csrno(env, csrno);
> > +
> > + /* Find the iselect CSR based on CSR number */
> > + switch (csrno) {
> > + case CSR_MISELECT:
> > + iselect = &env->miselect;
> > + break;
> > + case CSR_SISELECT:
> > + iselect = &env->siselect;
> > + break;
> > + case CSR_VSISELECT:
> > + iselect = &env->vsiselect;
> > + break;
> > + default:
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + };
> > +
> > + if (val) {
> > + *val = *iselect;
> > + }
> > +
> > + wr_mask &= ISELECT_MASK;
> > + if (wr_mask) {
> > + *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int rmw_iprio(target_ulong iselect, uint8_t *iprio,
> > + target_ulong *val, target_ulong new_val,
> > + target_ulong wr_mask, int ext_irq_no)
> > +{
> > + int i, firq, nirqs;
> > + target_ulong old_val;
> > +
> > + if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
> > + return -EINVAL;
> > + }
> > +#if TARGET_LONG_BITS == 64
> > + if (iselect & 0x1) {
> > + return -EINVAL;
> > + }
> > +#endif
> > +
> > + nirqs = 4 * (TARGET_LONG_BITS / 32);
> > + firq = ((iselect - ISELECT_IPRIO0) / (TARGET_LONG_BITS / 32)) *
> > (nirqs);
>
> Don't use TARGET_LONG_BITS, this should be checked at runtime instead
Okay, I will update this.
Regards,
Anup
>
> Alistair
