[PATCH v9 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

[PATCH v9 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3

[PATCH v9 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 119

[PATCH v9 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank

[PATCH v9 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v9 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by

[PATCH v9 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis R

[PATCH v9 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v9 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v9 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang --- target/riscv/csr.c | 156

[PATCH v9 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v9 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/s

[PATCH v9 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by

Re: [PATCH v9 00/23] QEMU RISC-V AIA support

On Tue, Feb 8, 2022 at 12:27 PM Alistair Francis wrote: > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote: > > > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote: > > > > > > From: Anup Patel > > > > > > The advanced i

Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

On Fri, Jan 14, 2022 at 5:33 PM Frank Chang wrote: > > Anup Patel 於 2021年12月30日 週四 下午8:55寫道： >> >> From: Anup Patel >> >> The RISC-V AIA (Advanced Interrupt Architecture) defines a new >> interrupt controller for wired interrupts called APLIC (Advanced &g

Re: [PATCH v3 2/3] target/riscv: add support for svinval extension

t; diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 615048ec87..4e5a9660a4 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -838,6 +838,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > #include "insn_trans/trans_rvb.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_privileged.c.inc" > +#include "insn_trans/trans_svinval.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > -- > 2.17.1 > > Apart from the minor mistake above, it looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension

add a patch before PATCH1 to add following: if (pte & (PTE_D | PTE_A | PTE_U)) { return TRANSLATE_FAIL; } The current PATCH1 should add PTE_N to the comparison and this patch can add PTE_PBMT to the comparison. > base = ppn << PGSHIFT; > } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { > /* Reserved leaf PTE flags: PTE_W */ > -- > 2.17.1 > Apart from the minor comment above, it looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v3 2/3] target/riscv: add support for svinval extension

On Fri, Jan 14, 2022 at 7:24 PM Weiwei Li wrote: > > Thanks for your comments. > > 在 2022/1/14 下午9:40, Anup Patel 写道: > > On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cp

[PATCH] hw/riscv: spike: Allow using binary firmware as bios

machine can now use OpenSBI firmware BIN as bios. Signed-off-by: Anup Patel --- hw/char/riscv_htif.c | 33 +++-- hw/riscv/spike.c | 41 ++-- include/hw/char/riscv_htif.h | 5 - include/hw/riscv/spike.h | 1 +

Re: [PATCH v4 2/4] target/riscv: add support for svnapot extension

On Sun, Jan 16, 2022 at 8:31 AM Weiwei Li wrote: > > - add PTE_N bit > - add PTE_N bit check for inner PTE > - update address translation to support 64KiB continuous region (napot_bits = > 4) > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Looks good t

[PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example

[PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.h| 14 +- target

[PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv

[PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

[PATCH v7 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 127

[PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis R

[PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v7 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia

[PATCH v7 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/s

[PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level

[PATCH v7 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3

[PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish

[PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank

[PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by

[PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang --- target/riscv/csr.c | 156

[PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c

[PATCH v7 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by

[PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Review

[PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by

[PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any

[PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > > From: Guo Ren > > Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we > need to ignore them. They cannot be a part of ppn. > > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture >4.4 Sv39: Page-Based 39-

Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > > - add PTE_N bit > - add PTE_N bit check for inner PTE > - update address translation to support 64KiB continuous region (napot_bits = > 4) > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Cc: Anup Pate

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

wei Li > Signed-off-by: Junqiang Wang > Cc: Heiko Stuebner > Cc: Anup Patel > --- > target/riscv/cpu.c| 1 + > target/riscv/cpu.h| 1 + > target/riscv/cpu_bits.h | 2 ++ > target/riscv/cpu_helper.c | 4 +++- > 4 files changed, 7 insertions(+), 1 deleti

Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities

On Tue, Jan 18, 2022 at 9:04 AM Frank Chang wrote: > > Anup Patel 於 2022年1月17日 週一 下午10:28寫道： >> >> From: Anup Patel >> >> The AIA spec defines programmable 8-bit priority for each local interrupt >> at M-level, S-level and VS-level so we extend local int

Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis wrote: > > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel wrote: > > > > Currently, we have to use OpenSBI firmware ELF as bios for the spike > > machine because the HTIF console requires ELF for parsing "fromh

Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

On Tue, Jan 18, 2022 at 11:24 AM Alistair Francis wrote: > > On Tue, Jan 18, 2022 at 3:27 PM Anup Patel wrote: > > > > On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis > > wrote: > > > > > > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel > > &g

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

On Tue, Jan 18, 2022 at 2:16 PM Guo Ren wrote: > > On Tue, Jan 18, 2022 at 11:32 AM Anup Patel wrote: > > > > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > > > > > > From: Guo Ren > > > > > > Highest bits of PTE has been used for

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

On Tue, Jan 18, 2022 at 2:40 PM Weiwei Li wrote: > > > 在 2022/1/18 上午11:35, Anup Patel 写道: > > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > >> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on > >> QEMU, since QEMU is sequentially

[PATCH v2 0/3] Improve RISC-V spike machine bios support

/qemu.git Changes since v1: - Use htif_uses_elf_symbols() in htif_mm_init() for PATCH1 - Added PATCH2 and PATCH3 to remove ELF bios images Anup Patel (3): hw/riscv: spike: Allow using binary firmware as bios hw/riscv: Remove macros for ELF BIOS image names roms/opensbi: Remove ELF images hw

[PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names

Now that RISC-V Spike machine can use BIN BIOS images, we remove the macros used for ELF BIOS image names. Signed-off-by: Anup Patel --- hw/riscv/spike.c| 4 ++-- include/hw/riscv/boot.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv

[PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios

machine can now use OpenSBI firmware BIN as bios. Signed-off-by: Anup Patel --- hw/char/riscv_htif.c | 33 +++-- hw/riscv/spike.c | 41 ++-- include/hw/char/riscv_htif.h | 5 - include/hw/riscv/spike.h | 1 +

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

On Tue, Jan 18, 2022 at 4:45 PM Guo Ren wrote: > > On Tue, Jan 18, 2022 at 4:51 PM Anup Patel wrote: > > > > On Tue, Jan 18, 2022 at 2:16 PM Guo Ren wrote: > > > > > > On Tue, Jan 18, 2022 at 11:32 AM Anup Patel wrote: > > > > > >

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

On Tue, Jan 18, 2022 at 4:45 PM Guo Ren wrote: > > On Tue, Jan 18, 2022 at 4:51 PM Anup Patel wrote: > > > > On Tue, Jan 18, 2022 at 2:16 PM Guo Ren wrote: > > > > > > On Tue, Jan 18, 2022 at 11:32 AM Anup Patel wrote: > > > > > >

[PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any

[PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang --- target/riscv/csr.c | 156

[PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank

[PATCH v8 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia

[PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level

[PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish

[PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.h| 14 +- target

[PATCH v8 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by

[PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Review

[PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled

[PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by

[PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3

[PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward

[PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example

[PATCH v8 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 119

[PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv

Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

Hi Frank, On Wed, Jan 19, 2022 at 9:07 PM Frank Chang wrote: > > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote: >> >> From: Anup Patel >> >> The RISC-V AIA (Advanced Interrupt Architecture) defines a new >> interrupt controller for wired interrupts call

[PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

[PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang

[PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signe

[PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis R

[PATCH v8 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- docs/s

[PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by

Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images

On Wed, Jan 19, 2022 at 12:26 PM Bin Meng wrote: > > On Tue, Jan 18, 2022 at 7:18 PM Anup Patel wrote: > > > > Now that all RISC-V machines can use OpenSBI BIN images, we remove > > OpenSBI ELF images and also exclude these images from BIOS build. > >

[PATCH v3 1/3] hw/riscv: spike: Allow using binary firmware as bios

machine can now use OpenSBI firmware BIN as bios. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/char/riscv_htif.c | 33 +++-- hw/riscv/spike.c | 41 ++-- include/hw/char/riscv_htif.h

[PATCH v3 2/3] hw/riscv: Remove macros for ELF BIOS image names

Now that RISC-V Spike machine can use BIN BIOS images, we remove the macros used for ELF BIOS image names. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c| 4 ++-- include/hw/riscv/boot.h | 2 -- 2 files changed, 2 insertions(+), 4

Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

On Thu, Jan 20, 2022 at 1:49 PM Frank Chang wrote: > > On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote: >> >> Hi Frank, >> >> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang wrote: >> > >> > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote: >

[PATCH v3 0/3] Improve RISC-V spike machine bios support

/qemu.git Changes since v2: - Remove ELF file names from .gitlab-ci.d/opensbi.yml in PATCH3 Changes since v1: - Use htif_uses_elf_symbols() in htif_mm_init() for PATCH1 - Added PATCH2 and PATCH3 to remove ELF bios images Anup Patel (3): hw/riscv: spike: Allow using binary firmware as bios hw

Re: [PATCH v8 00/23] QEMU RISC-V AIA support

Hi Alistair, On Wed, Jan 19, 2022 at 8:56 PM Anup Patel wrote: > > From: Anup Patel > > The advanced interrupt architecture (AIA) extends the per-HART local > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > and Advanced PLIC (wired interrupt controlle

Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs

On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 5:01 PM Anup Patel wrote: > > > > The RISC-V AIA specification extends RISC-V local interrupts and > > introduces new CSRs. This patch adds defines for the new AIA CSRs. > >

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > A hypervsior can optionally take guest external interrupts using > > typo: hypervisor Okay, I will update. > > > SGEIP bit of hip and hie CSRs.

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 4:22 PM Bin Meng wrote: > > On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote: > > > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > > > > >

[PATCH v2 1/8] target/riscv: Fix csr number based privilege checking

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, the riscv_csrrw_check() function should generate virtual instruction trap instead illegal instruction trap. Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode") Signed-off-by: Anup Patel Reviewed-by

[PATCH v2 0/8] QEMU RISC-V nested virtualization fixes

n this series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (8): target/riscv: Fix csr number based privilege checking target/riscv: Fix hsta

[PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 168 +- target/riscv

[PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

g GVA") Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2097..b16bfe0182 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1367

[PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps

mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 8 +++- target/riscv

[PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest

t latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by

[PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match

o the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3b61dfd63..25a4ba3e22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541

[PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices

: Add support for generating platform FDT entries") Signed-off-by: Anup Patel --- hw/riscv/virt.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3326f4db96..c576173815 100644 --- a/hw/riscv/virt.c +++ b/hw/ri

[PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher

The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Pat

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