On Sun, Jan 16, 2022 at 8:31 AM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> - add PTE_N bit
> - add PTE_N bit check for inner PTE
> - update address translation to support 64KiB continuous region (napot_bits =
> 4)
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
Looks good to me.
Reviewed-by: Anup Patel <a...@brainfault.org>
Regards,
Anup
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
> 4 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bc25d3055..ff6c86c85b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> +
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d63086765..d3d17cde82 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -327,6 +327,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..bc23e3b523 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,6 +486,7 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_N 0x8000000000000000 /* NAPOT translation */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d84cde424d..832a2dd79c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,14 +619,17 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>
> - if (!(pte & PTE_V)) {
> + RISCVCPU *cpu = env_archcpu(env);
> + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> + return TRANSLATE_FAIL;
> + } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> @@ -702,8 +705,17 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> - (addr & ~TARGET_PAGE_MASK);
> +
> + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
> + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
> + (napot_bits != 0 && napot_bits != 4)) {
> + return TRANSLATE_FAIL;
> + }
> +
> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << ptshift) - 1))
> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>
