Now that VFIO can unmask the interrupt autonomously through an eventfd
file descriptor, get rid of the resampler_handler.
TODO: move this code and PCI one to common.c
Signed-off-by: Alvise Rigo
---
hw/vfio/platform.c | 38 --
1 file changed, 24 insertions
igned-off-by: Alvise Rigo
---
hw/vfio/pci.c | 18 +-
hw/vfio/platform.c| 8
include/qemu/event_notifier.h | 1 +
util/event_notifier-posix.c | 24 +---
4 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/hw
m,primecell", a
clock property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
[Eric Auger]
put str_ptr in the declaration part and rename pcompat into compat
Signed-off-by: Alvise Rigo
Signed-off-by: Eric Auger
---
(eventfd_notifier_init) is added to fulfill
this purpose.
Alvise Rigo (3):
Add AMBA devices support to VFIO
Force eventfd as notifying mechanism for VFIO
Let VFIO handle the unmasking of interrupts at EOI
Eric Auger (1):
vfio: Add irqfd support in platform device
hw/arm/virt.c
ch in
near future.
This work was tested with Calxeda Midway xgmac.
Signed-off-by: Eric Auger
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 14 +
hw/intc/arm_gic_kvm.c | 1 +
hw/vfio/platform.c| 165 +-
3 files changed, 166 inserti
nsystems.com/en/solutions/guides/vfio-on-arm) will be run to
verify even further the correct behaviour of the device. This suite has been
tested with ARM FastModels.
Alvise Rigo (4):
Add EXEC_FLAG to VFIO DMA mappings
Add AMBA devices support to VFIO
MemoryRegion with EOI callbacks for VFIO
The flag is mandatory for the ARM SMMU so we always add it if the MMIO
handles it.
Signed-off-by: Alvise Rigo
---
hw/vfio/common.c | 9 +
hw/vfio/vfio-common.h | 1 +
linux-headers/linux/vfio.h | 2 ++
3 files changed, 12 insertions(+)
diff --git a/hw/vfio/common.c b/hw
m,primecell", a
clock property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt.c b
-platform,...,intclr-region="0;0x2c;4"
Signed-off-by: Alvise Rigo
---
hw/vfio/platform.c | 91 --
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
index c4a4286..ec6a29e 100644
---
When eventfd is not configured the method event_notifier_init fallbacks
to the pipe/pipe2 system call, causing an error in VFIO_DEVICE_SET_IRQS
since we pass to the kernel a file descriptor which is not created by
eventfd.
Signed-off-by: Alvise Rigo
---
hw/vfio/platform.c | 5 +
1 file
drive if=scsi,index=1,file=scsi.img \
-drive if=scsi,index=2,file=scsi_2.img ...
to attach the SCSI disks to the guest.
Thank you,
alvise
On Tue, Sep 9, 2014 at 6:35 PM, Claudio Fontana
wrote:
> On 11.07.2014 11:28, Alvise Rigo wrote:
>> The kernel version is a very recent on
The method is not behaving in the way it's supposed to. It should return
the new value only if it's less than the actual one.
Signed-off-by: Alvise Rigo
---
vmstate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/vmstate.c b/vmstate.c
index 284b080..038b
The value of this flag indicates the execution mode of the CPU prior the
migration. It is used to handle the KVM <-> TCG migration.
Signed-off-by: Alvise Rigo
---
target-arm/cpu-qom.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
Since the irq bit seems to not be updated, exclude it from the check done
while copying data during migration.
Signed-off-by: Alvise Rigo
---
target-arm/cpu.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index
astModels and the ARM Chromebook. Then, in the middle of the kernel
boot, the guest was migrated to a x86 host running TCG.
The machine model used is vexpress-a15 with cortex-a15 as CPU.
Alvise Rigo (4):
Fix issue affecting get_int32_le() in vmstate.c
Added flag in ARMCPU to track last execution
registers with the
cpreg_list keeping a list of the registers that do not succeeded the
match.
* handle_cpreg_kvm2tcg_migration(): try to solve the mismatch of
cp registers coming from KVM; without this additional step the
migration would fail even if it's feasible.
Signed-off-
f the process.
thanks,
alvise
On Tue, Feb 25, 2014 at 7:19 PM, Peter Maydell wrote:
> On 25 February 2014 16:52, Alvise Rigo
> wrote:
> > The value of this flag indicates the execution mode of the CPU prior the
> > migration. It is used to handle the KVM <-> TCG migration.
:52, Alvise Rigo
> wrote:
> > Since the irq bit seems to not be updated, exclude it from the check done
> > while copying data during migration.
> >
> > Signed-off-by: Alvise Rigo
> > ---
> > target-arm/cpu.c | 22 ++
> >
at 7:25 PM, Peter Maydell wrote:
> On 25 February 2014 16:52, Alvise Rigo
> wrote:
> > CPUARMState:
> > * added adfsr cp register.
> > * added aifsr cp register.
> > These registers have been added because they are migrated by KVM. This
> prevents
> > the mig
register which is migrated in a
wildcarded case) could be considered to handle the migration.
alvise
On Wed, Feb 26, 2014 at 11:04 AM, Peter Maydell wrote:
> On 26 February 2014 10:02, alvise rigo
> wrote:
> > I agree that this is a sort of workaround, but it seems to me that
user pointer, allowing to not call the IOMMU callbacks for
these regions, but rather to access the memory directly.
Signed-off-by: Alvise Rigo
---
exec.c| 2 +-
include/exec/memory.h | 16
memory.c | 14 ++
memory_mapping.c | 2 +-
4
ng that we will see in a
future version of VFIO for platform devices).
These patches are based on the QEMU branch mentioned in the original
thread ("[Qemu-devel] [RFC v2 0/6] KVM platform device passthrough").
Alvise Rigo (4):
Allocate non-RAM MemoryRegion from user pointer
Add E
-platform,...,intclr-region="0;0x2c;4"
Signed-off-by: Alvise Rigo
---
hw/vfio/platform.c | 158 ++---
1 file changed, 150 insertions(+), 8 deletions(-)
diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
index c4a4286..9dae311 100644
---
The flag is mandatory for the ARM SMMU, add it.
When VFIO will be able to tell about the IOMMU being used, we will add
it only if necessary.
Signed-off-by: Alvise Rigo
---
hw/vfio/common.c | 3 +++
linux-headers/linux/vfio.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw
m,primecell", a
clock property will be added to the device tree node in order to allow the AMBA
bus code to probe the device.
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt.c b
Hi Eric,
Thank you for reviewing it.
On 23/04/2014 17:00, Eric Auger wrote:
> Hi Alvise,
>
> Thank you for the patch. Indeed I am very interested in further
> discussing the vfio-platform integration with you.
>
> On 04/17/2014 07:29 PM, Alvise Rigo wrote:
>> The user
On 24/04/2014 02:25, Peter Crosthwaite wrote:
> On Fri, Apr 18, 2014 at 3:29 AM, Alvise Rigo
> wrote:
>> The flag is mandatory for the ARM SMMU, add it.
>> When VFIO will be able to tell about the IOMMU being used, we will add
>> it only if necessary.
>>
Il 24/04/2014 02:16, Peter Crosthwaite ha scritto:
> On Thu, Apr 24, 2014 at 1:21 AM, Eric Auger wrote:
>> On 04/17/2014 07:29 PM, Alvise Rigo wrote:
>>> These patches were born after trying the current work on device
>>> passthrough (see thread "[Qemu-devel]
On 23/04/2014 17:21, Eric Auger wrote:
> On 04/17/2014 07:29 PM, Alvise Rigo wrote:
>> These patches were born after trying the current work on device
>> passthrough (see thread "[Qemu-devel] [RFC v2 0/6] KVM platform device
>> passthrough") with a DMA330 and FastMo
Both KVM and TCG populate the cpreg_list with 64 bit registers IDs, but in the
TCG side the cpreg_list is sorted using the 32 bit id version while in the kvm
side the 64 bit id version is used.
This patch makes the sorting of the cpreg_list consistent between KVM and TCG.
Signed-off-by: Alvise
The compare_u64 function was not sorting the KVM cpreg_list in the right way
due to the wrong returned value. Since we are comparing two 64bit values we
can't simply return their difference if the returned type is int.
Signed-off-by: Alvise Rigo
---
target-arm/kvm.c | 6 +-
1 file ch
, 2013 at 8:41 PM, Peter Maydell wrote:
> On 12 October 2013 02:38, Alvise Rigo
> wrote:
> > Both KVM and TCG populate the cpreg_list with 64 bit registers IDs, but
> in the TCG side the cpreg_list is sorted using the 32 bit id version while
> in the kvm side the 64 bit id version
H in favour of distinct definitions of the registers with
multiple views (like VBAR for AArch32 and VBAR_EL1 for AArch64).
Regards,
alvise
On Mon, Mar 3, 2014 at 10:39 PM, Peter Maydell wrote:
> On 26 February 2014 10:02, alvise rigo
> wrote:
> > I agree that this is a sort of work
-off-by: Alvise Rigo
---
target-arm/helper.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f65cbac..2791dac 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2313,6 +2313,14 @@ static void
The real hardware seems to not set the Interrupt Controller bit of the
L2CTLR cp register; on the contrary it could set some other bits
regarding RAM features that are not modelled in TCG, so we can mask them out.
Signed-off-by: Alvise Rigo
---
target-arm/cpu.c | 8 +++-
1 file changed, 3
boot, the guest was migrated to a x86 host
running TCG.
The machine model used is vexpress-a15 with cortex-a15 as CPU.
Alvise Rigo (7):
Decouple AArch64 cp registers from AArch32
Migrate CCSIDR registers values as cp17 registers
Add a way to mask some unimplemented bits of cp registers
Exclu
register
and then reading it from the CCSIDR register).
Signed-off-by: Alvise Rigo
---
target-arm/cpu.c | 64
1 file changed, 64 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1ce8a9b..3f0a9b3 100644
--- a/target-arm
ARMCPRegInfo structure to exclude the bits not supported of
the incoming registers values.
In case of an outgoing migration, the unsupported data is retrieved from the
cpreg_vmstate array.
Signed-off-by: Alvise Rigo
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 49
These registers are required in TCG because they are migrated by KVM:
their absence from the cpreg table leads to a migration failure.
Signed-off-by: Alvise Rigo
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/target-arm/cpu.h b
Revisit the definitions of the cp registers TTBR0/1 and TTBRC in such a way to
use the AArch32 ids format when the guest is using a 32bit model.
Signed-off-by: Alvise Rigo
---
target-arm/helper.c | 38 +++---
1 file changed, 27 insertions(+), 11 deletions
the Jazelle bits (in TCG
these bits are set in the reset value of the register, probably
we should consider to remove them).
Signed-off-by: Alvise Rigo
---
target-arm/helper.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper.c b/tar
On Tue, Jan 27, 2015 at 7:48 PM, Peter Maydell wrote:
> On 14 January 2015 at 10:16, Alvise Rigo
> wrote:
>> This is just an update to address the comments received on v2.
>>
>> This patch series is based on the previous work [1] and [2] by Rob Herring.
>> This is
Hi,
On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell wrote:
> On 24 November 2014 at 11:47, Claudio Fontana
> wrote:
>> On 21.11.2014 19:07, Alvise Rigo wrote:
>>> Keep a global list with all the functions that need to modify the device
>>> tree. Using qemu_add
2014 at 18:07, Alvise Rigo
> wrote:
>> Signed-off-by: Alvise Rigo
>> ---
>> hw/arm/virt.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index e8d527d..4e7b869 100644
>> --- a/hw/ar
On Mon, Jan 5, 2015 at 5:41 PM, Peter Maydell wrote:
> On 5 January 2015 at 16:14, alvise rigo wrote:
>> On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell
>> wrote:
>>> Sorry, I think I must have missed this series first time around.
>>> I'm not convinced -
Hi,
On Mon, Jan 5, 2015 at 6:13 PM, Alexander Graf wrote:
>
>
> On 21.11.14 19:07, Alvise Rigo wrote:
>> Add a generic PCI host controller for virtual platforms, based on the
>> previous work by Rob Herring:
>> http://lists.gnu.org/archive/html/qemu-devel/2014
8 AM, Eric Auger wrote:
> On 01/05/2015 05:14 PM, alvise rigo wrote:
>> Hi,
>>
>> On Mon, Jan 5, 2015 at 4:36 PM, Peter Maydell
>> wrote:
>>> On 24 November 2014 at 11:47, Claudio Fontana
>>> wrote:
>>>> On 21.11.2014 19:07, Alvise Rigo
Thank you. I will keep this in mind for the next spin of the patches.
Regards,
alvise
On Mon, Jan 5, 2015 at 7:07 PM, Peter Maydell wrote:
> On 5 January 2015 at 17:35, alvise rigo wrote:
>> So I suppose we need to define a fixed number of PCI slots according
>> to the numbe
On Thu, Jan 8, 2015 at 1:55 PM, Claudio Fontana
wrote:
> (added cc: Alvise which I mistakenly assumed was in Cc: already)
>
> On 07.01.2015 22:47, Alexander Graf wrote:
>>
>>
>> On 07.01.15 16:52, Claudio Fontana wrote:
>>> On 06.01.2015 17:03, Alexander Graf wrote:
Now that we have a working
Hi Alexander,
Just a comment below.
On Tue, Jan 6, 2015 at 5:03 PM, Alexander Graf wrote:
> Now that we have a working "generic" PCIe host bridge driver, we can plug
> it into ARMs virt machine to always have PCIe available to normal ARM VMs.
>
> I've successfully managed to expose a Bochs VGA d
Hi Alexander,
Just a comment below.
On Tue, Jan 6, 2015 at 5:03 PM, Alexander Graf wrote:
> With simple exposure of MMFG, ioport window, mmio window and an IRQ line we
> can successfully create a workable PCIe host bridge that can be mapped
> anywhere
> and only needs to get described to the OS
t: Add generic PCI host device"
http://lists.gnu.org/archive/html/qemu-devel/2014-06/msg03483.html
[3]
"[Qemu-devel] [PATCH 0/4] ARM: Add support for a generic PCI Express host
bridge"
https://www.mail-archive.com/qemu-devel@nongnu.org/msg272648.html
Alvise Rigo (2):
pci/pci-hos
rough the -device option (e.g., -device
virtio-blk-pci).
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 112 +-
1 file changed, 111 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2353440..7b0326f 100644
--- a/h
). The device
needs the following qdev properties to configure the memory regions:
- cfg_win_size: size of the configuration memory
- pio_win_size: size of the port I/O space
- mmio_win_size: size of the MMIO space
- mmio_win_addr: offset of MMIO space in the system memory
Signed-off-by: Alvise
Hi Claudio,
On Wed, Jan 14, 2015 at 2:10 PM, Claudio Fontana
wrote:
> On 14.01.2015 11:16, Alvise Rigo wrote:
>> The platform memory map has now three more memory ranges to map the
>> device's memory regions (Configuration region, I/O region and Memory
>> region).
>&
Hi Claudio,
Sorry, I should have missed this one.
On Wed, Jan 14, 2015 at 2:12 PM, Claudio Fontana
wrote:
> On 14.01.2015 11:16, Alvise Rigo wrote:
>> Add a generic PCI host controller for virtual platforms, based on the
>> previous work by Rob Herring:
>> http://lists.gnu.
On Wed, Nov 5, 2014 at 11:23 AM, Claudio Fontana
wrote:
> Hi Alvise,
Hi Claudio,
>
> On 11.07.2014 09:21, Alvise Rigo wrote:
>> This patch series is based on the previous work [1] and [2] by Rob
>> Herring and it tries to enhance this work on these points:
>
> do your
On Wed, Nov 5, 2014 at 1:26 PM, Claudio Fontana
wrote:
> On 11.07.2014 09:21, Alvise Rigo wrote:
>> Keeping advantage of the finalize_dt QEMUMachine function, the mach-virt
>> machine now completes the device tree creation after that all the
>> generic devices have been inst
cluding also Rob's patches,
> addressing the issues which have been raised before?
Yes, I hope to have something for the next week.
Regards,
alvise
>
>
> Thanks!
>
> Claudio
>
>
> On 11.07.2014 09:21, Alvise Rigo wrote:
> > This patch series is based on the prev
sts.gnu.org/archive/html/qemu-devel/2014-07/msg01957.html
[4]
http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03816.html
Alvise Rigo (4):
hw/arm/virt: Allow multiple agents to modify dt
hw/arm/virt: find_machine_info: handle NULL value
hw/pci-host: Add a generic PCI host contro
interrupt-map property generation. This property is fetched
by the guest operating system to map any PCI interrupt to the interrupt
controller. For the time being, the device expects a GIC v2 to be used
by the guest.
Only mach-virt has been used to test the controller.
Signed-off-by: Alvise Rigo
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e8d527d..4e7b869 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -151,6 +151,10 @@ static VirtBoardInfo *find_machine_info(const char *cpu)
{
int i
Keep a global list with all the functions that need to modify the device
tree. Using qemu_add_machine_init_done_notifier we register a notifier
that executes all the functions on the list and loads the kernel.
Signed-off-by: Alvise Rigo
---
hw/arm/virt.c | 55
Yes, I forgot to remove this hard-coded (wrong) value. I will fix it in the
next release.
On Mon, Nov 24, 2014 at 11:38 AM, Claudio Fontana <
claudio.font...@huawei.com> wrote:
> On 21.11.2014 19:07, Alvise Rigo wrote:
> > Instantiate a generic-pci PCI controller to add a PCI bus
Hi Claudio,
Thank you for your review. Please see my in-line comments.
On Mon, Nov 24, 2014 at 11:34 AM, Claudio Fontana
wrote:
> On 21.11.2014 19:07, Alvise Rigo wrote:
>> Add a generic PCI host controller for virtual platforms, based on the
>> previous work by Rob H
gt; understand where it is coming from...
I think it has to do with the efi-virtio.rom which is supplied to the
virtio-net-pci device.
At the end of pci_add_option_rom() in hw/pci/pci.c you will see the
sixth bar registered.
alvise
>
> Thanks,
>
> Claudio
>
> On 21.11.2014 19:07
Hello,
Related to TCG multithreaded, at Virtual Open Systems, we have also
been working on it. More specifically we are looking on how to enable
a basic multithreaded vCPU infrastructure with one cache per CPU. We
intend to focus on the vCPU private tcg structures
(instantiation/initialization), a
I'm going to respin these patches soon, I've found some issues that
I'm addressing now.
Thank you for your feedback,
alvise
On Tue, May 26, 2015 at 11:51 PM, Emilio G. Cota wrote:
> On Mon, May 11, 2015 at 11:10:05 +0200, alvise rigo wrote:
>
On 23/05/2014 10:40, Eric Auger wrote:
> On 05/11/2014 07:13 PM, Alvise Rigo wrote:
>> The flag is mandatory for the ARM SMMU so we always add it if the MMIO
>> handles it.
>
> Hi Alvise,
>
> Refering to the root problem explanation found in
> https://lkml.org/lkml/
On Sat, Sep 26, 2015 at 7:15 PM, Richard Henderson wrote:
> On 09/24/2015 01:32 AM, Alvise Rigo wrote:
> > +if (cpu == smp_cpus) {
> > +if (smp_cpus >= EXCL_BITMAP_CELL_SZ) {
> > +return bitmap[EXCL_BITMAP_GET_BYTE_OFFSET(add
Hi Paolo,
On Wed, Sep 30, 2015 at 6:44 AM, Paolo Bonzini wrote:
>
>
> On 24/09/2015 10:32, Alvise Rigo wrote:
>> The implementation heavily uses the software TLB together with a new
>> bitmap that has been added to the ram_list structure which flags, on a
>> per-CPU
On Wed, Sep 30, 2015 at 5:34 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> +if (unlikely(!(te->addr_write & TLB_MMIO) && (te->addr_write &
>> TLB_EXCL))) {
>> +/* We are removing an exclusive entry, set
On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> The new helpers rely on the legacy ones to perform the actual read/write.
>>
>> The LoadLink helper (helper_ldlink_name) prepares the way for the
>> fo
On Wed, Sep 30, 2015 at 6:05 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> Use the new slow path for atomic instruction translation when the
>> softmmu is enabled.
>
>
> Um... why? TCG_USE_LDST_EXCL would appear to be 100% r
On Wed, Sep 30, 2015 at 6:03 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> Introduce a set of new runtime helpers do handle exclusive instructions.
>> This helpers are used as hooks to call the respective LL/SC helpers in
>> softmmu_ll
On Wed, Sep 30, 2015 at 1:09 PM, Peter Maydell wrote:
> On 30 September 2015 at 10:24, alvise rigo
> wrote:
>> On Wed, Sep 30, 2015 at 5:34 AM, Richard Henderson wrote:
>>> (1) I don't see why EXCL support should differ whether MMIO is set or not.
>>> Eith
On Wed, Sep 30, 2015 at 10:42 PM, Richard Henderson wrote:
>
> On 09/30/2015 07:46 PM, alvise rigo wrote:
>>
>> On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson wrote:
>>>
>>> Why would you need to indicate that another cpu has started an exclusive
>
starts, the whole memory is set to dirty.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
exec.c | 7 +--
include/exec/memory.h | 3 ++-
include/exec/ram_addr.h | 31 +++
3 files changed, 38
Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 66 --
1 file changed, 44 insertions(+), 22 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index 7029a03..3d388ec 100644
--- a
check.
In addition, add a simple helper function to emulate the CLREX instruction.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/cpu.h | 2 +
target-arm/helper.h| 4 ++
target-arm/machine.c | 2 +
target-arm/op_helper.c
Add a new TLB flag to force all the accesses made to a page to follow
the slow-path.
The TLB entries referring guest pages with the DIRTY_MEMORY_EXCLUSIVE
bit clean will have this flag set.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
include/exec
ed-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c | 7 +++
softmmu_template.h | 26 --
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index aa9cc17..87d09c8 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -424,7 +
the softmmu_helpers.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 96 ++
1 file changed, 60 insertions(+), 36 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
Fontana
Signed-off-by: Alvise Rigo
---
include/qom/cpu.h | 15 +++
qom/cpu.c | 20
2 files changed, 35 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 2e5229d..682c81d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -29,6
' can be a store made by *any* vCPU
(although, some implementations allow stores made by the CPU that issued
the LoadLink).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 3 ++
include/qom/cpu.h
.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 110 +
1 file changed, 68 insertions(+), 42 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index 3d388ec..6279437
usive range in
case of collision.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 20 +---
include/exec/memory.h | 1 +
softmmu_llsc_template.h | 11 +++
softmmu_template.h | 22
86
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rigo (16):
exec.c: Add new exclusive bitmap to ram_list
softmmu: Simplify helper_*_st_name, wrap unaligned code
softmmu: Simplify helper_*_st_name, wrap MMIO code
softmmu: Simplify helper_*_st_name, wrap RAM co
: Alvise Rigo
---
configure | 14 ++
1 file changed, 14 insertions(+)
diff --git a/configure b/configure
index 44ac9ab..915efcc 100755
--- a/configure
+++ b/configure
@@ -294,6 +294,7 @@ solaris="no"
profiler="no"
cocoa="no"
softmmu="yes"
y: Claudio Fontana
Signed-off-by: Alvise Rigo
---
Makefile.target | 2 +-
include/exec/helper-gen.h | 3 ++
include/exec/helper-proto.h | 1 +
include/exec/helper-tcg.h | 3 ++
tcg-llsc-helper.c | 104
tcg-lls
-off-by: Alvise Rigo
---
cputlb.c | 44 --
softmmu_template.h | 80 --
2 files changed, 113 insertions(+), 11 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index ce6d720..aa9cc17 100644
--- a/cputlb.c
+++ b
for more
details).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/cpu64.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index cc177bb..1d45e66 100644
--- a/target-arm/cpu64.c
+++ b/target
Use the new LL/SC runtime helpers to handle the aarch64 atomic instructions
in softmmu_llsc_template.h.
The STXP emulation required a dedicated helper to handle the paired
doubleword case.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
configure
ility to forget the EXCL bit set.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 29 +++--
exec.c | 19 +++
include/qom/cpu.h | 8
softmmu_llsc_template.h
You are right, the for loop with i < DIRTY_MEMORY_NUM works just fine.
Thank you,
alvise
On Thu, Feb 11, 2016 at 2:00 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> The purpose of this new bitmap is to flag the memory pages that are in
>> the middle of LL/SC operat
s from Richard Henderson to improve the logic in
softmmu_template.h and to simplify the methods generation through
softmmu_llsc_template.h
- Added initial implementation of qemu_{ldlink,stcond}_i32 for tcg/i386
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rig
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
include/qom/cpu.h | 4
qom/cpu.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index c6bb6b6..9e409ce 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -175,6 +175,10
Use the new slow path for atomic instruction translation when the
softmmu is enabled.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index b9552fd..cc3891a 100755
Attempting to simplify the helper_*_st_name, wrap the MMIO code into an
inline function.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 64 +-
1 file changed, 44 insertions
n % 8.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
exec.c | 8 --
include/exec/memory.h | 3 +-
include/exec/ram_addr.h | 76 +
3 files changed, 84 insertions(+), 3 deletions
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