QEMU at the moment doesn't allow the migration between KVM and TCG, in
both directions. This limitation is due first of all to the different set
of coprocessor registers supported by KVM and TCG, but also in the way
the coprocessors values are copied from the incoming data to the local QEMU
structures.
This set of patches is focused on the KVM to TCG migration using the
CortexA15 processor (in both sides) and proposes a way to mitigate all the
blocking discrepancies between the two processors.
The major changes carried by this patch set could be summed as following:
- Excluded any AArch64 register definition from a AArch32 only
execution since KVM has none of those registers defined when running on
an ARMv7 processor.
- KVM migrates the values of the supported CSSIDR registers as coprocessors
cp17 registers. We can do the same in TCG adopting the same encoding used
in KVM.
- Some registers are partially supported in TCG mostly because some of
their bits reflect tightly the underlying real hardware.
In some cases TCG simply ignores those bits considering only the modelled
ones, in some other these bits have the default value.
In both cases however, the values carried by these registers could differ
from those migrated by KVM: this is why it is necessary a mechanism to
ignore part of a register when we are copying its value from the incoming
data. For this purpose a new field is introduced (attr_mask) inside
ARMCPRegInfo to explicitly specify, where necessary, which bits are to
be considered when comparing the incoming values with the current ones.
- Some definitions of coprocessors registers have been slightly modified to
guarantee backward compatibility with the AArch32 definitions. TTBCR, for
instance, is one of these registers.
This set of patches has been tested by booting a guest running the
Linux 3.13 and 3.14 kernel in a host using KVM.
Two types of hosts have been used: ARM FastModels and the ARM Chromebook.
Then, in the middle of the kernel boot, the guest was migrated to a x86 host
running TCG.
The machine model used is vexpress-a15 with cortex-a15 as CPU.
Alvise Rigo (7):
Decouple AArch64 cp registers from AArch32
Migrate CCSIDR registers values as cp17 registers
Add a way to mask some unimplemented bits of cp registers
Exclude IC bit from L2CTLR register and add attributes mask
Make TTBR0/1 and TTBRC cp registers backward compatible with AArch32
ids
Added ADFSR/AIFSR and REVIDR cp registers
Minor cp registers changes for KVM -> TCG migration
target-arm/cpu.c | 72 +++++++++++++++++++++++++++--
target-arm/cpu.h | 2 +
target-arm/helper.c | 129 ++++++++++++++++++++++++++++++++++++++++++++--------
3 files changed, 179 insertions(+), 24 deletions(-)
--
1.8.3.2
