[PATCH v5 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v5 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, This patch series targets Zjpm v0.8 extension. The spec itself could be found here: https://github.com/riscv/riscv-j-extension/blob/8088461d8d66a7676872b61c908cbeb7cf5c5d1d/zjpm-spec.pdf This patch series is updated after the suggested comments: - add "x-&qu

[PATCH v5 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v5 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v5 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8de1f1890..bf431ab728 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const

[PATCH v5 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v5 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c9bed5c9fc..1c8979c1c8 100644 --- a

[PATCH v6 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ded84f2e09..23d1692b59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v6 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v6 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v6 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v6 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, This patch series is rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks [v5]: This patch series targets Zjpm v0.8 extension. The spec itself could be found here: https://github.com/riscv/riscv-j-extension/blob

[PATCH v6 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v6 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v7 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v7 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v7 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v7 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v7 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, I'm terribly sorry, but previous rebase went wrong and somehow I missed it. This time I double-checked rebased version. This patch series is properly rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks [v6]: This patch series is rebas

[PATCH v7 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v7 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ded84f2e09..23d1692b59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v8 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v8 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, Rebasing patches on current qemu branch and resubmitting them. Thanks. [v7]: I'm terribly sorry, but previous rebase went wrong and somehow I missed it. This time I double-checked rebased version. This patch series is properly rebased on https://github.com/alist

[PATCH v8 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v8 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v8 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v8 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v8 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73c69f3d0a..9e3bf6c5c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

From: Alexey Baturo Hi, It looks like Pointer Masking spec has reached v1.0 and been frozen, rebasing on riscv-to-apply.next branch and resubmitting patches. Thanks. [v8]: Rebasing patches on current qemu branch and resubmitting them. [v7]: I'm terribly sorry, but previous rebase

[PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 5 target/riscv/cpu_helper.c | 58 +++ 2 files changed, 63 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e350e9bd8..b3b3a6275f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v9 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v12 0/7] RISC-V Pointer Masking implementatio

wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (6): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Add CSR defines for RISC-V PM extension [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode [RISCV_PM] Print new PM

[PATCH v12 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..1a3767804a 100644 --- a/target/riscv

[PATCH v12 1/7] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5896aca346..cd86f5422f 100644 --- a/target/riscv/cpu.h

[PATCH v12 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a95df559d..911cd02ea4 100644 --- a/target/riscv/cpu.c

[PATCH v12 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 287 + 3 files changed, 300 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd..6a95df559d 100644 --- a

[PATCH v12 7/7] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 911cd02ea4..c456be39a1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v12 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2

[PATCH v12 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 ++ target/riscv/translate.c | 56 +--- 2 files changed, 66 insertions(+), 10 deletions(-

Re: [PATCH v14 4/8] [RISCV_PM] Add J extension state description

Sure, will fix that. Thanks вт, 19 окт. 2021 г. в 09:53, Alistair Francis : > On Mon, Oct 18, 2021 at 3:36 AM Alexey Baturo > wrote: > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/machine.c | 27 +++ > > 1 file ch

[PATCH v15 1/8] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h

[PATCH v15 4/8] [RISCV_PM] Add J extension state description

Signed-off-by: Alexey Baturo --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..ae82f82525 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,14

[PATCH v15 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 75e8b8ca83..7f9dde70b7 100644 --- a/target/riscv/cpu.c

[PATCH v15 8/8] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f9dde70b7..fb08c0ffb8 100644 --- a/target/riscv/cpu.c

[PATCH v15 0/8] RISC-V Pointer Masking implementation

. If this patch series would be accepted, I think my further attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey

[PATCH v15 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target

[PATCH v15 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..1a3767804a 100644 --- a/target/riscv

[PATCH v15 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v15 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 target/riscv/translate.c | 39 +-- 2 files changed, 57 insertions(+), 2 deletio

[PATCH v16 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..aa0bce4e06 100644 --- a/target/riscv

[PATCH v16 1/8] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h

[PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b767a4a0b..16fac64806 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -271,6 +271,13 @@ static void riscv_cpu_dump_state

[PATCH v16 4/8] [RISCV_PM] Add J extension state description

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f64b2a96c1..7b4c739564 100644 --- a/target/riscv/machine.c +++ b/target

[PATCH v16 0/8] RISC-V Pointer Masking implementation

ccesses as @Richard mentioned previously Thanks! Alexey Baturo (7): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Add CSR defines for RISC-V PM extension [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode [RISCV_PM] Add J extension state description

[PATCH v16 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ target/riscv/translate.c | 39 +-- 3 files c

[PATCH v16 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target

[PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v16 8/8] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c

[PATCH v17 0/8] RISC-V Pointer Masking implementation

use temp register. v11: Addressed a few style issues Alistair mentioned in the previous review. Alexey Baturo (7): target/riscv: Add J-extension into RISC-V target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Support CSRs required for RISC-V PM extension except for the h-mod

[PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b767a4a0b..16fac64806 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -271,6 +271,13 @@ static void riscv_cpu_dump_state

[PATCH v17 1/8] target/riscv: Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h

[PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target

[PATCH v17 4/8] target/riscv: Add J extension state description

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f64b2a96c1..7b4c739564 100644 --- a/target/riscv/machine.c +++ b/target

[PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..aa0bce4e06 100644 --- a/target/riscv

[PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c

[PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ target/riscv/translate.c | 39 +-- 3 files c

Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

Hi, Having the feature to run binaries with pointer masking on qemu-user is really nice, but I see this patch series as an initial support. Obviously there'll be more patches and fixes for pointer masking as soon as arch tests are ready. I suggest supporting qemu-user in the next patches, but make

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

:44 AM liwei wrote: > > > > > > On 2024/5/11 18:10, Alexey Baturo wrote: > > > From: Alexey Baturo > > > > > > Hi, > > > > > > It looks like Pointer Masking spec has reached v1.0 and been frozen, > > > rebasing on riscv-to-app

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

ay 13, 2024 at 9:14 PM Alistair Francis > wrote: > > > > On Mon, May 13, 2024 at 9:05 PM Alexey Baturo > wrote: > > > > > > Hi, > > > > > > > Hi, any change from v0.8 to v1.0? > > > Not in the patches that were sent. I'd still

[PATCH 1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 63b04e8a94..86c19ea74e 100644 --- a/target/riscv/translate.c +++ b/target/riscv

[PATCH 0/1] Fix pointer masking functionality for RISC-V

From: Alexey Baturo Hi, This patch fixes a typo which leads to broken pointer masking functionality for RISC-V. Thanks. Alexey Baturo (1): target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v13 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..75e8b8ca83 100644 --- a

[PATCH v13 1/7] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h

[PATCH v13 0/7] RISC-V Pointer Masking implementatio

rther attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (6): [RISCV_PM] Add J-extension into RISC-V [RIS

[PATCH v13 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 75e8b8ca83..7f9dde70b7 100644 --- a/target/riscv/cpu.c

[PATCH v13 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..1a3767804a 100644 --- a/target/riscv

[PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 ++ target/riscv/translate.c | 56 +--- 2 files changed, 66 insertions(+), 10 deletions(-

[PATCH v13 7/7] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f9dde70b7..fb08c0ffb8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -558,6 +558,9 @@ static void riscv_cpu_realize(DeviceState

[PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2

Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

xed сб, 16 окт. 2021 г. в 03:01, Richard Henderson : > On 10/15/21 12:29 PM, Alexey Baturo wrote: > > FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) > > +/* If PointerMasking should be applied */ > > +FIELD(TB_FLAGS, PM_ENABLED, 10, 1) > > Merge error. > > >

Re: [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Hi, Sorry, my bad, got it wrong. Fixed now. Thanks! сб, 16 окт. 2021 г. в 02:49, Richard Henderson : > On 10/15/21 12:29 PM, Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo > > Reviewed-by: Richard Henderson > > Reviewed-by: Alistair Francis > > --- &g

[PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h

[PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..1a3767804a 100644 --- a/target/riscv

[PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 75e8b8ca83..7f9dde70b7 100644 --- a/target/riscv/cpu.c

[PATCH v14 0/8] RISC-V Pointer Masking implementation

rther attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (7): [RISCV_PM] Add J-extension into RISC-V [RIS

[PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target

[PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..75e8b8ca83 100644 --- a

[PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 target/riscv/translate.c | 39 +-- 2 files changed, 57 insertions(+), 2 deletio

[PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f9dde70b7..fb08c0ffb8 100644 --- a/target/riscv/cpu.c

[PATCH v14 4/8] [RISCV_PM] Add J extension state description

Signed-off-by: Alexey Baturo --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..4d99880797 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,14

[RFC v1 4/8] Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62dabfa207..25fe60476b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,6 +88,16 @@ typedef enum

[RFC v1 8/8] target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c| 1 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c| 4 target/riscv/machine.c| 1 + target/riscv/pmp.c| 1 + 5 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[RFC v1 1/8] target/riscv: Remove obsolete pointer masking extension code

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 12 -- target/riscv/cpu.h | 30 +--- target/riscv/cpu_bits.h | 82 - target/riscv/cpu_helper.c| 52 -- target/riscv/csr.c | 326 --- target/riscv/machine.c

[RFC v1 7/8] target/riscv: Update address modify functions to take into account pointer masking

Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++-- target/riscv/vector_helper.c | 7 +++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3434ba58b6..4aa0e2b9e1 100644 --- a

[RFC v1 5/8] target/riscv: Add pointer masking tb flags

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 19 +-- target/riscv/cpu_helper.c | 4 target/riscv/translate.c | 10 ++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 25fe60476b

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