v15:
Renamed pm into pointer_masking in machine state.
v14:
Addressed Richard's comments from previous series.
v13:
Rebased QEMU and addressed Richard's comment.
v12:
Updated function for adjusting address with pointer masking to allocate and use
temp register.
v11:
Addressed a few style issues Alistair mentioned in the previous review.
If this patch series would be accepted, I think my further attention would be
to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned
previously
Thanks!
Alexey Baturo (7):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Add CSR defines for RISC-V PM extension
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
the h-mode
[RISCV_PM] Add J extension state description
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 13 ++
target/riscv/cpu.h | 15 ++
target/riscv/cpu_bits.h | 96 ++++++++
target/riscv/cpu_helper.c | 18 ++
target/riscv/csr.c | 285 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/machine.c | 27 +++
target/riscv/translate.c | 43 ++++
11 files changed, 506 insertions(+)
--
2.30.2
