[PATCH v9 1/2] tests/functional: add skipLockedMemoryTest decorator

Used in future commit to skipping execution of a tests if the system's locked memory limit is below the required threshold. Signed-off-by: Alexandr Moshkov Reviewed-by: Thomas Huth --- tests/functional/qemu_test/__init__.py | 2 +- tests/functional/qemu_test/decorators.py | 18 ++

[PATCH v9 0/2] tests/functional: add memlock tests

Add new tests to check the correctness of the `-overcommit memlock` option (possible values: off, on, on-fault) by using `/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck values: * if `memlock=off`, then VmLck = 0; * if `memlock=on`, then VmLck > 0 and almost all memory is residen

[PATCH v9 2/2] tests/functional: add memlock tests

Add new tests to check the correctness of the `-overcommit memlock` option (possible values: off, on, on-fault) by using `/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck values: * if `memlock=off`, then VmLck = 0; * if `memlock=on`, then VmLck > 0 and almost all memory is residen

[PATCH] iotests: add test for changing the 'drive' property via 'qom-set'

Signed-off-by: Fiona Ebner --- tests/qemu-iotests/tests/qom-set-drive | 75 ++ tests/qemu-iotests/tests/qom-set-drive.out | 11 2 files changed, 86 insertions(+) create mode 100755 tests/qemu-iotests/tests/qom-set-drive create mode 100644 tests/qemu-iotests/tests/qo

[PATCH 2/3] scripts/qapi: add QAPISchemaIfCond.rsgen()

From: Marc-André Lureau Generate Rust #[cfg(...)] guards from QAPI 'if' conditions. Signed-off-by: Marc-André Lureau Link: https://lore.kernel.org/r/20210907121943.3498701-15-marcandre.lur...@redhat.com Signed-off-by: Paolo Bonzini --- scripts/qapi/common.py | 16 scripts/qa

[PATCH 3/3] scripts/qapi: generate high-level Rust bindings

From: Marc-André Lureau Generate high-level idiomatic Rust code for the QAPI types, with to/from translations for the C FFI. - char* is mapped to String, scalars to there corresponding Rust types - enums are simply aliased from FFI - has_foo/foo members are mapped to Option - lists are repres

[PATCH 1/3] rust: make TryFrom macro more resilient

If the enum includes values such as "Ok", "Err", or "Error", the TryInto macro can cause errors. Be careful and qualify identifiers with the full path, or in the case of TryFrom<>::Error do not use the associated type at all. Signed-off-by: Paolo Bonzini --- rust/qemu-api-macros/src/lib.rs | 7

[PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function

The current handler for TXFIFO writes schedules an async callback to pop characters from the queue. When software writes to TXFIFO faster than the async callback delay (100ns), the timer may be pushed back while the previous character has not be dequeued yet. This happens in particular when using -

[PATCH v3 00/14] rust: bindings for Error

As explained for v1, the impetus for this series is to remove BqlCell<> from HPETState::num_timers. However, it's also an important step for QAPI: error propagation is pretty central for example to QMP, and the series is also a first example of two-way conversion between C and native-Rust structs

[PATCH 01/14] subprojects: add the anyhow crate

This is a standard replacement for Box which is more efficient (it only occcupies one word) and provides a backtrace of the error. This could be plumbed into &error_abort in the future. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/meson.build | 2

[PATCH 03/14] util/error: expose Error definition to Rust code

This is used to preserve the file and line in a roundtrip from C Error to Rust and back to C. Signed-off-by: Paolo Bonzini --- include/qapi/error-internal.h | 26 ++ rust/wrapper.h| 1 + util/error.c | 10 +- 3 files changed, 28 i

[PATCH 10/14] hpet: adjust VMState for consistency with Rust version

No functional change intended. Suggested-by: Zhao Liu Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 0fd1337a156..9db027cf76f 100644 --- a/hw/timer/hpet.c +

[PATCH 07/14] rust: qemu-api: add tests for Error bindings

Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/error.rs | 104 + 1 file changed, 104 insertions(+) diff --git a/rust/qemu-api/src/error.rs b/rust/qemu-api/src/error.rs index 80157f6ea1b..e114fc4178b 100644 --- a/rust/qemu-api/src/error.rs +++ b/rust/qemu-a

[PATCH 04/14] util/error: allow non-NUL-terminated err->src

Rust makes the current file available as a statically-allocated string, but without a NUL terminator. Allow this by storing an optional maximum length in the Error. Signed-off-by: Paolo Bonzini --- include/qapi/error-internal.h | 9 - util/error.c | 5 +++-- 2 files cha

[PATCH 12/14] rust/hpet: return errors from realize if properties are incorrect

Match the code in hpet.c; this also allows removing the BqlCell from the num_timers field. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw/timer/hpet/src/device.rs | 16 +++- rust/hw/timer/hpet/src/fw_cfg.rs | 7 +++ 2 files changed, 10 insertions(+), 13 deletion

[PATCH 02/14] subprojects: add the foreign crate

This is a cleaned up and separated version of the patches at https://lore.kernel.org/all/20240701145853.1394967-4-pbonz...@redhat.com/ https://lore.kernel.org/all/20240701145853.1394967-5-pbonz...@redhat.com/ Its first user will be the Error bindings; for example a QEMU Error ** can be converted t

[PATCH 05/14] util/error: make func optional

The function name is not available in Rust, so make it optional. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- include/qapi/error-internal.h | 2 ++ util/error.c | 9 +++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/qapi/error-internal.h

[PATCH 06/14] rust: qemu-api: add bindings to Error

Provide an implementation of std::error::Error that bridges the Rust anyhow::Error and std::panic::Location types with QEMU's Error*. It also has several utility methods, analogous to error_propagate(), that convert a Result into a return value + Error** pair. One important difference is that the

[PATCH 14/14] docs: update Rust module status

error is new; offset_of is gone. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- docs/devel/rust.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/rust.rst b/docs/devel/rust.rst index 98803d5e8dd..67acd7d2867 100644 --- a/docs/devel/rust.rst +++ b/docs/de

[PATCH 11/14] hpet: return errors from realize if properties are incorrect

Do not silently adjust num_timers, and fail if intcap is 0. Reviewed-by: Markus Armbruster Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 9db027cf

[PATCH 09/14] rust/hpet: change type of num_timers to usize

Remove the need to convert after every read of the BqlCell. Because the vmstate uses a u8 as the size of the VARRAY, this requires switching the VARRAY to use num_timers_save; which in turn requires ensuring that the num_timers_save is always there. For simplicity do this by removing support for

[PATCH 13/14] rust/hpet: Drop BqlCell wrapper for num_timers

From: Zhao Liu Now that the num_timers field is initialized as a property, someone may change its default value using qdev_prop_set_uint8(), but the value is fixed after the Rust code sees it first. Since there is no need to modify it after realize(), it is not to be necessary to have a BqlCell

[PATCH 08/14] rust: qdev: support returning errors from realize

Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 5 +++-- rust/hw/timer/hpet/src/device.rs | 5 +++-- rust/qemu-api/src/qdev.rs| 10 ++ 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/ru

[PATCH preview 0/3] reviving minimal QAPI generation from 2021

This is just an extremely minimal extraction from the patches at https://patchew.org/QEMU/20210907121943.3498701-1-marcandre.lur...@redhat.com/, limited to generating structs and enums from the QAPI schema. It does not include them in any crate and does not compile them. While I'm not going to wor

Re: [PATCH v12 2/6] arm/virt.c: add cache hierarchy to device tree

On Thu, 5 Jun 2025 17:44:52 +0800 Zhao Liu wrote: > Hi Ali, > > I'm very sorry to bother you with some comments after so many > versions. > > > diff --git a/hw/cpu/core.c b/hw/cpu/core.c > > index 5cb2e9a7f5..7339782663 100644 > > --- a/hw/cpu/core.c > > +++ b/hw/cpu/core.c > > core.c is not

Re: [PATCH v4 04/19] target/i386/cpu: Remove X86CPU::check_cpuid field

On Thu, Jun 05, 2025 at 11:09:30AM +0200, Igor Mammedov wrote: > On Tue, 3 Jun 2025 23:54:19 +0800 > Xiaoyao Li wrote: > > > On 6/3/2025 11:02 PM, Igor Mammedov wrote: > > > On Wed, 28 May 2025 13:23:49 +0800 > > > Zhao Liu wrote: > > > > > >> On Wed, May 28, 2025 at 10:09:56AM +0800, Xiaoyao

[PATCH v3 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa

'ssstrict' is a RVA23 profile-defined extension defined as follows: "No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap

[PATCH v3 0/3] target/riscv: add missing named features

Hi, New version where typos in patch 1 were fixed. No other changes made. All patches acked. Changes from v2: - patch 1 - fixed typos dince -> since and specd -> spec - v2 link: https://lore.kernel.org/qemu-riscv/20250604174329.1147549-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (3)

[PATCH v3 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa

We have support for sdtrig for awhile but we are not advertising it. It is enabled by default via the 'debug' flag. Use the same flag to also advertise sdtrig. Add an exception in disable_priv_spec_isa_exts() to avoid spamming warnings for 'sdtrig' for vendor CPUs like sifive_u. Signed-off-by: Da

Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

On 6/2/25 5:41 PM, Shameer Kolothum wrote: > Although this change does not affect functionality at present, it is > required when we add support for user-creatable SMMUv3 devices in > future patches. > > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3.c | 8 > 1 file changed, 8

Re: [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices

Hi Shameer, On 6/2/25 5:41 PM, Shameer Kolothum wrote: > With the soon to be introduced user-creatable SMMUv3 devices for > virt, it is possible to have multiple SMMUv3 devices associated > with different PCIe root complexes. > > Update IORT nodes accordingly. > > Signed-off-by: Shameer Kolothum >

[PATCH v3 4/5] hw/char/sh_serial: Remove dummy definition of SH_SERIAL class

SH_SERIAL is declared with OBJECT_DECLARE_SIMPLE_TYPE but defined with OBJECT_DEFINE_TYPE, SHSerialStateClass is also a dummy class which missed its parent. Change to use OBJECT_DEFINE_SIMPLE_TYPE and remove SHSerialStateClass. Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg0058

[PATCH v3 1/5] virtio-mem: Fix definition of VirtIOMEMClass

Parent of VirtIOMEMClass is VirtioDeviceClass rather than VirtIODevice. Fixes: 910b25766b33 ("virtio-mem: Paravirtualized memory hot(un)plug") Signed-off-by: Zhenzhong Duan Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-mem.h | 2 +- 1 file chan

[PATCH v3 3/5] hw/gpio/aspeed: Fix definition of AspeedGPIOClass

AspeedGPIOClass's parent is SysBusDeviceClass rather than SysBusDevice. Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Suggested-by: David Hildenbrand Reviewed-by: Cédric Le Goater

[PATCH v3 0/5] Fix definition of classes with wrong parent

Hi, This fix definition of some classes with wrong parent. Used below script to get a list, hoping all are addressed. find "$directory" -type d \( -name "roms" -o -name "build" \) -prune -o -type f \( -name "*.c" -o -name "*.h" \) -print | while read -r file; do awk '/^(struct |typedef struc

RE: [PATCH v3 2/6] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build

Hi Eric, > -Original Message- > From: Eric Auger > Sent: Thursday, June 5, 2025 10:40 AM > To: Shameer Kolothum ; qemu- > a...@nongnu.org; qemu-devel@nongnu.org > Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@nvidia.

RE: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

> -Original Message- > From: Eric Auger > Sent: Thursday, June 5, 2025 11:02 AM > To: Shameerali Kolothum Thodi > ; qemu-...@nongnu.org; > qemu-devel@nongnu.org > Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@nvidia

RE: [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices

> -Original Message- > From: Eric Auger > Sent: Thursday, June 5, 2025 10:58 AM > To: Shameerali Kolothum Thodi > ; qemu-...@nongnu.org; > qemu-devel@nongnu.org > Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@nvidia

[PATCH v3 3/3] target/riscv/cpu.c: do better with 'named features' doc

Most of the named features are added directly in isa_edata_arr[], some of them are also added in riscv_cpu_named_features(). There is a reason for that, and the existing docs can do better explaining it. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.c |

Re: [PATCH] target/riscv/kvm: use qemu_chr_fe_write_all() in SBI_EXT_DBCN_CONSOLE_WRITE_BYTE

On 5/6/25 11:00, Daniel Henrique Barboza wrote: The SBI spec states, for console write byte: "This is a blocking SBI call and it will only return after writing the specified byte to the debug console. It will also return, with SBI_ERR_FAILED, if there are I/O errors." Being a blocker call will

Re: [PATCH v3 2/6] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build

Hi Shameer, On 6/2/25 5:41 PM, Shameer Kolothum wrote: > Introduces a new struct AcpiIortSMMUv3Dev to hold all the information > required for SMMUv3 IORT node and use that for populating the node. > > The current machine wide SMMUv3 is named as legacy SMMUv3 as we will > soon add support for user-

[PATCH] hw/intc/loongarch_extioi: Fix typo issue about register EXTIOI_COREISR_END

Interrupt controller extioi supports 256 vectors, register EXTIOI_COREISR records pending interrupt status with bitmap method. Size of EXTIOI_COREISR is 256 / 8 = 0x20 bytes, EXTIOI_COREISR_END should be EXTIOI_COREISR_START + 0x20 rather than 0xB20. Signed-off-by: Bibo Mao --- include/hw/intc/l

Re: [PATCH v12 2/6] arm/virt.c: add cache hierarchy to device tree

Hi Ali, I'm very sorry to bother you with some comments after so many versions. > diff --git a/hw/cpu/core.c b/hw/cpu/core.c > index 5cb2e9a7f5..7339782663 100644 > --- a/hw/cpu/core.c > +++ b/hw/cpu/core.c core.c is not the right place. It just contains the "cpu-core" abstraction. So we need to

Re: [PATCH v4 04/19] target/i386/cpu: Remove X86CPU::check_cpuid field

On Tue, Jun 03, 2025 at 05:02:38PM +0200, Igor Mammedov wrote: > On Wed, 28 May 2025 13:23:49 +0800 > Zhao Liu wrote: > > > On Wed, May 28, 2025 at 10:09:56AM +0800, Xiaoyao Li wrote: > > > Date: Wed, 28 May 2025 10:09:56 +0800 > > > From: Xiaoyao Li > > > Subject: Re: [PATCH v4 04/19] target/i3

Re: [PATCH v12 5/6] tests/qtest/bios-table-test: testing new ARM ACPI PPTT topology

On Wed, Jun 04, 2025 at 02:34:38PM +0100, Alireza Sanaee wrote: > Date: Wed, 4 Jun 2025 14:34:38 +0100 > From: Alireza Sanaee > Subject: [PATCH v12 5/6] tests/qtest/bios-table-test: testing new ARM ACPI > PPTT topology > X-Mailer: git-send-email 2.34.1 > > Test new PPTT topolopy with cache repre

[PATCH v3 RESEND] target/i386/kvm: Refine VMX controls setting for backward compatibility

From: EwanHai Commit 4a910e1 ("target/i386: do not set unsupported VMX secondary execution controls") implemented a workaround for hosts that have specific CPUID features but do not support the corresponding VMX controls, e.g., hosts support RDSEED but do not support RDSEED-Exiting. In detail, c

[PATCH v2 1/1] target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE

The SBI spec states, for console write byte: "This is a blocking SBI call and it will only return after writing the specified byte to the debug console. It will also return, with SBI_ERR_FAILED, if there are I/O errors." Being a blocker call will either succeed writing the byte or error out, it's

[PATCH v2 0/1] riscv: qemu_chr_fe_write_all() in CONSOLE_WRITE_BYTE

Hi, In this version I removed the reference of SBI_EXT_DBCN_CONSOLE_WRITE in the commit message. That API is *non-blocking*, and citing it to justify a change in a blocking API sounds weird. It's also uneeded since we have a good case without it regardless. No other changes made. Changes from v1

Re: [PATCH] target/riscv/kvm: use qemu_chr_fe_write_all() in SBI_EXT_DBCN_CONSOLE_WRITE_BYTE

On 6/5/25 6:26 AM, Philippe Mathieu-Daudé wrote: On 5/6/25 11:00, Daniel Henrique Barboza wrote: The SBI spec states, for console write byte: "This is a blocking SBI call and it will only return after writing the specified byte to the debug console. It will also return, with SBI_ERR_FAILED,

Re: [PATCH v12 6/6] Update the ACPI tables based on new aml-build.c

On Wed, Jun 04, 2025 at 02:34:39PM +0100, Alireza Sanaee wrote: > Date: Wed, 4 Jun 2025 14:34:39 +0100 > From: Alireza Sanaee > Subject: [PATCH v12 6/6] Update the ACPI tables based on new aml-build.c > X-Mailer: git-send-email 2.34.1 > > The disassembled differences between actual and expected P

Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

On 6/5/25 11:53 AM, Eric Auger wrote: > > > On 6/2/25 5:41 PM, Shameer Kolothum wrote: >> Although this change does not affect functionality at present, it is >> required when we add support for user-creatable SMMUv3 devices in >> future patches. >> >> Signed-off-by: Shameer Kolothum >> --- >

Re: [PATCH] accel/tcg: Make round-robin kick period configurable

Hi Philippe, Thank you for your response. Since TCGState is currently defined only in tcg-all.c, we’re unable to access rr_kick_delay_ns from other .c files through the struct. One potential approach would be to introduce a tcg-all.h header and move the TCGState definition there. This would allo

[PATCH v3 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class

RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really neces

[PATCH v3 2/5] virtio-pmem: Fix definition of VirtIOPMEMClass

VirtIOPMEMClass's parent is VirtioDeviceClass rather than VirtIODevice. Fixes: 5f503cd9f388 ("virtio-pmem: add virtio device") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Reported-by: David Hildenbrand Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-D

Re: [PATCH v5 4/6] python: add qapi static analysis tests

On Thu, Jun 05, 2025 at 08:33:44AM +0200, Markus Armbruster wrote: > John Snow writes: > > [...] > > > diff --git a/python/tests/qapi-flake8.sh b/python/tests/qapi-flake8.sh > > new file mode 100755 > > index 000..2211b6c7f41 > > --- /dev/null > > +++ b/python/tests/qapi-flake8.sh > > @@

Re: ppc kvm: support of 64K guest page size with 4K host pagesize?

On Thu, Jun 05, 2025 at 08:52:44AM +0200, Thomas Huth wrote: > On 05/06/2025 08.34, Michael Tokarev wrote: > > There's a bug report filed in debian against qemu, > > https://bugs.debian.org/1107288 - saying kvm on ppc does not > > work on debian (anymore) due to qemu requesting unrealistic > > (non

[PATCH v4 1/3] docs: introduce dedicated page about code provenance / sign-off

From: Daniel P. Berrangé Currently we have a short paragraph saying that patches must include a Signed-off-by line, and merely link to the kernel documentation. The linked kernel docs have a lot of content beyond the part about sign-off an thus are misleading/distracting to QEMU contributors. Th

[PATCH v4 3/3] docs: define policy forbidding use of AI code generators

From: Daniel P. Berrangé There has been an explosion of interest in so called AI code generators. Thus far though, this is has not been matched by a broadly accepted legal interpretation of the licensing implications for code generator outputs. While the vendors may claim there is no problem and

[PATCH v4 0/3] docs: define policy forbidding use of "AI" / LLM code generators

More than a year ago, Daniel posted patches to put an AI policy in writing. Reception was mostly positive. A v2 to address feedback followed with some delay. But no pull request. I asked Daniel why, and he told me he was concerned it might go too far in its interpretation of the DCO requirement

[PATCH v4 2/3] docs: define policy limiting the inclusion of generated files

From: Daniel P. Berrangé Files contributed to QEMU are generally expected to be provided in the preferred format for manipulation. IOW, we generally don't expect to have generated / compiled code included in the tree, rather, we expect to run the code generator / compiler as part of the build pro

Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

On Mon, 2 Jun 2025 16:41:05 +0100 Shameer Kolothum via wrote: > Although this change does not affect functionality at present, it is > required when we add support for user-creatable SMMUv3 devices in > future patches. > > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3.c | 8 >

Re: [PATCH v3 1/5] virtio-mem: Fix definition of VirtIOMEMClass

Zhenzhong Duan writes: > Parent of VirtIOMEMClass is VirtioDeviceClass rather than VirtIODevice. > > Fixes: 910b25766b33 ("virtio-mem: Paravirtualized memory hot(un)plug") > Signed-off-by: Zhenzhong Duan > Reviewed-by: David Hildenbrand > Reviewed-by: Philippe Mathieu-Daudé > --- > include/hw

RE: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

> -Original Message- > From: Igor Mammedov > Sent: Thursday, June 5, 2025 11:55 AM > To: Shameer Kolothum via > Cc: Shameerali Kolothum Thodi > ; qemu-...@nongnu.org; > eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com; > nicol...@nvidia.com; ddut...@redhat.com; berra...

Re: [PATCH] virtio: avoid cost of -ftrivial-auto-var-init in hot path

On 5/6/25 10:34, Daniel P. Berrangé wrote: On Wed, Jun 04, 2025 at 03:18:43PM -0400, Stefan Hajnoczi wrote: Since commit 7ff9ff039380 ("meson: mitigate against use of uninitialize stack for exploits") the -ftrivial-auto-var-init=zero compiler option is used to zero local variables. While this re

Re: [PATCH v4 2/3] docs: define policy limiting the inclusion of generated files

On Thu, 5 Jun 2025 at 11:52, Markus Armbruster wrote: > +At times contributors may use or create scripts/tools to generate an initial > +boilerplate code template which is then filled in to produce the final patch. > +The output of such a tool would still be considered the "preferred format", > +s

[PATCH] hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions

The AN500 application note documents that it configures the Cortex-M7 CPU to have 16 MPU regions. We weren't doing this in our emulation, so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions property to 16 for this board. This bug doesn't affect any of the other board types we mod

[PATCH] target: riscv: Add Svrsw60t59b extension support

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Signed-off-by: Alexandre Ghiti --- Changes in v2: - Add support for IOMMU - Make svrsw60t59b depend on sv39 (deepak) Open question: svrsw60t59b in IOMMU should also depend on 64bit, but I did not fin

Re: [PATCH] virtio: avoid cost of -ftrivial-auto-var-init in hot path

On 5/6/25 14:50, Stefan Hajnoczi wrote: On Thu, Jun 05, 2025 at 01:28:49PM +0200, Philippe Mathieu-Daudé wrote: On 5/6/25 10:34, Daniel P. Berrangé wrote: On Wed, Jun 04, 2025 at 03:18:43PM -0400, Stefan Hajnoczi wrote: Since commit 7ff9ff039380 ("meson: mitigate against use of uninitialize st

Re: [PATCH 06/14] rust: qemu-api: add bindings to Error

On Thu, Jun 05, 2025 at 12:15:35PM +0200, Paolo Bonzini wrote: > Date: Thu, 5 Jun 2025 12:15:35 +0200 > From: Paolo Bonzini > Subject: [PATCH 06/14] rust: qemu-api: add bindings to Error > X-Mailer: git-send-email 2.49.0 > > Provide an implementation of std::error::Error that bridges the Rust > a

Re: [PATCH v5 00/13] Improve futex usage

From: Akihiko Odaki > In a recent discussion, Phil Dennis-Jordan pointed out a quirk in > QemuEvent destruction due to futex-like abstraction, which prevented > the usage of QemuEvent in new and existing code[1]. With some more > thoughts after this discussion, I also found other problem and room

Re: [PULL 00/16] rust, i386 changes for 2025-06-03

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v1] ramfb: Add property to control if load the romfile

Hi, guys Thanks for all of your suggestions. On 6/5/25 11:11 PM, Philippe Mathieu-Daudé wrote: On 5/6/25 14:21, Gerd Hoffmann wrote:    Hi, Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramfb.bin, this can cause that when use the release pac

Re: [PATCH 3/4] tests/unit/test-char: Avoid using g_alloca()

On 5/6/25 22:53, Pierrick Bouvier wrote: On 6/5/25 12:35 PM, Philippe Mathieu-Daudé wrote: Do not use g_alloca(), simply allocate the CharBackend structure on the stack. Signed-off-by: Philippe Mathieu-Daudé ---   tests/unit/test-char.c | 3 +--   1 file changed, 1 insertion(+), 2 deletions(-)

[PATCH v3 05/13] hw/intc/loongarch_ipi: Add kernel irqchip save and restore function

Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set IPI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 20 hw/intc/loongarch_ipi_kvm.c | 54 + include/hw/intc/loon

[PATCH v3 00/13] hw/loongarch/virt: Add kernel irqchip support

If kernel irqchip is set such as kvm_irqchip_in_kernel() return true, there is special operations with irqchips in such fields: 1. During irqchip object realization, kvm_create_device() is used here to create irqchip in KVM kernel. 2. Add pre_save and post_load function, where register sta

[PATCH v3 03/13] hw/intc/loongarch_ipi: Add kernel irqchip realize function

Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true. It is to create and initialize IPI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 5 + hw/intc/loongarch_ipi_kvm.c | 27 +++ hw/intc/loongson_ipi_com

[PATCH v3 04/13] hw/intc/loongson_ipi: Add load and save interface with ipi_common class

Add pre_save and post_load interfaces with ipi_common class, here only framework ipi_common adds these interfaces. The defailed implementation is LoongArchIPI child device in later. Signed-off-by: Bibo Mao --- hw/intc/loongson_ipi_common.c | 28 +++ include/hw/int

[PATCH v3 06/13] hw/intc/loongarch_pch_msi: Inject MSI interrupt to kernel

If kvm_irqchip_in_kernel() return true, MSI interrupt can be injected with API kvm_irqchip_send_msi() to KVM. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_msi.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c index 06

[PATCH v3 09/13] hw/intc/loongarch_pch: Inject irq line interrupt to kernel

If kvm_irqchip_in_kernel() return true, irq line interrupt can be injected with API kvm_set_irq() to KVM. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 4d232f4cca..7

[PATCH v3 02/13] hw/intc/loongarch_extioi: Add kernel irqchip save and restore function

Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set ExtIOI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_extioi.c | 14 + hw/intc/loongarch_extioi_kvm.c | 90 ++ include/hw/intc/loong

[PATCH v3 01/13] hw/intc/loongarch_extioi: Add kernel irqchip realize function

Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is set. It is to create and initialize ExtIOI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_extioi.c | 31 hw/intc/loongarch_extioi_kvm.c | 46 ++ h

[PATCH v3 07/13] hw/intc/loongarch_pch: Add kernel irqchip realize function

Function kvm_pic_realize() is added if kvm_irqchip_in_kernel() return true. It is to notify KVM kernel to create and initialize PCH PCI device in kernel mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 14 --- hw/intc/loongarch_pic_kvm.c | 38 ++

[PATCH v3 08/13] hw/intc/loongarch_pch: Add kernel irqchip save and restore function

Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set PCH PCI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c| 22 hw/intc/loongarch_pic_kvm.c| 47 ++ include/h

[PATCH v3 10/13] hw/loongarch/virt: Add reset support for kernel irqchip

When system reboot, interrupt controller is restored to initial state. However if interrupt controller extioi/ipi/pch_pic is emulated in kernel, it should notify kvm to do so. Here suspend and restore API is used for reset, set initial state in qemu user space and restore API is used to notify kvm

[PATCH v3 11/13] target/loongarch: Report error with split kernel_irqchip option

Option kernel_irqchip=split is not supported on LoongArch virt machine, report error and exit if detect split kernel_irqchip option. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/loongarch/kvm/kvm.c b/targe

[PATCH v3 13/13] hw/loongarch/virt: Add kernel irqchip support

If kvm_irqchip_in_kernel() return true, interrupt controller ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And it is not necessary to create memory region for these devices in user space. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c| 57 ++--

[PATCH v3 12/13] hw/loongarch/virt: Disable emulation with IOCSR misc register

Register IOCSR MISC_FUNC_REG is to enable features about EXTIOI irqchip. If EXTIOI is emulated in kernel, MISC_FUNC_REG register should be emulated in kernel also. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/loongarch/virt.c b/hw

Re: [PATCH v1] ramfb: Add property to control if load the romfile

On 6/6/25 05:20, Shaoqin Huang wrote: Hi, guys Thanks for all of your suggestions. On 6/5/25 11:11 PM, Philippe Mathieu-Daudé wrote: On 5/6/25 14:21, Gerd Hoffmann wrote:    Hi, Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramfb.bin, this

RE: [PATCH v5 2/7] ui/spice: Add an option for users to provide a preferred codec

Hi Daniel, > Subject: Re: [PATCH v5 2/7] ui/spice: Add an option for users to provide a > preferred codec > > On Wed, May 28, 2025 at 10:11:13PM -0700, Vivek Kasireddy wrote: > > Giving users an option to choose a particular codec will enable > > them to make an appropriate decision based on thei

Re: [PATCH v4 2/3] docs: define policy limiting the inclusion of generated files

Daniel P. Berrangé writes: > On Thu, Jun 05, 2025 at 12:38:09PM +0100, Peter Maydell wrote: >> On Thu, 5 Jun 2025 at 11:52, Markus Armbruster wrote: >> > +At times contributors may use or create scripts/tools to generate an >> > initial >> > +boilerplate code template which is then filled in to

[PATCH v6] target/riscv/kvm: add max_satp_mode from host cpu

This patch adds max_satp_mode from host kvm cpu setting. Tested on: Milkv Megrez (Eswin 7700x) Reviewed-by: Andrew Jones Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 Signed-off-by: Meng Zhuo --- Change in v6: - Rebase on https://github.com/alistair23/qemu/tree/riscv-to-apply.nex

Re: [PULL 09/17] hw/display: re-arrange memory region tracking

On 2025/06/06 1:26, Alex Bennée wrote: QOM objects can be embedded in other QOM objects and managed as part of their lifetime but this isn't the case for virtio_gpu_virgl_hostmem_region. However before we can split it out we need some other way of associating the wider data structure with the mem

Re: [PATCH v1] ramfb: Add property to control if load the romfile

On Thu, Jun 05, 2025 at 04:24:07PM +0200, Cédric Le Goater wrote: > On 6/5/25 14:21, Gerd Hoffmann wrote: > >Hi, > > > > > > Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only > > > > the x86 need the vgabios-ramfb.bin, this can cause that when use the > > > > release pack

Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association

On Thu, 5 Jun 2025 12:36:52 + Shameerali Kolothum Thodi wrote: > > -Original Message- > > From: Igor Mammedov > > Sent: Thursday, June 5, 2025 1:20 PM > > To: Shameerali Kolothum Thodi > > Cc: Shameer Kolothum via ; qemu- > > a...@nongnu.org; eric.au...@redhat.com; peter.mayd...@lin

[PATCH] hw/arm/smmuv3: Fix incorrect reserved mask for SMMU CR0 register

From: Tao Tang The current definition of the SMMU_CR0_RESERVED mask is incorrect. It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while treating bit 9 (RES0) as an implemented bit. According to the SMMU architecture specification, the layout for CR0 is: | 31:11| RES0 | | 10

Re: [PATCH 03/14] util/error: expose Error definition to Rust code

On Thu, Jun 05, 2025 at 12:15:32PM +0200, Paolo Bonzini wrote: > Date: Thu, 5 Jun 2025 12:15:32 +0200 > From: Paolo Bonzini > Subject: [PATCH 03/14] util/error: expose Error definition to Rust code > X-Mailer: git-send-email 2.49.0 > > This is used to preserve the file and line in a roundtrip fr

Re: [PATCH v5 2/3] hw/s390x: add Control-Program Identification to QOM

On Thu, 2025-06-05 at 14:03 +0200, Thomas Huth wrote: > On 05/06/2025 13.56, Thomas Huth wrote: > > On 05/06/2025 10.34, Nina Schoetterl-Glausch wrote: > > > On Tue, 2025-06-03 at 15:56 +0200, Shalini Chellathurai Saroja wrote: > > > > Add Control-Program Identification (CPI) data to the QEMU Objec

Re: [PATCH v1] ramfb: Add property to control if load the romfile

On 5/6/25 14:21, Gerd Hoffmann wrote: Hi, Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramfb.bin, this can cause that when use the release package on arm64 it can't find the vgabios-ramfb.bin. Simpler to directly pass the ROM path instea

Re: [PATCH 07/18] hw/pci/pcie: Remove QEMU_PCIE_EXTCAP_INIT definition

On Thu, 1 May 2025 23:04:45 +0200 Philippe Mathieu-Daudé wrote: > QEMU_PCIE_EXTCAP_INIT was only used by the hw_compat_2_8[] > array, via the 'x-pcie-extcap-init=off' property. We removed > all machines using that array, lets remove all the code around > QEMU_PCIE_EXTCAP_INIT. > > Signed-off-by

Build platform guarantees, docs, tests, and snakes in the garden

Hi, I've long been a little confused about the specifics of our build platform guarantee and how it applies to documentation and testing. My *current* understanding is that our build platform guarantee applies to both unit tests and building documentation, but that this requirement may not be as a

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