On 5/28/25 08:04, Zhenzhong Duan wrote:
Enhance HostIOMMUDeviceIOMMUFD object with 3 new members, specific
to the iommufd BE + 2 new class functions.
IOMMUFD BE includes IOMMUFD handle, devid and hwpt_id. IOMMUFD handle
and devid are used to allocate/free ioas and hwpt. hwpt_id is used to
re-att
On 5/28/25 08:04, Zhenzhong Duan wrote:
Implement [at|de]tach_hwpt handlers in VFIO subsystem. vIOMMU
utilizes them to attach to or detach from hwpt on host side.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/vfio/iommufd.c | 22
On 5/28/25 08:04, Zhenzhong Duan wrote:
There are three iommufd specific members in HostIOMMUDeviceIOMMUFD
that need to be initialized after attachment, they will all be used
by vIOMMU.
Signed-off-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/vfio/iommufd.c | 6 +
From: Alexandr Moshkov
Used in future commit to skipping execution of a tests if the system's
locked memory limit is below the required threshold.
Signed-off-by: Alexandr Moshkov
Reviewed-by: Thomas Huth
Message-ID: <20250525070737.54267-2-dtalexund...@yandex-team.ru>
Signed-off-by: Thomas Hut
Sorry, my first message seems to not have made it out...
Thanks for the review, I posted a v2 patch to the list.
On Tue, May 20, 2025 at 03:13:38PM +0100, Alex Bennée wrote:
> This seems reasonable. Do you have any specific use cases where this
> information is useful?
In an embedded application
From: Philippe Mathieu-Daudé
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS was only used by the
hw_compat_2_5[] array, via the 'x-old-msi-offsets=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS.
Signed-off-by: Philippe Mathieu-Dau
From: Philippe Mathieu-Daudé
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Message-ID: <20250512083948
On Tue, 27 May 2025 15:54:15 +0200
Eric Auger wrote:
> Hi Igor,
>
> On 5/27/25 1:58 PM, Igor Mammedov wrote:
> > On Tue, 27 May 2025 09:40:04 +0200
> > Eric Auger wrote:
> >
> >> acpi_pcihp VirtMachineClass state flag will allow
> >> to opt in for acpi pci hotplug. This is guarded by a
> >> c
From: Philippe Mathieu-Daudé
Simplify merging vmxnet3_realize() within vmxnet3_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Message-ID: <2025051208
Paolo Bonzini writes:
> On 5/27/25 15:42, Markus Armbruster wrote:
>> Paolo Bonzini writes:
>>
>>> Rust makes the current file available as a statically-allocated string,
>>> but without a NUL terminator. Allow this by storing an optional maximum
>>> length in the Error.
>>>
>>> Note that for
On Wed, May 28, 2025 at 11:49 AM Markus Armbruster wrote:
> > diff --git a/rust/qemu-api/src/error.rs b/rust/qemu-api/src/error.rs
> > new file mode 100644
> > index 000..f08fed81028
> > --- /dev/null
> > +++ b/rust/qemu-api/src/error.rs
> > @@ -0,0 +1,273 @@
> > +// SPDX-License-Identifie
On 5/28/25 08:04, Zhenzhong Duan wrote:
Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP|ERRATA] for IOMMUFD
backed host VTD IOMMU device.
Query on these capabilities is not supported for legacy backend because there
is no plan to support nesting with legacy backend backed host device.
S
On Wed, 28 May 2025 11:48:20 +0200
Eric Auger wrote:
> Hi Igor,
>
> On 5/28/25 11:38 AM, Igor Mammedov wrote:
> > On Tue, 27 May 2025 09:40:26 +0200
> > Eric Auger wrote:
> >
> >> From: Gustavo Romero
> >>
> >> ACPI PCI hotplug is now turned on by default so we need to change the
> >> existi
Check 32 vs 64-bit state.
Cc: qemu-...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/ppc/cpu_init.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9642812a71..a0e77f2673 100644
--- a/tar
On Fri, May 23, 2025 at 4:06 PM Paolo Bonzini wrote:
>
>
>
> Il gio 22 mag 2025, 10:12 Manos Pitsidianakis
> ha scritto:
>>
>> This is unnecessary though, because once we have the
>> const_refs_to_static feature we can introduce a QdevProp trait that
>> returns a reference to a type's qdev_prop_
From: Li Chen
(REPOST because the previous post failed to send to
qemu-devel/qemu-riscv/qemu-arm,
see
https://lore.kernel.org/qemu-devel/1971648603b.dce1f5d22901195.6702025346547333607@linux.beauty/T/#u)
This series introduces a new machine option, spcr=on|off, allowing users
to disable the A
From: Li Chen
Add ACPI SPCR table test case for RISC-V when SPCR was off.
Signed-off-by: Li Chen
Reviewed-by: Sunil V L
---
Notes:
Changes since v3: Add Reviewed-by from Sunil V L
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g.,
"cons
From: Li Chen
Add ACPI SPCR table test case for ARM when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435..d2a1aa7fb
Hi Thomos,
On Wed, 28 May 2025 17:52:50 +0800 Thomas Huth wrote
---
> On 28/05/2025 11.45, Li Chen wrote:
> > Hi,
> >
> > My emails to the qemu-devel, qemu-riscv, and qemu-arm mailing lists
> > regarding the
> > "[PATCH v4 0/4] acpi: Add machine option to disable SPCR table" seri
On arm/virt the memory map is set up before any devices are brought
up. To enable this provide split functions to establish the fw->base
and later to actually map it.
Signed-off-by: Jonathan Cameron
---
v14: Update wrt to changes in previous patch.
Add a do_cfwms_set_memmap_and_update_mmio(
Previously these somewhat device like structures were tracked using a list
in the CXLState in each machine. This is proving restrictive in a few
cases where we need to iterate through these without being aware of the
machine type. Just make them sysbus devices.
Restrict them to not user created a
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
---
includ
To enable these to be found in a fixed order, that order needs
to be known. This will later be used to sort a list of these
structures that address map and ACPI table entries are predictable.
Reviewed-by: Li Zhijian
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v14: Picked up tags.
From: Li Chen
The virt machines always instantiate a PL011/16550 at UART0 and
describe it in ACPI (DSDT device node plus optional SPCR table). When
the command line contains “-serial none” there is no backend attached to
that UART, yet the guest still discovers it via ACPI and may try to use
it
v14: Simplifications suggeseted by Itaru (and some extra simplifications
that became apparent) and gather tags.
See individual patches for more information.
Updated cover letter
Richard Henderson has posted a pull request with a fix for the TCG TLB
issue which will hopefully merge short
Hi Philippe,
On Mon, 26 May 2025 18:07:16 +0800 Philippe Mathieu-Daudé
wrote ---
> Hi Li,
>
> On 15/5/25 14:41, Li Chen wrote:
> > From: Li Chen
> >
> > The ACPI SPCR (Serial Port Console Redirection) table allows firmware
> > to specify a preferred serial console device to the
On Mon, May 26, 2025 at 04:24:49PM +0200, Paolo Bonzini wrote:
> Date: Mon, 26 May 2025 16:24:49 +0200
> From: Paolo Bonzini
> Subject: [PATCH 06/12] util/error: make func optional
> X-Mailer: git-send-email 2.49.0
>
> The function name is not available in Rust, so make it optional.
>
> Signed-o
Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
configs/targets/microblaze-softmmu.mak | 4 +---
configs/targets/microblazeel-softmmu.mak | 4 +-
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/helper.c | 64 +-
1 file changed, 36 insertions(+), 28 deletions(-)
diff --git a/target/microblaze/helper.c b/t
This series failed to send to qemu-devel/qemu-arm/qemu-riscv. I have requested
assistance via this thread:
https://lore.kernel.org/qemu-devel/1971648603b.dce1f5d22901195.6702025346547333607@linux.beauty/T/#u
On Wed, 28 May 2025 16:09:36 +0800 Li Chen wrote ---
> From: Li Chen
>
> T
Hi,
My emails to the qemu-devel, qemu-riscv, and qemu-arm mailing lists regarding
the
"[PATCH v4 0/4] acpi: Add machine option to disable SPCR table" series are
being
rejected by these mailing lists, while other recipients are unaffected.
This issue didn't occur with versions v1-v3, which I s
Paolo Bonzini writes:
> Provide an implementation of std::error::Error that bridges the Rust
> anyhow::Error and std::panic::Location types with QEMU's Error*.
> It also has several utility methods, analogous to error_propagate(),
> that convert a Result into a return value + Error** pair.
>
> Si
On 28/05/2025 11.45, Li Chen wrote:
Hi,
My emails to the qemu-devel, qemu-riscv, and qemu-arm mailing lists regarding
the
"[PATCH v4 0/4] acpi: Add machine option to disable SPCR table" series are being
rejected by these mailing lists, while other recipients are unaffected.
This issue didn't oc
Hi Igor,
On 5/28/25 11:38 AM, Igor Mammedov wrote:
> On Tue, 27 May 2025 09:40:26 +0200
> Eric Auger wrote:
>
>> From: Gustavo Romero
>>
>> ACPI PCI hotplug is now turned on by default so we need to change the
>> existing tests to keep it off. However, even setting the ACPI PCI
>> hotplug off in
Hello Zhenzhong,
On 5/28/25 08:04, Zhenzhong Duan wrote:
This helper passes cache invalidation request from guest to invalidate
stage-1 page table cache in host hardware.
Signed-off-by: Nicolin Chen
Signed-off-by: Zhenzhong Duan
---
include/system/iommufd.h | 4
backends/iommufd.c
Currently, there is only one CPER buffer (entry) can be delivered and
acknoledged at once. This conflicts to the scenario where the host and
guest has 64KB and 4KB page size. In this specific scenario, a problematic
host page can affect 16x guest pages, resulting in 16x memory errors
in the worst c
In the situation where host and guest has 64KB and 4KB page sizes, one
error on the host's page affects 16 guest's pages. we need to send 16
consective errors in this specific case.
Extend acpi_ghes_memory_errors() to support multiple CPERs after the
hunk of code to generate the GHES error status
Introduce helper push_ghes_memory_errors(), which sends ACPI GHES memory
errors, injects SEA exception or aborts on errors. This function will
be extended to support multiple ACPI GHES memory errors in the next
path.
No functional changes intended.
Signed-off-by: Gavin Shan
---
target/arm/kvm.c
assert(hole == file_length);
-}
-*pnum = ROUND_UP(*pnum, bs->bl.request_alignment);
-}
+*pnum = ROUND_UP(*pnum, bs->bl.request_alignment);
ret = BDRV_BLOCK_DATA;
} else {
---
base-commit: f0737158b483e7ec2b2512145aeab888b85cc1f7
change-id: 20250528-dio-db04a66a7848
Best regards,
--
Akihiko Odaki
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH rfcv3 15/21] intel_iommu: Bind/unbind guest page table to
>host
>
>OK. Let me clarify this at the top as I see the gap here now:
>
>First, the vSMMU model is based on Zhenzhong's older series that
>keeps an ioas_id in the Host
Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 2 +-
target/microblaze/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
i
From: Andreas Schwab
Signed-off-by: Andreas Schwab
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID:
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 23b901b713..fc37028597 100644
--- a
Use exec/target_page.h instead of independent variables.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 3 ---
accel/tcg/translate-all.c| 4
tcg/perf.c | 2 +-
tcg/tcg-op-ldst.c| 3 ++-
tcg/tcg.c
Alpha, HPPA, and SH4 always use aligned addresses,
and therefore never produce accesses that cross pages.
Cc: Helge Deller
Cc: Yoshinori Sato
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 5 +
accel/tcg/cputlb.c | 13 +
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250515174641.4000309-1-pierrick.bouv...@linaro.org>
---
system/main.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/system/main.c b/system
Check 32 vs 64-bit addressing state.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4cbfb9435a..1f6c41fd34 100644
--- a/target/mips/cpu.c
+++ b/ta
When we moved TLB_MMIO and TLB_DISCARD_WRITE to TLB_SLOW_FLAGS_MASK,
we failed to update atomic_mmu_lookup to properly reconstruct flags.
Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow
flags")
Reported-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Reviewed-by: P
Check va32 state.
Reviewed-by: Song Gao
Reviewed-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f7535d1be7..abad84c054
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets. AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.
Cc: Michael Rolnik
Cc: Laurent Vivier
Cc: Stafford Horne
Cc: Yoshinori Sato
Cc: Max Filippov
Tested-by Bastian Koppelmann (tricore)
Review
For a-profile, check A32 vs A64 state.
For m-profile, use cpu_pointer_wrap_uint32.
Cc: qemu-...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 24
target/arm/tcg/cpu-v7m.c | 1 +
2 files changed, 25 insertions(+)
diff --git a/target/arm/cpu.
This was an extremely minor optimization for aarch64
and x86_64, to use a 32-bit AND instruction when the
guest softmmu tlb maximum was sufficiently small.
Both hosts can simply use a 64-bit AND insn instead.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 1 -
accel/tcg/tran
Use an explicit 64-bit type for extended addresses.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/
Require TCGv_i32 and TCGv be identical, so drop
the extensions. Return constants when possible
instead of a mov into a temporary. Return register
inputs unchanged when possible.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 26
The following changes since commit 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into
staging (2025-05-26 10:16:59 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202
Check 32 vs 64-bit and pointer masking state.
Cc: qemu-ri...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/tcg/tcg-cpu.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/riscv/tc
Check address masking state for sparc64.
Cc: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 2a3e408923..ed7701b02f 1006
Check 32 vs 64-bit state.
Cc: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/tcg-cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 179dfdf064..6f5dc06b3b 100644
--
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/op_helper.c | 70 +--
1 file changed, 42 insertions(+), 28 deletions(-)
diff --git a/target/microblaze/op_helper.c
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 7 +++
accel/tcg/cputlb.c | 6 ++
2 files changed, 13 insertions(+)
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index cd22e5d5b9..83b2c2c864 100644
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/helper.h | 12 ++--
target/microblaze/helper.c | 7 +++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index f740835fcb..41f
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 24 ++--
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/target/microblaze/transl
All targets now provide the function, so we can
make the call unconditional.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 1 +
accel/tcg/cputlb.c | 7 ++-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/cpu-exec.c
Use TARGET_FMT_lx to match the target_ulong type of vaddr.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 95a12e16f8..8703ff
On 27/05/2025 19.20, Thomas Huth wrote:
On 12/05/2025 10.39, Philippe Mathieu-Daudé wrote:
The "fallback" property was only used by the hw_compat_2_5[] array,
as 'fallback=144'. We removed all machines using that array, lets
remove ISA floppy drive 'fallback' property, manually setting the
defau
On 27.05.2025 19:10, elisey.konstanti...@icloud.com wrote:
From e2f3eab60e9b9787c5c8f87bea5d1bd7079d982e Mon Sep 17 00:00:00 2001
From: Elisey
Date: Tue, 27 May 2025 17:17:35 +0300
Subject: [PATCH] Revert "i386/cpu: Set up CPUID_HT in x86_cpu_expand_features()
instead of cpu_x86_cpuid()"
This
On 28.05.2025 11:29, Michael Tokarev wrote:
Cc: qemu-sta...@nongnu.org
for 10.0.x.
Ah, 10.0.1 already has a fix. n/m.
/mjt
On 28/05/2025 10.30, Thomas Huth wrote:
On 27/05/2025 19.20, Thomas Huth wrote:
On 12/05/2025 10.39, Philippe Mathieu-Daudé wrote:
The "fallback" property was only used by the hw_compat_2_5[] array,
as 'fallback=144'. We removed all machines using that array, lets
remove ISA floppy drive 'fallb
Il ven 9 mag 2025, 09:58 Daniel P. Berrangé ha
scritto:
> On Fri, May 09, 2025 at 07:48:57AM +0200, Markus Armbruster wrote:
> > Nabih Estefan writes:
> >
> > > From: Peter Foley
> > >
> > > e.g.
> > > I 2025-02-28 09:51:05.240071-0800 624 stream.go:47
> qemu: Uninitialized value
This reverts commit 3d5b2f81fbc6b96b70271af1820674731a441ff7.
It should not be in 10.0.x branch, since we do support python 3.8
in 10.0.
Signed-off-by: Michael Tokarev
diff --git a/configure b/configure
index a2f5597fa0..02f1dd2311 100755
--- a/configure
+++ b/configure
@@ -540,17 +540,17 @@ if
The following patches are queued for QEMU stable v10.0.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-10.0
There's a single revert of a commit in 10.0.1 which should not
be there in the first place, as a quick fix.
Thanks!
/mjt
--
01 6f7a53e58e
On 28/05/2025 03.47, Gustavo Romero wrote:
The current links for the Linux and initrd.gz images are not truly
immutable, so let's change them to point to immutable versions, to avoid
having to keep updating their SHAs.
Signed-off-by: Gustavo Romero
---
tests/functional/test_aarch64_hotplug_pc
Hi Zhao,
Thanks again for the info!
You're right — I just tested the latest master (including commits 5979f50fa9fd
and 7a4861230676), and the issue is indeed fixed there. macOS guests now boot
successfully with TCG and multiple vCPUs, without needing my patch.
I’ll go ahead and drop the revert
On 28/05/2025 09.53, Michael Tokarev wrote:
This reverts commit 3d5b2f81fbc6b96b70271af1820674731a441ff7.
It should not be in 10.0.x branch, since we do support python 3.8
in 10.0.
Signed-off-by: Michael Tokarev
...
diff --git a/tests/docker/dockerfiles/python.docker
b/tests/docker/dockerfi
On Wed, 28 May 2025 00:52:40 +0100,
Miguel Luis wrote:
>
>
>
> > On 27 May 2025, at 16:52, Marc Zyngier wrote:
> >
> > On Tue, 27 May 2025 16:55:32 +0100,
> > Miguel Luis wrote:
> >>
>> Result on the guest: Splat at early_kvm_mode_cfg, boot proceeds, ends up in
>> hard lockup splat.
> >
On 28/05/2025 05.01, Xiaoyao Li wrote:
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
(series reviewed)
Since v3:
- Fixed 2 issues noticed by Thomas (floppy fallback, e1000)
Since v2:
- Removed qtest in test-x86-cpuid-compat.c
Since v1:
- Fixed issues noticed by Thomas
The versioned 'pc
在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
> Hi all,
>
> This series addressed a couple of missing Bonito functionalities
> I found when I was trying to test NetBSD against QEMU.
Hi Philippe,
A gentle ping :-)
Do you have bandwidth on MIPS recently?
I'm planning to respin my CPS SMP series as well.
From: Thomas Huth
Now that the endianness of the petalogix-s3adsp1800 can be configured,
we should test that the cross-endianness also works as expected, thus
test the big endian variant on the little endian target and vice versa.
(based on an original idea from Philippe Mathieu-Daudé)
Reviewed-
From: Thomas Huth
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-wired to "true", see commits
133d23b3ad1 and a88bbb006a52), so the variants that showed up
on the big endian target likely never worked. We deprecated these
non-working machine varia
From: Thomas Huth
Use self.set_machine() to set the machine instead of relying on the
default machine of the binary. This way the test can be skipped in
case the machine has not been compiled into the QEMU binary.
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Signed-off-by: Thomas Huth
Mess
From: Philippe Mathieu-Daudé
The X86MachineClass::save_tsc_khz boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it and simplify tsc_khz_needed().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Reviewe
From: Philippe Mathieu-Daudé
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the qtest in test
From: Philippe Mathieu-Daudé
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the hw_compat_2_4[]
array, via the 'x-disable-pcie=false' property. We removed all
machines using that array, lets remove all the code around
VIRTIO_PCI_FLAG_DISABLE_PCIE (see commit 9a4c0e220d8 for similar
VIRTIO_PCI_FLAG
From: Philippe Mathieu-Daudé
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT, including the now
unused PVSCSIState::compat_flag
From: Matheus Tavares Bernardino
The test fails with --enable-asan as the error struct is never freed.
In the case where the test expects a success but it fails, let's also
report the error for debugging (it will be freed internally).
Fixes 316e8ee8d6 ("util/qemu-sockets: Refactor inet_parse() t
From: Philippe Mathieu-Daudé
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the now unused em
From: Philippe Mathieu-Daudé
The PCMachineClass::broken_reserved_end field was only used
by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed.
Remove it and simplify pc_memory_init().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Rev
From: Philippe Mathieu-Daudé
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Message-ID: <20250512083948.392
From: Philippe Mathieu-Daudé
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the
hw_compat_2_4[] array, via the 'migrate-extra=true'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-b
From: Philippe Mathieu-Daudé
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION was only used by the
hw_compat_2_5[] array, via the 'x-old-pci-configuration=on'
property. We removed all machines using that array, lets remove
all the code around PVSCSI_COMPAT_OLD_PCI_CONFIGURATION.
Signed-off-by: Philippe Mathi
From: Philippe Mathieu-Daudé
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Message-ID: <20250512083948.392
From: Philippe Mathieu-Daudé
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC, including the MAC_ACCESS_FLAG_NEEDED enum,
similarly to commit fa4ec9ffda7
From: Philippe Mathieu-Daudé
The MachineClass::legacy_fw_cfg_order boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it along with:
- FW_CFG_ORDER_OVERRIDE_* definitions
- fw_cfg_set_order_override()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- r
From: Thomas Huth
By using self.set_machine() the tests get properly skipped in case
the machine has not been compiled into the QEMU binary, e.g. when
"configure" has been run with "--without-default-devices".
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Th
From: Philippe Mathieu-Daudé
VMXNET3_COMPAT_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé
Revie
Hi!
The following changes since commit 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into
staging (2025-05-26 10:16:59 -0400)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2025-0
From: Thomas Huth
The problem with the PCI bridge has been fixed in commit e5894fd6f411c1
("hw/pci-host/gt64120: Fix endianness handling"), so we can enable the
corresponding test again.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
Message-ID: <20250
From: Alexandr Moshkov
Add new tests to check the correctness of the `-overcommit memlock`
option (possible values: off, on, on-fault) by using
`/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck
values:
* if `memlock=off`, then VmLck = 0;
* if `memlock=on`, then VmLck > 0 and alm
From: Thomas Huth
The (former big-endian only) binary qemu-system-microblaze can
handle both endiannesses nowadays, so we don't need the separate
qemu-system-microblazeel binary for little endian anymore. Let's
deprecate it to avoid unnecessary compilation and test time in
the future.
Reviewed-b
From: Philippe Mathieu-Daudé
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Message-ID: <20250512083948.392
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