On Sun, May 25, 2025 at 05:02:19PM +0100, Richard Henderson wrote:
> Return a constant 0 from reg_for_read, and a new
> temporary from reg_for_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 24 ++--
> 1
On Sun, May 25, 2025 at 05:02:20PM +0100, Richard Henderson wrote:
> Require TCGv_i32 and TCGv be identical, so drop
> the extensions. Return constants when possible
> instead of a mov into a temporary. Return register
> inputs unchanged when possible.
>
> Signed-off-by: Richard Henderson
Revi
On Sun, May 25, 2025 at 05:02:18PM +0100, Richard Henderson wrote:
> Now that the extended address instructions are handled separately
> from virtual addresses, we can narrow the emulation to 32-bit.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Richard Henderson
> ---
> configs/targets/
On Sun, May 25, 2025 at 05:02:17PM +0100, Richard Henderson wrote:
> Use TARGET_FMT_lx to match the target_ulong type of vaddr.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/mmu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> d
+Markus
On 24/5/25 13:55, Richard Henderson wrote:
On 5/15/25 14:20, Thomas Huth wrote:
+static int machine_get_endianness(Object *obj, Error **errp
G_GNUC_UNUSED)
+{
+ S3Adsp1800MachineState *ms = PETALOGIX_S3ADSP1800_MACHINE(obj);
+ return ms->endianness;
+}
+
+static void machine_set_
On 16/5/25 16:06, Thomas Huth wrote:
On 16/05/2025 17.00, Philippe Mathieu-Daudé wrote:
On 15/5/25 15:20, Thomas Huth wrote:
From: Thomas Huth
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-wired to "true", see commits
133d23b3ad1 and a88bbb00
Hi Richard,
May 25, 2025 at 2:14 PM, Richard Henderson wrote:
> Having read the whole series now, I think it would be better to change the
> TCGCPUOps.do_interrupt interface.
>
> Instead of having each target call qemu_plugin_*, instead have each
> do_interrupt return the discontinuity type, or
>-Original Message-
>From: Steven Sistare
>Subject: Re: [PATCH V3 29/42] backends/iommufd: change process ioctl
>
>On 5/23/2025 10:56 AM, Steven Sistare wrote:
>> On 5/23/2025 4:56 AM, Duan, Zhenzhong wrote:
-Original Message-
From: Steven Sistare
Subject: Re: [PA
On 21.05.2025 16:52, Juraj Marcin wrote:
From: Juraj Marcin
Commit aec21d3175 (qapi: Add InetSocketAddress member keep-alive)
introduces the keep-alive flag, but this flag is not copied together
with other options in qio_dns_resolver_lookup_sync_inet().
This patch fixes this issue and also pre
On 21/5/25 17:42, Alex Bennée wrote:
From: Dominik 'Disconnect3d' Czarnota
This commit adds support for the `qGDBServerVersion` packet to the qemu
gdbstub which could be used by clients to detect the QEMU version
(and, e.g., use a workaround for known bugs).
This packet is not documented/stan
Use an explicit 64-bit type for the address to store in EAR.
Signed-off-by: Richard Henderson
---
target/microblaze/op_helper.c | 70 +--
1 file changed, 42 insertions(+), 28 deletions(-)
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
v1:
https://lore.kernel.org/qemu-devel/20250212220155.1147144-1-richard.hender...@linaro.org/
Use out-of-line helpers to implement extended address memory ops.
With this, we can reduce TARGET_LONG_BITS to the more natural 32
for this 32-bit cpu.
Changes for v2:
- Handle alignment check inline,
Use an explicit 64-bit type for the address to store in EAR.
Signed-off-by: Richard Henderson
---
target/microblaze/helper.c | 64 +-
1 file changed, 36 insertions(+), 28 deletions(-)
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index
Signed-off-by: Richard Henderson
---
target/microblaze/helper.h | 12 ++--
target/microblaze/helper.c | 7 +++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index f740835fcb..41f56a5601 100644
--- a/target/micr
Use TARGET_FMT_lx to match the target_ulong type of vaddr.
Signed-off-by: Richard Henderson
---
target/microblaze/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 95a12e16f8..8703ff5c65 100644
--- a/target/microbl
Use helpers and address_space_ld/st instead of inline
loads and stores. This allows us to perform operations
on physical addresses wider than virtual addresses.
Signed-off-by: Richard Henderson
---
target/microblaze/helper.h| 10 +++
target/microblaze/op_helper.c | 40 ++
Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.
Signed-off-by: Richard Henderson
---
configs/targets/microblaze-softmmu.mak | 4 +---
configs/targets/microblazeel-softmmu.mak | 4 +---
2 files changed, 2 insertion
Use an explicit 64-bit type for EAR.
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 2 +-
target/microblaze/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6ad8643f2e..3ce28b302f 1006
Use an explicit 64-bit type for extended addresses.
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b1fc9e5624..dc
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 24 ++--
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/transl
Require TCGv_i32 and TCGv be identical, so drop
the extensions. Return constants when possible
instead of a mov into a temporary. Return register
inputs unchanged when possible.
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 26 +-
1 file changed,
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
WRMSRNS doesn't become a required feature for FERD, and Linux has
removed the dependency, as such remove it from Qemu.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 4
1 file changed, 4 deletions(-)
diff --
Hi Eric,
On 5/22/25 22:13, Gustavo Romero wrote:
Hi Eric,
While we go through the ACPI PCI Hotplug series [0] and review it, I'm
starting to take a look at tests/qtest/bios-tables-test.c.
You mentioned testing the combinations of "acpi-root-pci-hotplug"
and "acpi-pci-hotplug-with-bridge-suppor
On Sun, May 25, 2025 at 05:02:12PM +0100, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/helper.h | 12 ++--
> target/microblaze/helper.c | 7 +++
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff -
On Sun, May 25, 2025 at 05:02:13PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/op_helper.c | 70 +--
> 1 file chang
On Sun, May 25, 2025 at 05:02:11PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/helper.c | 64 +-
> 1 file chang
On Sun, May 25, 2025 at 05:02:14PM +0100, Richard Henderson wrote:
> Use helpers and address_space_ld/st instead of inline
> loads and stores. This allows us to perform operations
> on physical addresses wider than virtual addresses.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Ig
On Sun, May 25, 2025 at 05:02:16PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for extended addresses.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 24
> 1 file changed, 12 insertions(+)
On Sun, May 25, 2025 at 05:02:15PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Richard Henderson
> ---
> target/microblaze/cpu.h | 2 +-
> target/microblaze/translate.c | 2 +-
> 2 files changed, 2 insertions(
Hi Eric,
On 14/5/25 18:01, Eric Auger wrote:
QEMU will notify the OS about PCI hotplug/hotunplug events through
GED interrupts. Let the GED device handle a new PCI hotplug event.
On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK
mutex held.
The GED device uses a dedicated MMIO
Hi Richard,
CC-ing all the maintainers again.
Richard Henderson wrote:
> On 5/19/25 16:19, Julian Ganz wrote:
> > +QEMU_DISABLE_CFI
> > +static void plugin_vcpu_cb__discon(CPUState *cpu,
> > + enum qemu_plugin_discon_type type,
> > +
Hi Richard,
> On 5/19/25 16:19, Julian Ganz wrote:
> > diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> > index 486823094c..08f0ed9b89 100644
> > --- a/target/openrisc/interrupt.c
> > +++ b/target/openrisc/interrupt.c
> > @@ -25,11 +25,13 @@
> > #ifndef CONFIG_USER_ONLY
>
Hi Richard,
Richard Henderson wrote:
> On 5/19/25 16:19, Julian Ganz wrote:
> > diff --git a/plugins/core.c b/plugins/core.c
> > index dc1f5cb4d8..f07813d588 100644
> > --- a/plugins/core.c
> > +++ b/plugins/core.c
> > @@ -104,6 +104,44 @@ static void plugin_vcpu_cb__simple(CPUState *cpu, enum
>
On Thu, May 22, 2025 at 12:39 PM Akihiko Odaki wrote:
>
> On 2025/05/22 10:50, 'Jason Wang' via devel wrote:
> > On Wed, May 21, 2025 at 11:51 AM Akihiko Odaki
> > wrote:
> >>
> >> On 2025/05/21 9:51, Jason Wang wrote:
> >>> On Fri, May 16, 2025 at 11:29 AM Akihiko Odaki
> >>> wrote:
>
>
On 22/5/25 11:35, Akihiko Odaki wrote:
On 2025/05/22 19:31, Alex Bennée wrote:
Akihiko Odaki writes:
On 2025/05/22 1:42, Alex Bennée wrote:
The user can run a subset of the tcg tests directly, e.g.:
make run-tcg-tests-hexagon-linux-user
but in this case we fail if there has not been a fu
On 22/5/25 06:19, Akihiko Odaki wrote:
On 2025/05/22 1:42, Alex Bennée wrote:
From: Nabih Estefan
../tests/qtest/libqos/igb.c:106:5: runtime error: load of
misaligned address 0x562040be8e33 for type 'uint32_t', which requires
4 byte alignment
Instead of straight casting the uint8_t arra
On 22/5/25 06:45, Akihiko Odaki wrote:
On 2025/05/22 1:42, Alex Bennée wrote:
It's easy to get lost in zeros while setting the numbers of
instructions per second. Add a scaling suffix to make things simpler.
Signed-off-by: Alex Bennée
Reviewed-by: Pierrick Bouvier
---
v2
- normalise the s
On 21/5/25 17:42, Alex Bennée wrote:
Thanks for volunteering to help.
Cc: Akihiko Odaki
Cc: Dmitry Osipenko
Signed-off-by: Alex Bennée
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
On 21/5/25 15:37, Thomas Huth wrote:
From: Thomas Huth
By using self.set_machine() the tests get properly skipped in case
the machine has not been compiled into the QEMU binary, e.g. when
"configure" has been run with "--without-default-devices".
Signed-off-by: Thomas Huth
---
tests/functio
On 14/5/25 18:00, Eric Auger wrote:
No need to export aml_pci_device_dsm() as it is only used
in hw/i386/acpi-build.c.
Signed-off-by: Eric Auger
---
include/hw/acpi/pci.h | 1 -
hw/i386/acpi-build.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Dau
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Michael,
On 5/20/25 15:46, Cédric Le Goater wrote:
@@ -1010,6 +1017,8 @@ static void vfio_iommu_map_dirty_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
ram_addr_t translated_addr;
Error *local_err = NULL;
int ret = -EINVAL;
+ MemoryRegion *mr;
+ ram_addr_t xlat;
xla
>-Original Message-
>From: Nicolin Chen
...
>> >I think you did some substantial work to isolate the get_hw_info
>> >part inside the iommufd backend code, which looks nice and clean
>> >as the vIOMMU code simply does iodc->get_cap().
>> >
>> >However, that then makes these direct raw ba
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
The immediate form of MSR access instructions will use this new CPU
feature word.
Signed-off-by: Xin Li (Intel)
---
target/i386/cpu.c | 23 ++-
target/i386/cpu.h | 1 +
2 files changed, 23 insertions(+), 1 deletion(-)
diff --g
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH rfcv3 15/21] intel_iommu: Bind/unbind guest page table to
...
>> yes based on the current design. when guest GPTT==PT, attach device
>> to S2 hwpt, when it goes to S1, then attach it to a S1 hwpt whose
>> parent is the aforeme
On 2025/05/26 9:41, Jason Wang wrote:
On Thu, May 22, 2025 at 12:39 PM Akihiko Odaki wrote:
On 2025/05/22 10:50, 'Jason Wang' via devel wrote:
On Wed, May 21, 2025 at 11:51 AM Akihiko Odaki wrote:
On 2025/05/21 9:51, Jason Wang wrote:
On Fri, May 16, 2025 at 11:29 AM Akihiko Odaki wrote:
Add new tests to check the correctness of the `-overcommit memlock`
option (possible values: off, on, on-fault) by using
`/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck
values:
* if `memlock=off`, then VmLck = 0;
* if `memlock=on`, then VmLck > 0 and almost all memory is residen
Used in future commit to skipping execution of a tests if the system's
locked memory limit is below the required threshold.
Signed-off-by: Alexandr Moshkov
Reviewed-by: Thomas Huth
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/functional/qemu_test/decorators.py | 18 ++
Add new tests to check the correctness of the `-overcommit memlock`
option (possible values: off, on, on-fault) by using
`/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck values:
* if `memlock=off`, then VmLck = 0;
* if `memlock=on`, then VmLck > 0 and almost all memory is res
On 25.05.2025 03:42, Helge Deller wrote:
On 5/24/25 12:26, Michael Tokarev wrote:
On 17.05.2025 15:00, del...@kernel.org wrote:
From: Helge Deller
This series fixes and improves the floating point exception
handling in the hppa system and user emulation.
A testcase is included in patch #3.
P
On 24/05/2025 17.38, Alex Bennée wrote:
Gustavo Romero writes:
Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and
hot-unplug on arm64.
Signed-off-by: Gustavo Romero
Reviewed-by: Daniel P. Berrangé
---
MAINTAINERS | 5 ++
tests/functi
On 25/05/2025 21.19, Philippe Mathieu-Daudé wrote:
On 16/5/25 16:06, Thomas Huth wrote:
On 16/05/2025 17.00, Philippe Mathieu-Daudé wrote:
On 15/5/25 15:20, Thomas Huth wrote:
From: Thomas Huth
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-w
On 22/05/2025 21.05, Pierrick Bouvier wrote:
From: Daniel P. Berrangé
This removes the TARGET_S390X and CONFIG_KVM conditions from the
CPU commands that are conceptually specific to s390x. Top level
stubs are provided to cope with non-s390x targets, or builds
without KVM.
The removal of CONFIG
Fabiano Rosas writes:
> Commit 407bc4bf90 ("qapi: Move include/qapi/qmp/ to include/qobject/")
> brought the migration-helpers.c back by mistake. This file has been
> replaced with migration/migration-qmp.c and
> migration/migration-util.c.
>
> Fixes: 407bc4bf90 ("qapi: Move include/qapi/qmp/ to
marcandre.lur...@redhat.com writes:
> From: BALATON Zoltan
>
> Quoting Volker Rümelin: "try-poll=on tells the ALSA backend to try to
> use an event loop instead of the audio timer. This works most of the
> time. But the poll event handler in the ALSA backend has a bug. For
> example, if the guest
Update the aarch64 'virt' base blob and all of its variants. All of them
have the same diff, so only one is shown below. The essential changes is
in the AML code of the _OSC (OS Capabilities) method, (variable name
from 'CTRL' to 'Local0') and the scope for GED device.
DSDT table diff:
Definitio
scripts/checkpatch.pl warns for __linux__ saying "architecture specific
defines should be avoided".
Signed-off-by: Akihiko Odaki
---
include/qemu/thread-posix.h | 2 +-
util/qemu-thread-posix.c| 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/qemu/thread-posi
Use the futex-based implementation of QemuEvent on Windows to
remove code duplication and remove the overhead of event object
construction and destruction.
Signed-off-by: Akihiko Odaki
---
include/qemu/thread-posix.h | 9
include/qemu/thread-win32.h | 6 ---
include/qemu/thread.h
Add a test to verify that the aarch64 'virt' machine correctly generates
the ACPI tables and AML code for PCI device hotplug.
Signed-off-by: Gustavo Romero
---
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | 0
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/qtest/bios-tables-test.c
Windows supports futex-like APIs since Windows 8 and Windows Server
2012.
Signed-off-by: Akihiko Odaki
---
meson.build | 2 ++
include/qemu/futex.h | 53 ++-
tests/unit/test-aio-multithread.c | 2 +-
util/lockcnt.c
futex(2) - Linux manual page
https://man7.org/linux/man-pages/man2/futex.2.html
> Note that a wake-up can also be caused by common futex usage patterns
> in unrelated code that happened to have previously used the futex
> word's memory location (e.g., typical futex-based implementations of
> Pthrea
sem in AppleGFXReadMemoryJob is an one-shot event so it can be converted
into QemuEvent, which is more specialized for such a use case.
Signed-off-by: Akihiko Odaki
---
hw/display/apple-gfx.m | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/display/apple-gfx.m b/
pause_event can utilize qemu_event_reset() to discard events.
Signed-off-by: Akihiko Odaki
---
migration/migration.h | 2 +-
migration/migration.c | 21 +
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/migration/migration.h b/migration/migration.h
index d53
This unlocks the futex-based implementation of QemuLockCnt to Windows.
Signed-off-by: Akihiko Odaki
---
include/qemu/lockcnt.h | 2 +-
util/lockcnt.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/qemu/lockcnt.h b/include/qemu/lockcnt.h
index f4b62a3f
thread_sync_sem is an one-shot event so it can be converted into
QemuEvent, which is more lightweight.
Signed-off-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
---
migration/migration.h| 4 ++--
migration/postcopy-ram.c | 10 +-
migration/savevm.c | 2 +-
3 files changed, 8 i
In a recent discussion, Phil Dennis-Jordan pointed out a quirk in
QemuEvent destruction due to futex-like abstraction, which prevented
the usage of QemuEvent in new and existing code[1]. With some more
thoughts after this discussion, I also found other problem and room
of improvement in futex usage
qemu-thread used to abstract pthread primitives into futex for the
QemuEvent implementation of POSIX systems other than Linux. However,
this abstraction has one key difference: unlike futex, pthread
primitives require an explicit destruction, and it must be ordered after
wait and wake operations.
colo_exit_sem and colo_incoming_sem represent one-shot events so they
can be converted into QemuEvent, which is more lightweight.
Signed-off-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
---
migration/migration.h | 6 +++---
migration/colo.c | 20 ++--
2 files changed, 13 i
The pair of smp_mb() and qatomic_read() sometimes allows skipping the
following qatomic_xchg() call, but it is unclear if it improves
performance so remove it.
Commit 374293ca6fb0 ("qemu-thread: use acquire/release to clarify
semantics of QemuEvent") replaced atomic_mb_read() in qemu_event_set()
w
Update the .acpipcihp blob variant for the aarch64 'virt' machine. Since
this is a new blob, the diff is large and not particularly useful, so
below is the diff against the base DSDT blob with ACPI PCI off.
Main changes include:
a) The _OSC method, which now allows the platform to control PCIe
ACPI PCI hotplug is now turned on by default so we need to change the
existing tests to keep it off. However, even setting the ACPI PCI
hotplug off in the existing tests, there will be changes in the ACPI
tables because the _OSC method was modified, hence in the next patch of
this series the blobs
This series updates the existing ACPI tests to work with the new support
for ACPI PCI hotplug on aarch64, which is now enabled by default in the
'virt' machine. Because ACPI PCI hotplug is now enabled by default it's
necessary to disable it (acpi-pcihp=off) for the existing tests, because
they use
Hi Eric,
On 5/14/25 14:00, Eric Auger wrote:
This series enables ACPI PCI hotplug/hotunplug on ARM
and makes it default for 10.1 machine type. This aligns with
x86 q35 machine. Expected benefits should be similar to
those listed in [1].
It is still possible to disable it using a virt machine
op
The following patches are queued for QEMU stable v7.2.18:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2025-05-24, and the release is planned for 2025-05-26:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any patches
you
From: Akihiko Odaki
virtio-net expects set_features() will be called when the feature set
used by the guest changes to update the number of virtqueues but it is
not called during reset, which will clear all features, leaving the
queues added for VIRTIO_NET_F_MQ or VIRTIO_NET_F_RSS. Not only these
From: Icenowy Zheng
The j pseudoinstruction maps to a JAL instruction, which can only handle
a jump to somewhere with a signed 20-bit destination. In case of static
linking and LTO'ing this easily leads to "relocation truncated to fit"
error.
Switch to use tail pseudoinstruction, which is the st
From: Loïc Lefort
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-ID: <20250313193011.720075-3-l...@rivosinc.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherry picked from commit 915b203745540e
The following patches are queued for QEMU stable v9.2.4:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-05-24, and the release is planned for 2025-05-26:
https://wiki.qemu.org/Planning/9.2
Please respond here or CC qemu-sta...@nongnu.org on any patches
you t
From: Max Chou
According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.
The vs1 EEW of vrgatherei16.vv is 16.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <
From: Akihiko Odaki
virtio-net expects set_features() will be called when the feature set
used by the guest changes to update the number of virtqueues but it is
not called during reset, which will clear all features, leaving the
queues added for VIRTIO_NET_F_MQ or VIRTIO_NET_F_RSS. Not only these
From: Max Chou
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-8-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherr
From: Daniel Henrique Barboza
'reglist' is being g-malloc'ed but never freed.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-ID: <20250429124421.223883-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Franc
From: Max Chou
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-7-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherr
From: Anton Blanchard
Signed-off-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Max Chou
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-3-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherry picked from commit b0450a101d6
On Mon, Mar 17, 2025 at 9:07 AM Akihiko Odaki wrote:
>
> Commit 90320051ea99 ("spiceaudio: add a pcm_ops buffer_get_free
> function") caused to emit messages saying "Resetting rate control"
> frequently when the guest generates no frames.
>
> audio_rate_peek_bytes() resets the rate control when fr
The following patches are queued for QEMU stable v9.2.4:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-05-24, and the release is planned for 2025-05-26:
https://wiki.qemu.org/Planning/9.2
v3: drop single riscv-related change:
51 73f81da0a362 Daniel Henriqu
From: Anton Blanchard
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Max Chou
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-2-ma
From: Daniel Henrique Barboza
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_
From: Max Chou
Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-9-max.c...@s
From: Fabiano Rosas
ASAN spotted a leaking string in machine_set_loadparm():
Direct leak of 9 byte(s) in 1 object(s) allocated from:
#0 0x560ffb5bb379 in malloc
../projects/compiler-rt/lib/asan/asan_malloc_linux.cpp:69:3
#1 0x7f1aca926518 in g_malloc ../glib/gmem.c:106
#2 0x7f1aca94
From: Daniel Henrique Barboza
At this moment we're not checking if the host has support for any
specific CSR before doing get/put regs. This will cause problems if the
host KVM doesn't support it (see [1] as an example).
We'll use the same approach done with the CPU extensions: read all known
KV
From: Peter Xu
With commit 82137e6c8c ("migration: enforce multifd and postcopy preempt to
be set before incoming"), and if postcopy preempt / multifd is enabled, one
cannot setup any capability because these checks would always fail.
(qemu) migrate_set_capability xbzrle off
Error: Postcopy pree
From: Helge Deller
The hardware stores the instruction code in the lower bits of the FP
exception register #1 on FP assist traps.
This fixes the FP exception handler on Linux, as the Linux kernel uses
the value to decide on the correct signal which should be pushed into
userspace (see decode_fpu(
From: Rakesh Jeyasingh
The GT-64120 PCI controller requires special handling where:
1. Host bridge(bus 0 ,device 0) must never be byte-swapped
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
The previous implementation incorrectly swapped all accesses, breaking
host bridge detection (lspci
From: Daniel Henrique Barboza
This change is motivated by a future change w.r.t CSRs management. We
want to handle them the same way as KVM extensions, i.e. a static array
with KVMCPUConfig objs that will be read/write during init and so on.
But to do that properly we must be able to declare a st
From: Max Chou
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-5-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherr
From: Ziqiao Kong
On big endian systems, pte and updated_pte hold big endian host data
while pte_pa points to little endian target data. This means the branch
at cpu_helper.c:1669 will be always satisfied and restart translation,
causing an endless translation loop.
The correctness of this patch
From: Anton Blanchard
vslidedown always zeroes elements past vl, where it should use the
tail policy.
Signed-off-by: Anton Blanchard
Reviewed-by: Alistair Francis
Message-ID: <20250414213006.3509058-1-ant...@tenstorrent.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
(cherry p
From: Max Chou
According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-11-max.c...@sifive.com>
Signed-off-by: Alistair Francis
1 - 100 of 157 matches
Mail list logo
