[Stable-9.2.4 43/62] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

[Michael Tokarev]

From: Max Chou <max.c...@sifive.com>

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
Message-ID: <20250408103938.3623486-5-max.c...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Cc: qemu-sta...@nongnu.org
(cherry picked from commit fbeaf35838768086b435833cb4dc5182c73ec2bc)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4a0c9fbeff..e8197f779e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -412,7 +412,8 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, 
int vm)
 {
     return require_vm(vm, vd) &&
            require_align(vd, s->lmul) &&
-           require_align(vs, s->lmul);
+           require_align(vs, s->lmul) &&
+           vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
 }
 
 /*
-- 
2.39.5