Re: [PATCH] target/riscv: add satp mode for kvm host cpu

On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: > This patch adds host satp mode while kvm/host cpu satp mode is not > set. Huh, the KVM side[1] was written for this purpose, but it appears we never got a QEMU side merged. [1] commit 2776421e6839 ("RISC-V: KVM: provide UAPI for host SA

Re: [PATCH v3 1/3] hw/misc/aspeed_otp: Add Aspeed OTP memory device model

On 4/23/25 04:56, Kane Chen wrote: From: Kane-Chen-AS This introduces a new model for the ASPEED OTP (One-Time Programmable) memory. The device is implemented as a `SysBusDevice` and provides an abstracted interface for OTP read, write (program), and default value initialization. OTP content i

Re: [PATCH v3 2/3] hw/misc/aspeed_sbc: Connect Aspeed OTP memory device to SBC controller

On 4/23/25 04:56, Kane Chen wrote: From: Kane-Chen-AS This patch integrates the `aspeed.otpmem` device with the ASPEED Secure Boot Controller (SBC). The SBC now accepts an OTP backend via a QOM link property ("otpmem"), enabling internal access to OTP content for controller-specific logic. Thi

Re: [PATCH] hw/rdma: Add initial Support for Vhost-User-Rdma Device

On Mon, Apr 28, 2025 at 10:12:16AM +0800, Weimin Xiong wrote: > From: xiongweimin > > Add initial support for vhost-user-rdma device model for qemu, > this includes the interaction(e.g feature negotiation, setting > vring baseaddr, setting device status) between guest kernel and > host vhost-user

Re: [PATCH 3/5] i386/kvm: Support event with select & umask format in KVM PMU filter

Zhao Liu writes: > Hi Markus, > >> > +case KVM_PMU_EVENT_FORMAT_X86_SELECT_UMASK: { >> > +if (event->u.x86_select_umask.select > UINT12_MAX) { >> > +error_setg(errp, >> > + "Parameter 'select' out of range (%d).", >> > +

Re: [PATCH 2/5] i386/kvm: Support basic KVM PMU filter

Zhao Liu writes: > ... > >> > diff --git a/qemu-options.hx b/qemu-options.hx >> > index dc694a99a30a..51a7c61ce0b0 100644 >> > --- a/qemu-options.hx >> > +++ b/qemu-options.hx >> > @@ -232,7 +232,8 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, >> > "eager-split-size=n (KVM Eage

[PATCH 17/26] target/riscv: convert SiFive E CPU models to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 74 -- 2 files changed, 21 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4cfdb74891e

[PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types

Do not create the RHCT MMU type entry for RV32 CPUs, since it only has definitions for SV39/SV48/SV57. Likewise, check that satp_mode_max_from_map() will actually return a valid value, skipping the MMU type entry if all MMU types were disabled on the command line. Acked-by: Alistair Francis Sign

[PATCH 16/26] target/riscv: convert dynamic CPU models to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 113 + 1 file changed, 31 insertions(+), 82 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93992be6c4d..56f292a3616 100644 --- a/target/riscv/

[PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid

Check that the argument to set_satp_mode_max_supported is valid for the MXL value of the CPU. It would be a bug in the CPU definition if it weren't. In fact, there is such a bug in riscv_bare_cpu_init(): not just SV64 is not a valid VM mode for 32-bit CPUs, SV64 is not a valid VM mode at all, not

[PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc

In preparation for adding a function to merge two RISCVCPUConfigs (pulling values from the parent if they are not overridden) annotate cpu_cfg_fields.h.inc with the default value of the fields. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h| 2

[PATCH 05/26] target/riscv: remove supported from RISCVSATPMap

"supported" can be computed on the fly based on the max_satp_mode. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 4 +--- target/riscv/cpu.c | 34 -- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/ta

[PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function

Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 21 ++--- 1 file changed, 10 insertions(+

[PATCH 15/26] target/riscv: convert bare CPU models to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 58 ++ 1 file changed, 17 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c07ce5ddb9b..93992be6c4d 100644 --- a/target/riscv/

[PATCH 12/26] target/riscv: add more RISCVCPUDef fields

Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis Signed-o

[PATCH 21/26] target/riscv: generalize custom CSR functionality

While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h| 15 --- target/riscv/cpu.c| 25 - target/riscv/csr.c| 2 +- target/riscv/th_c

[PATCH 14/26] target/riscv: convert profile CPU models to RISCVCPUDef

Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent pr

[PATCH 25/26] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 80 +- 1 file changed, 23 insertions(+), 57 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6cdb92c8a4c..e7e9e6bfe80 100644 --- a/target/riscv/

[PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 61 +- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5045ebc0b70..f3af9643af4 100644 --- a/target/riscv/

[PATCH 24/26] target/riscv: convert Ventana V1 to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 75 ++ 1 file changed, 35 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 20a68ba43c4..6cdb92c8a4c 100644 --- a/target/riscv/

[PATCH 19/26] target/riscv: convert SiFive U models to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 79 +++--- 2 files changed, 37 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 0f9be15e47b

[PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties

Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[]. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv

[PATCH 18/26] target/riscv: convert ibex CPU models to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 39 --- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5b4ffc285da..4f531711655 100644 --- a/target/riscv/cpu.c +

[PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef

Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Reviewed-by: Alis

[PATCH 07/26] target/riscv: introduce RISCVCPUDef

Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 target/riscv/cpu.c | 27 ++

[PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive

In preparation for generalizing the custom CSR functionality, make the test return bool instead of int. Make the insertion_test optional, too. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/th_csr.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-

[PATCH 26/26] target/riscv: remove .instance_post_init

Unlike other uses of .instance_post_init, accel_cpu_instance_init() *registers* properties, and therefore must be run before device_post_init() which sets them to their values from -global. In order to move all registration of properties to .instance_init, call accel_cpu_instance_init() at the end

[PATCH 23/26] target/riscv: convert TT Ascalon to RISCVCPUDef

Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 127 + 1 file changed, 60 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3af9643af4..20a68ba43c4 100644 --- a/target/riscv/

[PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig

They are used to provide the nice QOM properties for svNN, but the canonical source of the CPU configuration is now cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 14 ++ target/riscv/

[PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file

To support merging a subclass's RISCVCPUDef into the superclass, a list of all the CPU features is needed. Put them into a header file that can be included multiple times, expanding the macros BOOL_FIELD and TYPE_FIELD to different operations. Reviewed-by: Alistair Francis Signed-off-by: Paolo B

[PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class

Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.

[PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer

The maximum available SATP mode implies all the shorter virtual address sizes. Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_map. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 11 +-

Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table

On Wed, 23 Apr 2025 11:51:41 -0400 "Michael S. Tsirkin" wrote: Hi Michael, > On Wed, Apr 23, 2025 at 04:47:20PM +0100, Jonathan Cameron wrote: > > On Wed, 23 Apr 2025 11:35:46 -0400 > > "Michael S. Tsirkin" wrote: > > > > > On Wed, Apr 23, 2025 at 10:15:42PM +0800, Yicong Yang wrote: > > >

Re: [PATCH v3 1/9] target/riscv/kvm: minor fixes/tweaks

On Sat, Apr 26, 2025 at 2:05 AM Daniel Henrique Barboza wrote: > > Remove an unused 'KVMScratchCPU' pointer argument in > kvm_riscv_check_sbi_dbcn_support(). > > Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will > make a future patch diff easier to read, when changes in > kv

Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong

On 4/27/25 2:59 AM, Andrew Jones wrote: On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote: We want to support scounteren as a KVM CSR. The KVM UAPI defines every CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. The other existing cases where the pr

Re: [PATCH v4 1/8] new configure option to enable gstreamer

On Mon, Apr 28, 2025 at 12:07 PM Dietmar Maurer wrote: > > GStreamer is required to implement H264 encoding for VNC. Please note > that QEMU already depends on this library when you enable Spice. > > Signed-off-by: Dietmar Maurer Reviewed-by: Marc-André Lureau > --- > meson.build

Re: [PATCH v3 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()

On Sat, Apr 26, 2025 at 2:06 AM Daniel Henrique Barboza wrote: > > 'reglist' is being g-malloc'ed but never freed. > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c |

Re: [PATCH] ui/gtk: Properly apply x/y scale when rendering GL area

Hi On Sat, Apr 19, 2025 at 1:51 PM Weifeng Liu wrote: > > On startup, scale_x and scale_y were set to 1 that didn't reflect the > real situation of the scan-out, resulting in incorrect cursor > coordinates to be sent when moving the mouse pointer. Simply updating > the scales before rendering the

Re: [PATCH v3 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros

On Sat, Apr 26, 2025 at 2:03 AM Daniel Henrique Barboza wrote: > > This change is motivated by a future change w.r.t CSRs management. We > want to handle them the same way as KVM extensions, i.e. a static array > with KVMCPUConfig objs that will be read/write during init and so on. > But to do tha

Re: [PATCH v4 2/8] vnc: initialize gst during argument processing

Hi On Mon, Apr 28, 2025 at 12:04 PM Dietmar Maurer wrote: > > So that we can set --gst- options on the qemu command line. > > Signed-off-by: Dietmar Maurer This breaks the build, because gstreamer may not be linked. Maybe another reason to drop the gst_init(argc, argv) and do it in VNC module

Re: [PATCH v3 3/3] hw/arm: Integrate Aspeed OTP memory into AST10x0 and AST2600 SoCs

On 4/28/25 13:00, Cédric Le Goater wrote: Hello, I understand that using a machine option (e.g., -M ast2600-evb,otpmem=xxx) to specify the OTP memory drive is similar to the modeling used for flash devices in the Q35 machine. However, in the real ASPEED hardware, the OTP memory is physically pa

Re: [PATCH v4 8/8] h264: stop gstreamer pipeline before destroying, cleanup on exit

Hi On Mon, Apr 28, 2025 at 12:06 PM Dietmar Maurer wrote: > > Some encoders can hang indefinitely (i.e. nvh264enc) if > the pipeline is not stopped before it is destroyed > (Observed on Debian bookworm). > > Signed-off-by: Dietmar Maurer In file included from /home/elmarco/src/qemu/include/ui/c

Re: [PATCH v3 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro

On Sat, Apr 26, 2025 at 2:04 AM Daniel Henrique Barboza wrote: > > We need the reg_id_ulong() helper to be a macro to be able to create a > static array of KVMCPUConfig that will hold CSR information. > > Despite the amount of changes all of them are tedious/trivial: > > - replace instances of "kv

Re: [PATCH 07/14] vfio: specify VFIO_DMA_UNMAP_FLAG_ALL to callback

On 4/24/25 21:35, John Levon wrote: On Thu, Apr 24, 2025 at 07:16:52PM +0200, Cédric Le Goater wrote: Having said that I'm OK with going back to just a simple boolean if you'd really prefer. yes. VFIO_DMA_UNMAP_FLAG_ALL is a kernel interface and we don't need more than one flag today. OK

Re: [PATCH 03/11] vfio/igd: Detect IGD device by OpRegion

On 4/23/25 14:54, Corvin Köhne wrote: > On Tue, 2025-04-22 at 00:31 +0800, Tomita Moeko wrote: >> CAUTION: External Email!! >> There is currently no straightforward way to distinguish if a Intel >> graphics device is IGD or discrete GPU. However, only IGD devices expose >> OpRegion. Use the presen

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

On Mon, Apr 28, 2025 at 03:37:26PM +0200, Radim Krčmář wrote: > 2025-04-28T14:08:59+02:00, Andrew Jones : > > On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote: > >> 2025-04-28T09:00:55+02:00, Andrew Jones : > >> > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: > >> >> This p

Re: [PATCH v8 30/55] kvm: Check KVM_CAP_MAX_VCPUS at vm level

On Tue, Apr 01, 2025 at 09:01:40AM -0400, Xiaoyao Li wrote: > Date: Tue, 1 Apr 2025 09:01:40 -0400 > From: Xiaoyao Li > Subject: [PATCH v8 30/55] kvm: Check KVM_CAP_MAX_VCPUS at vm level > X-Mailer: git-send-email 2.34.1 > > KVM with TDX support starts to report different KVM_CAP_MAX_VCPUS per >

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 4/28/25 4:07 AM, Markus Armbruster wrote: Peter Krempa writes: So what should libvirt do once multiple targets are supported? How do we query CPUs for each of the supported targets? It's kind of a similar question we have to solve now with QEMU code. What happens when a symbol is duplic

Re: [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc

On 4/9/25 4:43 PM, Cornelia Huck wrote: > Generated against Linux 6.14-rc1. > > Reviewed-by: Sebastian Ott > Signed-off-by: Cornelia Huck Reviewed-by: Eric Auger Eric > --- > target/arm/cpu-sysregs.h.inc | 43 +--- > 1 file changed, 30 insertions(+), 13 delet

Re: [PATCH for-10.1 v5 00/13] arm: rework id register storage

Hi Connie, On 4/9/25 4:42 PM, Cornelia Huck wrote: > Just a quick respin to fix a missed conversion in hvf.c. > > Also available at > https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v5 I reviewed it again - I can't send any R-b through since I am co-author ;-) - and I spotted fe

?????? Whether the qemu mps2-an385 model support getchar?

But I just write getchar() in the demo's main_blinky() function without any other order, I just keep the original UART address configuration in demo and annotation other codes, however, the error still occurred. The program can enter the main_blinky() successfully but can't excute getchar().  

Re: [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class

On 28/4/25 14:17, Paolo Bonzini wrote: On Mon, Apr 28, 2025 at 1:50 PM Daniel Henrique Barboza wrote: On 4/28/25 4:34 AM, Paolo Bonzini wrote: Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure

Re: [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 into the idregs array

On 4/9/25 4:42 PM, Cornelia Huck wrote: > From: Eric Auger > > Reviewed-by: Richard Henderson > Reviewed-by: Sebastian Ott > Signed-off-by: Eric Auger > Signed-off-by: Cornelia Huck > --- > target/arm/cpu-features.h | 40 - > target/arm/cpu.c | 29 +

Re: [PATCH 12/14] vfio: add region info cache

On 4/9/25 15:48, John Levon wrote: Instead of requesting region information on demand with VFIO_DEVICE_GET_REGION_INFO, maintain a cache: this will become necessary for performance for vfio-user, where this call becomes a message over the control socket, so is of higher overhead than the traditio

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 4/28/25 1:37 AM, Daniel P. Berrangé wrote: On Fri, Apr 25, 2025 at 01:39:49PM -0700, Pierrick Bouvier wrote: On 4/25/25 00:35, Daniel P. Berrangé wrote: On Thu, Apr 24, 2025 at 11:33:47AM -0700, Pierrick Bouvier wrote: Feedback The goal of this series is to be spark a conversation

Re: [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 into the idregs array

On 4/9/25 4:42 PM, Cornelia Huck wrote: > From: Eric Auger > > Reviewed-by: Richard Henderson > Reviewed-by: Sebastian Ott > Signed-off-by: Eric Auger > Signed-off-by: Cornelia Huck > --- > target/arm/cpu-features.h | 16 > target/arm/cpu.c | 15 +-- >

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 4/28/25 3:25 AM, Peter Krempa wrote: On Fri, Apr 25, 2025 at 14:07:34 -0700, Pierrick Bouvier wrote: On 4/25/25 08:38, Markus Armbruster wrote: Pierrick Bouvier writes: Note: This RFC was posted to trigger a discussion around this topic, and it's not expected to merge it as it is. Contex

Re: [PATCH V1 0/6] fast qom tree get

On 4/28/2025 4:04 AM, Markus Armbruster wrote: Steven Sistare writes: On 4/9/2025 3:39 AM, Markus Armbruster wrote: Hi Steve, I apologize for the slow response. Steve Sistare writes: Using qom-list and qom-get to get all the nodes and property values in a QOM tree can take multiple second

Re: [PATCH 3/5] i386/kvm: Support event with select & umask format in KVM PMU filter

Zhao Liu writes: > On Mon, Apr 28, 2025 at 09:19:07AM +0200, Markus Armbruster wrote: >> Date: Mon, 28 Apr 2025 09:19:07 +0200 >> From: Markus Armbruster >> Subject: Re: [PATCH 3/5] i386/kvm: Support event with select & umask format >> in KVM PMU filter >> >> Zhao Liu writes: >> >> > Hi Mark

Re: [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 into the idregs array

On 4/9/25 4:42 PM, Cornelia Huck wrote: > From: Eric Auger > > Reviewed-by: Richard Henderson > Reviewed-by: Sebastian Ott > Signed-off-by: Eric Auger > Signed-off-by: Cornelia Huck > --- > hw/intc/armv7m_nvic.c | 12 ++-- > target/arm/cpu-features.h | 36 +- > target/arm/cpu

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 4/25/25 11:21 PM, Markus Armbruster wrote: Trouble is some uses of the second kind are in QAPI conditionals. I can see three options: (1) Drop these conditionals. (2) Replace them by run-time checks. (3) Have target-specific QAPI-generated code for multiple targets coexist in the sing

Re: [PATCH v5 8/8] hw/hyperv/hyperv: common compilation unit

On 4/24/25 16:28, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- hw/hyperv/hyperv.c| 3 ++- hw/hyperv/meson.build | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v5 7/8] include/system: make functions accessible from common code

On 4/24/25 16:28, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- include/system/kvm.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~

[PATCH 6/9] vfio/igd: Enable OpRegion by default

As the presence of OpRegion is used to detect IGD device now, and guest driver usually depends on OpRegion to work. Enable OpRegion on IGD devices by default for out-of-the-box passthrough experience (except pre-boot display output), especially for libvirt users. Example of IGD passthrough with li

[PATCH 8/9] vfio/igd: Only emulate GGC register when x-igd-gms is set

x-igd-gms is used for overriding DSM region size in GGC register in both config space and MMIO BAR0, by default host value is used. There is no need to emulate it in default case. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 49 ++--- 1 file changed

[PATCH 3/9] vfio/igd: Detect IGD device by OpRegion

There is currently no straightforward way to distinguish if a Intel graphics device is IGD or discrete GPU. However, only IGD devices have OpRegion. Use the presence of VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION to identify IGD devices. Still, OpRegion on hotplugged IGD device is not supported. Signed

[PATCH 9/9] vfio/igd: Remove generation limitation for IGD passthrough

Starting from Intel Core Ultra Series (Meteor Lake), Data Stolen Memory has became a part of LMEMBAR (MMIO BAR2) [1][2], meaning that BDSM and GGC register quirks are no longer needed on these platforms. To support Meteor/Arrow/Lunar Lake and future IGD devices, remove the generation limitation in

Re: [PULL 00/50] vfio queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 0/4] Block layer patches

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 000/159] tcg patch queue

Hi Richard, Please take a look at this CI failure: https://gitlab.com/qemu-project/qemu/-/jobs/9849960705 It might be related to this pull request, so I have dropped it from the staging tree for now. Thanks, Stefan signature.asc Description: PGP signature

Re: [PULL 00/58] Misc single binary patches for 2025-04-25

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v3 02/13] accel/tcg: Use vaddr in user/page-protection.h

On 24/04/25, Philippe Mathieu-Daudé wrote: > From: Richard Henderson > > Signed-off-by: Richard Henderson > Message-ID: <20250424011918.599958-14-richard.hender...@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé > --- > include/user/page-protection.h | 17 +--- > accel/tcg/user-exe

Re: [PATCH v3 09/13] accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'

On 24/04/25, Philippe Mathieu-Daudé wrote: > Most files including "exec/helper-proto.h" call GETPC(). > Include it there (in the common part) instead of the > unspecific "exec/exec-all.h" header. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/exec/exec-all.h| 1 - > includ

Re: [PATCH v3 05/13] include/exec: Move tb_invalidate_phys_range to translation-block.h

On 24/04/25, Philippe Mathieu-Daudé wrote: > From: Richard Henderson > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > Message-ID: <20250424011918.599958-15-richard.hender...@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé > --- > include/exec/exec-all.h

Re: [PATCH 1/3] aio-posix: treat io_uring setup failure as fatal

On Fri, Apr 25, 2025 at 05:51:43PM +0200, Kevin Wolf wrote: > Am 01.04.2025 um 16:27 hat Stefan Hajnoczi geschrieben: > > In the early days of io_uring it was possible for io_uring_setup(2) to > > fail due to exhausting RLIMIT_MEMLOCK. QEMU's solution was to fall back > > to epoll(7) or ppoll(2) wh

Re: [PATCH v3 06/13] accel/tcg: Compile tb-maint.c twice

On 24/04/25, Philippe Mathieu-Daudé wrote: > From: Richard Henderson > > Signed-off-by: Richard Henderson > Message-ID: <20250424011918.599958-16-richard.hender...@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé > --- > accel/tcg/tb-hash.h | 3 +-- > accel/tcg/tb-maint.c | 2 -- > accel

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On Fri, Apr 25, 2025 at 17:38:44 +0200, Markus Armbruster via Devel wrote: > Pierrick Bouvier writes: [...] > To be precise: conditionals that use macros restricted to > target-specific code, i.e. the ones poisoned by exec/poison.h. Let's > call them target-specific QAPI conditionals. > > The

[PATCH v2] target/riscv/kvm: add satp mode for host cpu

This patch adds host satp mode while kvm/host cpu satp mode is not set. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 Signed-off-by: Meng Zhuo --- target/riscv/cpu.c | 3 +-- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 20 +++- 3 files

RE: [PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and creating address spaces

Hi Clement, >-Original Message- >From: CLEMENT MATHIEU--DRIF >Subject: [PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and >creating address spaces > >vtd_find_add_as can be called by multiple threads which leads to a race >condition on address space creation. The IOMMU loc

Re: [PATCH v6 0/2] tests/functional: add memlock tests

On 4/17/25 16:40, Alexandr Moshkov wrote: Add new tests to check the correctness of the `-overcommit memlock` option (possible values: off, on, on-fault) by using `/proc/{qemu_pid}/smaps` file to check in Size, Rss and Locked fields of anonymous segments: * if `memlock=off`, then Locked = 0 on e

Re: [RFC PATCH] target/ppc: Inline most of dcbz helper

On Mon, 28 Apr 2025, BALATON Zoltan wrote: On Mon, 28 Apr 2025, BALATON Zoltan wrote: On Thu, 24 Apr 2025, BALATON Zoltan wrote: The test case I've used came out of a discussion about very slow access to VRAM of a graphics card passed through with vfio the reason for which is still not clear bu

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

2025-04-28T14:08:59+02:00, Andrew Jones : > On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote: >> 2025-04-28T09:00:55+02:00, Andrew Jones : >> > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: >> >> This patch adds host satp mode while kvm/host cpu satp mode is not >> >> set.

Re: [PATCH] target/riscv: add satp mode for kvm host cpu

2025-04-28T09:00:55+02:00, Andrew Jones : > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote: >> This patch adds host satp mode while kvm/host cpu satp mode is not >> set. > > Huh, the KVM side[1] was written for this purpose, but it appears we never > got a QEMU side merged. > > [1] commi

Re: [PATCH v4 1/4] hw/s390x: add SCLP event type CPI

On Thu, 2025-04-10 at 17:09 +0200, Shalini Chellathurai Saroja wrote: > Implement the Service-Call Logical Processor (SCLP) event > type Control-Program Identification (CPI) in QEMU. This > event is used to send CPI identifiers from the guest to the > host. The CPI identifiers are: system type, sys

Re: [RFC PATCH] target/ppc: Inline most of dcbz helper

On 4/28/25 06:26, BALATON Zoltan wrote: I have tried profiling the dst in real card vfio vram with dcbz case (with 100 iterations instead of 1 in above tests) but I'm not sure I understand the results. vperm and dcbz show up but not too high. Can somebody explain what is happening here and w

[qemu-web PATCH] _posts: fix two typos on the 10.0 release announcement

We already had EL2 timers, the new ones where for secure mode. Also fix a transposition on s390x. Signed-off-by: Alex Bennée --- _posts/2025-04-23-qemu-10-0-0.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/_posts/2025-04-23-qemu-10-0-0.md b/_posts/2025-04-23-qemu-10-0

Re: [PATCH 2/5] i386/kvm: Support basic KVM PMU filter

On Mon, Apr 28, 2025 at 08:12:09AM +0200, Markus Armbruster wrote: > Date: Mon, 28 Apr 2025 08:12:09 +0200 > From: Markus Armbruster > Subject: Re: [PATCH 2/5] i386/kvm: Support basic KVM PMU filter > > Zhao Liu writes: > > > ... > > > >> > diff --git a/qemu-options.hx b/qemu-options.hx > >> >

Re: [PATCH 6/9] MAINTAINERS: add myself to virtio-gpu for Odd Fixes

On 28/04/2025 14.59, Alex Bennée wrote: Seeing as I've taken a few patches to here now I might as well put myself forward to maintain virtio-gpu. I've marked it as Odd Fixes as it's not my core focus. If someone with more GPU experience comes forward we can always update again. Signed-off-by: Al

Re: [PATCH v11 04/10] virtio-gpu: Support asynchronous fencing

liucong2...@phytium.com.cn writes: > I user Phytium D3000 8 Core, and I am not sure if it has a broken PCI. > > https://www.cpubenchmark.net/cpu.php?cpu=ARM+Phytium+D3000+8+Core+2500+MHz Ahh - looks totally unrelated to the Altera platform so hopefully that isn't an issue. Apparently a lot of the

Re: [PULL 4/4] qemu-img: improve queue depth validation in img_bench

25.04.2025 20:52, Kevin Wolf wrote: From: Denis Rastyogin This error was discovered by fuzzing qemu-img. Currently, running `qemu-img bench -d 0` in img_bench is allowed, which is a pointless operation and causes qemu-img to hang. Signed-off-by: Denis Rastyogin Message-ID: <20250327162423.25

Re: [PULL 4/4] qemu-img: improve queue depth validation in img_bench

28.04.2025 16:54, Michael Tokarev пишет: 25.04.2025 20:52, Kevin Wolf wrote: From: Denis Rastyogin This error was discovered by fuzzing qemu-img. Currently, running `qemu-img bench -d 0` in img_bench is allowed, which is a pointless operation and causes qemu-img to hang. Signed-off-by: Denis

Re: [PATCH 1/9] tests/docker: expose $HOME/.cache as docker volume

On 28/04/2025 14.59, Alex Bennée wrote: If you want to run functional tests we should share .cache so we don't force containers to continually re-download images. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/docker/Mak

Re: [PATCH 2/9] gitlab: disable debug info on CI builds

On 28/04/2025 14.59, Alex Bennée wrote: Our default build enables debug info which adds hugely to the size of the builds as well as the size of cached objects. Disable debug info across the board to save space and reduce pressure on the CI system. We still have a number of builds which explicitly

Re: [PATCH v4 06/10] hw/arm/aspeed: Add support for loading vbootrom image via "-bios"

On 28/4/25 09:54, Jamin Lin wrote: Hi Cedric, Subject: Re: [PATCH v4 06/10] hw/arm/aspeed: Add support for loading vbootrom image via "-bios" Hello Jamin, + Phil. On 4/23/25 09:02, Jamin Lin wrote: Hi Cedric, Cc: Troy Lee ; nabiheste...@google.com Subject: Re: [PATCH v4 06/10] hw/arm/aspe

Re: [PATCH 07/10] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state

On 4/28/25 1:10 PM, Richard Henderson wrote: diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..8dbe79ea7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,8 +18,13 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" -vo

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 4/28/25 12:54 PM, Stefan Hajnoczi wrote: Sure. Maybe there is a misunderstanding, but at this point, we are not trying to invent anything new. We are just looking for a way to build QAPI generated code only once, so it's possible to link together object files coming from two different targets

Re: [PATCH v7 0/6] Report vfio-ap configuration changes

On 4/25/25 07:23, Rorie Reyes wrote: Changelog: v7: - Dropped initial commit for linux-header file vfio.h since I created two new commits to address the changes made in v6 - Moved patches 6 and 7 to the beginning of the series after dropping the first patch - Because I dropped the initial c

Re: [PATCH 01/10] accel/tcg: Generalize fake_user_interrupt test

On 4/28/25 1:10 PM, Richard Henderson wrote: Test for the hook being present instead of ifdef TARGET_I386. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Pierrick Bouvier

Re: [PATCH 07/10] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state

On 4/28/25 15:00, Pierrick Bouvier wrote: On 4/28/25 1:10 PM, Richard Henderson wrote: diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..8dbe79ea7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,8 +18,13 @@   #include "exe

Re: [PATCH 07/10] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state

On 4/28/25 3:07 PM, Richard Henderson wrote: On 4/28/25 15:00, Pierrick Bouvier wrote: On 4/28/25 1:10 PM, Richard Henderson wrote: diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..8dbe79ea7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tc

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