On 4/4/25 10:56, Philippe Mathieu-Daudé wrote:
On 4/4/25 18:51, Pierrick Bouvier wrote:
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-all.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-all.c
Hi Pierrick,
On 4/4/25 19:10, Pierrick Bouvier wrote:
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
system/vl.c | 24
1 file changed, 24 insertions(+)
diff --git a/system/vl.c b/system/vl.c
index d8a0fe713c9..554f5f2a467 1
On 4/4/25 18:48, Pierrick Bouvier wrote:
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
The temptation is good, but please do not touch any target code at this
On 4/4/25 11:01, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 4/4/25 19:10, Pierrick Bouvier wrote:
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
system/vl.c | 24
1 file changed, 24 insertions(+)
diff --git a/system/v
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-bit
DRAM address space. To support future AST2700 updates, a new "digest_addr"
variable is introduced with a 64-bit data type.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 4 +++-
1 file changed, 3 insertions(+), 1
In this series we replace the TARGET_SUPPORTS_MTTCG (Makefile)
definition by a 'mttcg_supported' field in TCGCPUOps.
Based-on: <20250321125737.72839-1-phi...@linaro.org>
Philippe Mathieu-Daudé (4):
target/riscv: Restrict RV128 MTTCG check on system emulation
tcg: Move qemu_tcg_mttcg_enabled()
The PL011 device's C implementation exposes its PL011State struct to
users of the device, and one common usage pattern is to embed that
struct into the user's own state struct. (The internals of the
struct are technically visible to the C user of the device, but in
practice are treated as implemen
On 25/03/31 01:37PM, Philippe Mathieu-Daudé wrote:
> On 30/3/25 23:10, Aditya Gupta wrote:
> > <...snip...>
> >
> Reviewed-by: Philippe Mathieu-Daudé
Thanks for the tag, Philippe !
I will be posting a v5 with this patch split into 2 as suggested by
Cedric (one introducing the POWERPC_DEF_SVR_DEP
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
While this change is correct, this is not strictly needed.
With the current approach, using a set of common files per architecture,
we can rely on this include to be present, and it d
On Fri, 4 Apr 2025, Christian Schoenebeck wrote:
On Monday, March 31, 2025 3:05:24 PM CEST BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Christian Schoenebeck wrote:
On Sunday, March 16, 2025 1:20:46 AM CET BALATON Zoltan wrote:
Quoting Volker Rümelin: "try-poll=on tells the ALSA backend to try t
Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/tcg/insn-start-words.h | 4
include/tcg/tcg-op.h | 2 +-
target/alpha/cpu-param.h | 2 ++
targ
On Fri, Mar 21, 2025 at 11:56 AM Akihiko Odaki wrote:
>
> virtio-net uses the max_tx_vq field of struct virtio_net_rss_config to
> determine the number of queue pairs and emits an error message saying
> "Can't get queue_pairs". However, the field tells only about tx.
>
> Examine the indirection ta
On 2025-04-02 07:58, Thomas Huth wrote:
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification data to the QEMU Object
Model (QOM), along with the timestamp in which the data was received.
Example:
virsh # qemu-monitor-command vm --pretty '{
"execute": "qom-g
Signed-off-by: Markus Armbruster
---
docs/sphinx/qmp_lexer.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/sphinx/qmp_lexer.py b/docs/sphinx/qmp_lexer.py
index 1bd1b81b70..7b3b808d12 100644
--- a/docs/sphinx/qmp_lexer.py
+++ b/docs/sphinx/qmp_lexer.py
@@ -24,7 +24,7 @@
On 23/3/25 22:35, Philippe Mathieu-Daudé wrote:
On 23/3/25 18:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index e4011004b4..538fcbc215 100644
-
Consistently use two spaces to separate sentences.
Put "::" on a line of its own when it's preceded by whitespace.
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/docs/devel/qapi-c
On 4/4/25 10:12, Pierrick Bouvier wrote:
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
Hi,
At this point this series is mostly a draft for Pierrick.
After introducing the generic TargetInfo API [*], we implement
the ARM variants, then use the API to remove target-specific code,
allowing to ev
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 dele
On Tue Apr 1, 2025 at 5:40 AM AEST, Richard Henderson wrote:
> On 3/31/25 10:54, Nicholas Piggin wrote:
>> I've been struggling with these couple of performance issues with
>> TB coherency. I almost thought deferring flush to icbi would be
>> workable, buta note in the docs says that exceptions req
On Thu, Mar 20, 2025 at 11:48 PM Dragos Tatulea wrote:
>
> Hi Lei,
>
> On 03/20, Lei Yang wrote:
> > Hi Dragos, Si-Wei
> >
> > 1. I applied [0] [1] [2] to the downstream kernel then tested
> > hotplug/unplug, this bug still exists.
> >
> > [0] 35025963326e ("vdpa/mlx5: Fix suboptimal range on iot
On 3/21/25 10:26, Jamin Lin wrote:
The memory size was previously hardcoded to 0x1000 (4K). However, the actual
memory size of the HACE controller varies across different models:
1. AST2400/AST2500: 0x1000 (4K)
2. AST2600/AST1030: 0x1 (64K)
3. AST2700: 0x100 (256 bytes)
To address this, a ne
On Sun, 23 Mar 2025, Richard Henderson wrote:
On 3/23/25 15:13, BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Philippe Mathieu-Daudé wrote:
On 23/3/25 20:07, Richard Henderson wrote:
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 28fbbb8d3c1..ed79cc1a6b7 100644
--- a/target/ppc/
GIC ITS is checked for the MADT and IORT tables.
Factor the checks out to the its_enabled() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-buil
On 2/4/25 08:43, Gustavo Romero wrote:
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
GIC ITS is checked for the MADT and IORT tables.
Factor the checks out to the its_enabled() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c | 12 +---
1 file c
On Tue, Mar 25, 2025 at 05:06:48PM +0100, Hanna Czenczek wrote:
> Pull setting up and tearing down the AIO context handlers into two
> dedicated functions.
>
> Signed-off-by: Hanna Czenczek
> ---
> block/export/fuse.c | 32
> 1 file changed, 16 insertions(+), 16
Currently, if the program encounters an unsupported algorithm, it does not set
the HASH_IRQ bit in the status register and send an interrupt to indicate
command completion. As a result, the FW gets stuck waiting for a completion
signal from the HACE module.
Additionally, in do_hash_operation, if a
On Tue, Apr 01, 2025 at 09:01:19AM -0400, Xiaoyao Li wrote:
> Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
> EPT violation conversion to #VE on guest TD access of PENDING pages.
>
> Some guest OS (e.g., Linux TD guest) may require this bit as 1.
> Otherwise refuse to b
> -Original Message-
> From: Brian Cain
> Sent: Saturday, March 1, 2025 11:21 AM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsimp
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
default_mttcg_enabled() method content).
Instead of
On 2025/03/21 19:44, Yuri Benditovich wrote:
On Fri, Mar 21, 2025 at 11:56 AM Akihiko Odaki wrote:
virtio-net uses the max_tx_vq field of struct virtio_net_rss_config to
determine the number of queue pairs and emits an error message saying
"Can't get queue_pairs". However, the field tells o
On 2/19/25 02:03, Daniel P. Berrangé wrote:
+ cleanup:
+free(buf);
+
+if (outf &&
+fclose(outf) != 0)
+ret = EXIT_FAILURE;
+if (inf &&
+fclose(inf) != 0)
+ret = EXIT_FAILURE;
+return ret;
Modulo the lack of braces here, the patch looks fine.
r~
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 32
1 file changed, 16 insertions(+), 16 deletio
On Tue, Mar 04, 2025 at 06:33:40PM +, Daniel P. Berrangé wrote:
> There are two race conditions in the recently added virtio balloon
> test
>
> * The /dev/vda device node is not ready
> * The virtio-balloon driver has not issued the first stats refresh
>
> To fix the former, monitor dmesg f
Actually block job is not completed without the final flush. It's
rather unexpected to have broken target when job was successfully
completed long ago and now we fail to flush or process just
crashed/killed.
Mirror job already has mirror_flush() for this. So, it's OK.
Do this for stream, commit a
From: Suravee Suthikulpanit
Currently, the QEMU-emulated AMD IOMMU device use PCI vendor id 0x1022
(AMD) with device id zero (undefined). Eventhough this does not cause any
functional issue for AMD IOMMU driver since it normally uses information
in the ACPI IVRS table to probe and initialize the
On Thu, Apr 03, 2025 at 07:13:30PM +0200, Cédric Le Goater wrote:
> On 2/19/25 15:48, John Levon wrote:
> > From: Jagannathan Raman
> >
> > Split out code specific to the kernel-side vfio implementation from the
> > VFIOPCIDevice class into a VFIOKernelPCIDevice. The forthcoming
> > VFIOUserPCID
On Wed, Apr 02, 2025 at 10:52:38PM +0800, Xiaoyao Li wrote:
> On 4/2/2025 7:00 PM, Daniel P. Berrangé wrote:
> > On Tue, Apr 01, 2025 at 09:01:15AM -0400, Xiaoyao Li wrote:
> > > KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
> > > IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabi
On Tue, 2025-04-01 at 01:04 +0200, Philippe Mathieu-Daudé wrote:
> All MemoryRegionOps::read/write() handlers switch over a 32-bit
> aligned value, because converted using TO_REG(), which is defined
> as:
>
> #define TO_REG(offset) ((offset) >> 2)
>
> So all implementations are 32-bit.
> Set mi
Hi,
I tried to gather all the hw/arm/-related patches for
the GitLab issues tagged for 10.0.
First, trivial ones fixing / disabling broken tests;
then disable the VMapple machine (not sure about it);
finally fix ACPI tables for '-M its=off' CLI option.
While polishing the series, I noticed MST m
I saw that `Bernhard Beschow` is working on the same thing. So, please feel
free to close my pull request. Thank you :)
---
Saman Dehghan
Replying to qemu-devel@nongnu.org on March 31, 2025, 7:26 PM
From: sa...@enumclass.cc
To: qemu-devel@nongnu.org
CC: stefa...@redhat.com, qemu-r...@
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3686bbc9380..30238e9a223 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7481,6 +7481,7 @@ sta
Hi, Richard,
On Sat, Mar 29, 2025 at 1:55 AM Richard Henderson
wrote:
>
> Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing
> the system page size because of what the Loongson kernel "prefers"
> is flawed.
>
> In the Loongson-2E manual, section 5.5, it is clear that the cpu
> suppor
Hi,
The KVM/QEMU community call is at:
https://meet.jit.si/kvmcallmeeting
@
01/04/2025 14:00 UTC
Are there any agenda items for the sync-up?
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Thu, 3 Apr 2025 at 18:37, Fabiano Rosas wrote:
> The code assumes some understanding of the multifd sync in general. It
> doesn't help that we don't have a high level documentation for that
> (yet). If you think the comments at the MultiFDSyncReq are not enough,
> feel free to propose a separat
From: Steven Lee
Updated the IRQ handler mask check to AND with select variable.
This ensures that the interrupt service routine is correctly triggered
for the interrupts within the same irq group.
For example, both `eth0` and the debug UART are handled in `GICINT132`.
Without this fix, the debu
From: Zhu Yangyang
Calling qmp_block_resize() will be blocked for a long time on
bdrv_drained_begin()
when a network disk is configured and the network failure is just about
to occur.
Therefore, we add a timeout parameter for qmp_block_resize() to control its
execution duration.
The default va
On 18/03/2025 09:54, Cédric Le Goater wrote:
> Rename these routines :
>
> vfio_devices_all_device_dirty_tracking_started ->
> vfio_dirty_tracking_devices_is_started_all
> vfio_devices_all_dirty_tracking_started->
> vfio_dirty_tracking_devices_is_started
> vfio_devices_all_device_d
On Fri, 21 Mar 2025 at 15:49, Cédric Le Goater wrote:
> So you mean open coding :
> if (migration_is_running()) {
> migration_file_set_error(ret, errp);
> }
> ?
* Yes.
> Yes. I think it is a good idea to limit proliferation of this wrapper.
> Ideally, we wouldn't need to use m
On Tue, Apr 01, 2025 at 09:01:21AM -0400, Xiaoyao Li wrote:
> For QEMU VMs,
> - PKS is configured via CPUID_7_0_ECX_PKS, e.g., -cpu xxx,+pks and
> - PMU is configured by x86cpu->enable_pmu, e.g., -cpu xxx,pmu=on
>
> While the bit 30 (PKS) and bit 63 (PERFMON) of TD's attributes are also
> use
PSSCR aliases to two SPR numbers, one HV only and one where some fields
are available to supervisor. Supervisor also has some restrictions on
where it can execute 'stop' instruction, based on PSSCR field values.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 9 -
targ
On 3/21/25 10:26, Jamin Lin wrote:
Introduced "trace_aspeed_hace_addr", "trace_aspeed_hace_sg",
"trace_aspeed_hace_read", and "trace_aspeed_hace_write" trace events.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 8
hw/misc/trace-events | 6 ++
2 files changed, 14 insert
On 2/4/25 16:25, Philippe Mathieu-Daudé wrote:
On 23/3/25 19:08, Richard Henderson wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Multi-threaded TCG only concerns system emulation.
That's not really true. User emulation simply has no option to
run in a single-threaded context.
I rea
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
---
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c| 2 +-
3 files changed, 5 inserti
On 3/23/25 15:13, BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Philippe Mathieu-Daudé wrote:
On 23/3/25 20:07, Richard Henderson wrote:
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 28fbbb8d3c1..ed79cc1a6b7 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7490
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On Tue, 18 Mar 2025 at 13:00, Aleksandar Rakic
wrote:
> The soft(-float) requirement means that the program being loaded has no
> FPU dependency at all (i.e. it has no FPU instructions).
> https://elixir.bootlin.com/linux/v6.13.6/source/arch/mips/kernel/elf.c#L34
Yes, I know. But the kernel loade
On Wed, Apr 02, 2025 at 11:50:26 +0100, Daniel P. Berrangé wrote:
> CC libvirt / Jiri, for confirmation about whether the CPUID restrictions
> listed below will have any possible impact on libvirt CPUID handling...
..
> > +Feature check
> > +~
> > +
> > +QEMU checks if the final (CPU) f
> > > +// Some C users of this device embed its state struct into their own
> > > +// structs, so the size of the Rust version must not be any larger
> > > +// than the size of the C one. If this assert triggers you need to
> > > +// expand the padding_for_rust[] array in the C PL011State struct.
>
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-3-phi...@linaro.org>
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b84c6afb327..0887c103e4f 100644
--- a/hw/block/m25p80.c
+++
Prasad Pandit writes:
> From: Prasad Pandit
>
> The various logical migration channels don't have a
> standardized way of advertising themselves and their
> connections may be seen out of order by the migration
> destination. When a new connection arrives, the incoming
> migration currently make
On 3/19/25 1:00 PM, Eric Auger wrote:
Hi,
On 3/19/25 1:23 AM, Jason Gunthorpe wrote:
On Tue, Mar 18, 2025 at 05:22:51PM -0400, Donald Dutile wrote:
I agree with Eric that 'accel' isn't needed -- this should be
ascertained from the pSMMU that a physical device is attached to.
I seem to re
Actualize documentation and synchronize it for commands which actually
call the same functions internally.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 59 +---
qapi/job.json| 29 --
2 files changed, 61
For change, pause, resume, complete, dismiss and finalize actions
corresponding job- and block-job commands are almost equal. The
difference is in find_block_job_locked() vs find_job_locked()
functions. What's different?
1. find_block_job_locked() do check, is found job a block-job. This OK
whe
v2:
Update documentation: add patch 01
v1 was:
[PATCH] [for-10.1] qapi/block-core: derpecate some block-job- APIs
Supersedes: <20250401155730.103718-1-vsement...@yandex-team.ru>
Vladimir Sementsov-Ogievskiy (2):
qapi: synchronize jobs and block-jobs documentation
qapi/block-core: derpecate so
On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
To avoid including the huge "cpu.h" for a simple definition,
move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-param.h| 14 ++
target/arm/cpu.h | 14 --
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:28 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 3/26/2025 7:42 AM, 'Anton Johansson' wrote:
On 25/03/25, Brian Cain wrote:
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...@gmail.com; br
When the IOMMU is implemented as a PCI device, its BDF is created
locally in virt.c. However, the same BDF is also required in
virt-acpi-build.c to support ACPI. Therefore, make this information part
of the global RISCVVirtState structure so that it can be accessed
outside of virt.c as well.
Signe
Remove all uses of 32-bit temporaries in emit.c.inc. Remove uses
in translate.c outside the large multiplexed generator functions.
tmp3_i32 is not used anymore and can go away.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 43 +++
target/i386/tcg/emit.c.inc | 8
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smai
Hi,
We've been working with Panasonic to expand the testing of VirtIO across
a range of hypervisors and VMMs. We've tackled this with two approaches:
- simple unikernel to verify features and basic functions common
- rootfs images to exercise the whole device
The unikernel utilizes rcore-o
We only build ARM system emulators using little
endianness, so the MO_TE definition always expands to
MO_LE, and DEVICE_TARGET_ENDIAN to DEVICE_LITTLE_ENDIAN.
Replace the definitions by their expanded value, making
it closer to the Armv7-M Architecture Reference Manual
(ARM DDI 0403E) description:
Move all VFIODevice related routines of helpers.c into a new "device.c"
file.
Signed-off-by: Cédric Le Goater
---
hw/vfio/device.c | 331 +++
hw/vfio/helpers.c| 303 ---
hw/vfio/meson.build | 1 +
hw/vfio/trac
This hides the MemoryListener implementation and makes the code common
to both IOMMU backends, legacy and IOMMUFD.
Signed-off-by: Cédric Le Goater
---
hw/vfio/dirty-tracking.h | 4 ++--
hw/vfio/container.c | 11 +++
hw/vfio/dirty-tracking.c | 21 -
hw/vfio/iommu
Keep MTTCG initialization code out of tcg_init_machine().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-all.c | 50 +
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/
On 4/3/25 22:33, Farhan Ali wrote:
On 4/3/2025 11:05 AM, Alex Williamson wrote:
On Thu, 3 Apr 2025 10:33:52 -0700
Farhan Ali wrote:
On 4/3/2025 9:27 AM, Alex Williamson wrote:
On Thu, 3 Apr 2025 11:44:42 -0400
Stefan Hajnoczi wrote:
On Thu, Apr 03, 2025 at 09:47:26AM +0200, Niklas Schnell
Pull in recent TDX updates, which are not backwards compatible.
It's just to make this series runnable. It will be updated by script
scripts/update-linux-headers.sh
once TDX support is upstreamed in linux kernel
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 69 ++
On 20/03/2025 11:45, Avihai Horon wrote:
>
> On 20/03/2025 13:18, Joao Martins wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On 20/03/2025 11:13, Avihai Horon wrote:
>>> On 19/03/2025 14:21, Joao Martins wrote:
External email: Use caution opening links or attachm
Fabiano Rosas writes:
> Daniel P. Berrangé writes:
>
>> On Thu, Mar 27, 2025 at 11:39:31AM -0300, Fabiano Rosas wrote:
>>> It has always been possible to enable arbitrary migration capabilities
>>> and attempt to take a snapshot of the VM with the savevm/loadvm
>>> commands as well as their QMP
We do not set CONFIG_SEMIHOSTING in
configs/targets/xtensa*-linux-user.mak.
Do not raise SIGILL for user-only unconditionally.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/xte
On 4/4/25 20:20, Pierrick Bouvier wrote:
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
While this change is correct, this is not strictly needed.
With the current approach, using a set of common files per architecture,
we can re
On Wed, 19 Mar 2025 13:14:27 +0100
Christian Schoenebeck wrote:
> On Wednesday, March 19, 2025 11:08:58 AM CET Christian Schoenebeck wrote:
> > According to 'man 2 close' errors returned by close() should only be used
> > for either diagnostic purposes or for catching data loss due to a previous
On 3/19/25 00:21, Philippe Mathieu-Daudé wrote:
On 19/3/25 01:33, Pierrick Bouvier wrote:
On 3/18/25 14:32, Richard Henderson wrote:
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-of
Hi,
The soft(-float) requirement means that the program being loaded has no
FPU dependency at all (i.e. it has no FPU instructions).
https://elixir.bootlin.com/linux/v6.13.6/source/arch/mips/kernel/elf.c#L34
When -msoft-float is used, the processor does not use hardware
floating-point instruction
On Mär 18 2025, Daniel P. Berrangé wrote:
> Whereever practical, it is preferrable to check a discrete feature
> or behaviour in a functional way, rather than matching on "is it QEMU"
Do you know a way to detect support for CLONE_VFORK that isn't too
expensive?
--
Andreas Schwab, SUSE Labs, sch
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime access
to TCGCPUOps::guest_default_memory_order via CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/internal-target.h | 9 -
1 file c
+Paolo
On 4/4/25 20:23, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
Instead, we can simply make hvf_enabled present for common and target
s
+Paolo
On 4/4/25 20:25, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Hardware accelerators depends on the host, not the guest.
While this is true, no we can't unpoison those define.
They are applied per target, and not in config-host. So unpoisoining
them opens the
On 4/4/25 20:21, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target specific
"cpu.h" header.
Including cpu.h is n
On 4/4/25 20:28, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 32
1
Hi Kun,
On 3/3/25 23:55, Kun Qin wrote:
Hi Leif & Peter,
Thanks for the comments. I will address them in a v2 patch.
Please also Cc me in your v2 :)
Regards,
Phil.
Regards,
Kun
On Mon, Mar 3, 2025 at 12:44 PM Leif Lindholm
mailto:leif.lindh...@oss.qualcomm.com>>
wrote:
Doh! Add
On Tue, Apr 01, 2025 at 08:37:19AM +1000, Nicholas Piggin wrote:
> On Mon Mar 31, 2025 at 11:13 PM AEST, Corey Minyard wrote:
> > On Mon, Mar 31, 2025 at 10:57:22PM +1000, Nicholas Piggin wrote:
> >> If the dont-log flag is set in the 'timer use' field for the
> >> 'set watchdog' command, a watchdo
On 2/4/25 23:03, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3686bbc9380..30238e9a223 10064
On Mon, Mar 03, 2025 at 01:02:17PM -0500, yuanminghao wrote:
> > > Global used_memslots or used_shared_memslots is updated to 0 unexpectly
> >
> > it shouldn't be 0 in practice, as it comes from number of RAM regions VM
> > has.
> > It's likely a bug somewhere else.
> >
> > Please describe a way
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/s390x/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 1f75629ddc2..320ace67198 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -348,
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
> -Original Message-
> From: Sid Manning
> Sent: Thursday, March 20, 2025 3:26 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) ; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) ;
vfio_get_device_info() is a low level routine. Move it with the other
helpers.
Signed-off-by: Cédric Le Goater
---
hw/vfio/helpers.h | 1 +
include/hw/vfio/vfio-common.h | 1 -
hw/vfio/common.c | 24
hw/vfio/helpers.c | 24 +
On 3/19/25 00:03, Philippe Mathieu-Daudé wrote:
On 18/3/25 23:02, Pierrick Bouvier wrote:
On 3/18/25 11:50, Philippe Mathieu-Daudé wrote:
On 18/3/25 05:51, Pierrick Bouvier wrote:
This will affect zregs field for aarch32.
This field is used for MVE and SVE implementations. MVE implementation
i
On 3/20/2025 10:26 PM, Alejandro Jimenez wrote:
Hi Sairaj Kodilkar,
On 3/20/25 1:11 AM, Arun Kodilkar, Sairaj wrote:
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see
Table 8: V,
TV, and GV Fields in Device Table Entry), speci
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