Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/mips/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 47df563e123..269d3d69bd5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -554,6 +55
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/rx/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 723262f4b54..e14d9cbef93 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -208,6 +208,7 @@ sta
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/xtensa/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index ec6a0a8b662..51f9ee9e89a 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/sh4/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ce84bdf539a..df093988cb1 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -266,6 +266,7 @
Move riscv_cpu_mmu_index() to the TCG-specific file,
convert CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 6 --
target/riscv/tcg/tcg-cpu.c | 6 ++
2 files changed, 6 insertions(+),
All targets have been converted to TCGCPUOps::mmu_index(),
remove the now unused CPUClass::mmu_index().
Since this handler is now mandatory, add an assertion in
tcg_exec_realizefn().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/exec/cpu-mmu-index.h | 4 +---
Since commit f9ba56a03c2 ("user: Introduce 'user/guest-host.h' header")
cpu_untagged_addr() is only needed in "user/guest-host.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
in
Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not
include it:
- accel/tcg/cpu-exec.c
- target/arm/tcg/sve_helper.c
Include it there and remove it from "exec/exec-all.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
---
include/exec/e
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/hppa/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 0da8cdf41f5..51bff0c5d62 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -257,6 +25
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3686bbc9380..30238e9a223 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is supported via the
&first_cpu global.
Signed-off-
Keep MTTCG initialization code out of tcg_init_machine().
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-all.c | 50 +
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index ae3a137e87f.
Mechanical change using:
$ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \
$(git grep -l exec/cpu_ldst.h)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
---
bsd-user/qemu.h | 2 +-
include/{exec/
Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/tcg/insn-start-words.h | 4
include/tcg/tcg-op.h | 2 +-
target/alpha/cpu-param.h | 2 ++
targ
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
On 4/2/25 5:51 PM, Philippe Mathieu-Daudé wrote:
As Richard mentioned:
We should allow RV128 in user-mode at all until there's a
kernel abi for it.
By the context I suppose Richard said 'We shouldn't allow RV128 ...'.
If this was said in a gitlab issue or something it would be nice t
On Tue, 2025-04-01 at 13:58 +0200, Philippe Mathieu-Daudé wrote:
> On 1/4/25 13:43, David Woodhouse wrote:
> > On Tue, 2025-04-01 at 13:30 +0200, Philippe Mathieu-Daudé wrote:
> > > On 1/4/25 13:18, Philippe Mathieu-Daudé wrote:
> > > > Hi David,
> > > >
> > > > On 8/1/25 14:51, David Woodhouse wr
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
default_mttcg_enabled() method content).
In the tcg
Since commit f9ba56a03c2 ("user: Introduce 'user/guest-host.h' header")
cpu_untagged_addr() is only needed in "user/guest-host.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
in
Keep MTTCG initialization code out of tcg_init_machine().
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-all.c | 50 +
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 15d4e9232ae.
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is supported via the
current CPU class (CPU_RESOLVIN
m68k_set_irq_level() prototype doesn't use target-specific
types, move its declaration from target-specific "cpu.h"
to target-agnostic "cpu-qom.h". Doing so we can remove the
"cpu.h" header in m68k_irqc.c, making it target-agnostic,
which can be build as part of the system_ss[] source set.
Signed-
Hi Richard,
Here is my patch queue based on your tcg-next tree.
Missing review: 38, 41, 43 (all news)
Thanks,
Phil.
Since v1:
- Deferred warning change and updated desc (patches 40 & 42)
(skipping patches 1-37 because identical of v1:
https://lore.kernel.org/qemu-devel/20250402210328.52897-1-
On 3/21/25 11:15, Philippe Mathieu-Daudé wrote:
Since v1:
- Do not use tcg_ctx in tcg_req_mo (rth)
Hi,
In this series we replace the TCG_GUEST_DEFAULT_MO definition
from "cpu-param.h" by a 'guest_default_memory_order' field in
TCGCPUOps.
Since tcg_req_mo() now accesses tcg_ctx, this impact the
This patch addresses potential data races involving access to Job fields
in the test-bdrv-drain test.
Fixes: 7253220de4 ("test-bdrv-drain: Test drain vs. block jobs")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2900
Signed-off-by: Vitalii Mordan
---
include/qemu/job.h | 2
From: Richard Henderson
The number of bits set in PageMask must be even.
Fixes: d40b55bc1b86 ("target/mips: Fix PageMask with variable page size")
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250328175526.368121-3-richard.hender...@linaro.org>
Signed-off-
Hi Cedric,
> Subject: Re: [PATCH v1 00/22] Fix incorrect hash results on AST2700
>
> Hello Jamin,
>
> On 3/21/25 10:25, Jamin Lin wrote:
> > v1:
> > 1. Added support for 64-bit DMA in the HACE model
> > 2. Refactored the do_hash operation in the HACE model
> > 3. Fixed a crash caused by ou
On 2/19/25 15:48, John Levon wrote:
From: John Levon
The vfio-user container will later need to hook into these callbacks;
set up vfio to use them, and optionally pass them through to the
container.
Signed-off-by: John Levon
Looks ok. The future respin of this series will need to add routin
On Wed, Apr 02, 2025 at 11:26:11PM +0800, Xiaoyao Li wrote:
> Sorry for the late response.
>
> KVM part of TDX attestation support is submitting again. QEMU part will
> follow and we need to settle dowm this topic before QEMU patches submission.
>
> On 10/4/2024 2:08 AM, Daniel P. Berrangé wrote:
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 10.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-10.0.0-rc2.tar.xz
http://download.qem
On 26/03/2025 07:51, Cédric Le Goater wrote:
> vfio_container_query_dirty_bitmap() is only used in "container-base.c".
> Also, rename to vfio_container_vioc_query_dirty_bitmap() to reflect it
> is using the VFIO IOMMU backend device ->query_dirty_bitmap() handler.
>
> Signed-off-by: Cédric Le Goat
On Fri, Mar 14, 2025 at 2:15 AM Akihiko Odaki wrote:
>
> Based-on: <20250104-reuse-v18-0-c349eafd8...@daynix.com>
> ("[PATCH v18 00/14] hw/pci: SR-IOV related fixes and improvements")
>
> Introduction
>
>
> This series is based on the RFC series submitted by Yui Washizu[1].
> See also
On 4/2/25 04:26, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 18/3/25 22:31, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_ID
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification (CPI) device to QOM only when the virtual
machine supports CPI. CPI is supported from "s390-ccw-virtio-10.0" machine
and higher.
Signed-off-by: Shalini Chellathurai Saroja
---
hw/s390x/event-facility.c
On 3/21/25 10:26, Jamin Lin wrote:
Introduced SHA-384 test functions to verify hashing operations.
Extended support for scatter-gather (`_sg`) and accumulation (`_accum`) tests.
Updated test result vectors for SHA-384 validation.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed-hace-utils.h |
On 3/21/25 10:26, Jamin Lin wrote:
Currently, the hash data source and digest result buffer addresses are set to
32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and its
DRAM base address is also 64-bit.
To support AST2700, update the hash data source address and digest resu
On Tue, Apr 01, 2025 at 09:01:12AM -0400, Xiaoyao Li wrote:
> Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST,
> and will be used to create TDX VMs (TDs) by
>
> qemu -machine ...,confidential-guest-support=tdx0 \
>-object tdx-guest,id=tdx0
>
> It has one QAPI member '
On Tue, Apr 01, 2025 at 09:01:55AM -0400, Xiaoyao Li wrote:
> TDX architecture forcibly sets some CPUID bits for TD guest that VMM
> cannot disable it. They are fixed1 bits.
>
> Fixed1 bits are not covered by tdx_caps.cpuid (which only contians the
Typo s/contians/contains/
> directly configur
On 01.04.25 20:07, Vladimir Sementsov-Ogievskiy wrote:
For now we only log the vhost device error, when virtqueue is actually
stopped. Let's add a QAPI event, which makes possible:
- collect statistics of such errors
- make immediate actions: take core dumps or do some other debugging
- in
On Wed, Apr 02, 2025 at 03:52:28PM +0100, Mads Ynddal wrote:
> From: Mads Ynddal
>
> hvf_arch_set_traps is already called from a context of a specific
> CPUState, so we don't need to do a nested CPU_FOREACH.
>
> It also results in an error from hv_vcpu_set_sys_reg, as it may only be
> called fro
On 4/2/25 03:17, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 8/3/25 23:58, Richard Henderson wrote:
Some of these bits are actually common to all cpus; while the
reset have common reservations for target-specific usage.
While generic code cannot know what the target-specific usage is,
common c
On 2/4/25 22:00, Richard Henderson wrote:
On 3/21/25 11:15, Philippe Mathieu-Daudé wrote:
Since v1:
- Do not use tcg_ctx in tcg_req_mo (rth)
Hi,
In this series we replace the TCG_GUEST_DEFAULT_MO definition
from "cpu-param.h" by a 'guest_default_memory_order' field in
TCGCPUOps.
Since tcg_req
On 2/4/25 20:46, Richard Henderson wrote:
On 4/2/25 03:17, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 8/3/25 23:58, Richard Henderson wrote:
Some of these bits are actually common to all cpus; while the
reset have common reservations for target-specific usage.
While generic code cannot know
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