Re: [PATCH-for-10.0?] target/riscv: Do not expose rv128 CPU on user mode emulation

[Daniel Henrique Barboza]

On 4/2/25 5:51 PM, Philippe Mathieu-Daudé wrote:

As Richard mentioned:

   We should allow RV128 in user-mode at all until there's a
   kernel abi for it.

By the context I suppose Richard said 'We shouldn't allow RV128 ...'.

If this was said in a gitlab issue or something it would be nice to
add a link in the commit msg.

Remove the experimental 'x-rv128' CPU on user emulation
(since it is experimental, no deprecation period is required).

Reported-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/cpu.c         | 10 ++++------
  target/riscv/tcg/tcg-cpu.c |  5 +++--
  2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 430b02d2a58..ad534cee51f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
  #endif
  }

-#ifdef CONFIG_TCG

+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
  static void rv128_base_cpu_init(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
@@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj)

/* Set latest version of privileged specification */

      env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
-#endif
  }
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */

static void rv64i_bare_cpu_init(Object *obj)

  {
@@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  
rv64_veyron_v1_cpu_init),
      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
                                                   MXL_RV64, 
rv64_xiangshan_nanhu_cpu_init),
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, 
rv128_base_cpu_init),
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I,        MXL_RV64,  
rv64i_bare_cpu_init),
      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E,        MXL_RV64,  
rv64e_bare_cpu_init),
      DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64,  MXL_RV64,  
rva22u64_profile_cpu_init),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 19ab324cb2a..50e81b2e521 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1048,7 +1048,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
  static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
-    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);

if (!riscv_cpu_tcg_compatible(cpu)) {

          g_autofree char *name = riscv_cpu_get_name(cpu);
@@ -1057,6 +1056,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error 
**errp)
          return false;
      }

+#ifndef CONFIG_USER_ONLY

+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+
      if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
          /* Missing 128-bit aligned atomics */
          error_setg(errp,
@@ -1065,7 +1067,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error 
**errp)
          return false;
      }

-#ifndef CONFIG_USER_ONLY

      CPURISCVState *env = &cpu->env;

tcg_cflags_set(CPU(cs), CF_PCREL);