Windows has no native equivalent API, but it would be possible to
simulate it as illustrated here (BSD-3-Clause):
https://github.com/giampaolo/psutil/pull/1485
Reviewed-by: Daniel P. Berrangé
Tested-by: Dehan Meng
Reviewed-by: Yan Vugenfirer
Signed-off-by: Konstantin Kostiuk
---
qga/comman
Tested-by: Dehan Meng
Reviewed-by: Yan Vugenfirer
Signed-off-by: Konstantin Kostiuk
---
tests/unit/test-qga.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/tests/unit/test-qga.c b/tests/unit/test-qga.c
index 541b08a5e7..587e30c7e4 100644
--- a/tests/unit/test-qga.c
+++
v1 -> v2:
- Added comments about init_load_avg_counter
v1: https://patchew.org/QEMU/20250314113847.109460-1-kkost...@redhat.com/
Konstantin Kostiuk (2):
qga-win: implement a 'guest-get-load' command
qga: Add tests for guest-get-load command
qga/commands-win32.c | 148 +++
Detect when used descriptors are ready for consumption by the guest via
packed virtqueues and forward them from the device to the guest.
Signed-off-by: Sahil Siddiq
---
Changes from v4 -> v5:
- New commit.
- vhost-shadow-virtqueue.c:
(vhost_svq_more_used): Split into vhost_svq_more_used_split a
Implement the insertion of available buffers in the descriptor area of
packed shadow virtqueues. It takes into account descriptor chains, but
does not consider indirect descriptors.
Enable the packed SVQ to forward the descriptors to the device.
Signed-off-by: Sahil Siddiq
---
Changes from v4 ->
Hi,
I had a few more queries here as well.
On 3/24/25 7:29 PM, Sahil Siddiq wrote:
Detect when used descriptors are ready for consumption by the guest via
packed virtqueues and forward them from the device to the guest.
Signed-off-by: Sahil Siddiq
---
Changes from v4 -> v5:
- New commit.
- vh
On Mon, Mar 24, 2025 at 6:09 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Mon, Mar 24, 2025 at 12:19 PM wrote:
> >
> > From: Qiang Yu
> >
> > It's used already, just check it explicitly.
> >
> > Signed-off-by: Qiang Yu
> > ---
> > ui/egl-helpers.c | 10 ++
> > 1 file changed, 6 insertions
Hi,
On 3/6/25 12:53 PM, Eugenio Perez Martin wrote:
On Thu, Mar 6, 2025 at 6:26 AM Sahil Siddiq wrote:
[...]
On 2/11/25 1:27 PM, Eugenio Perez Martin wrote:
[...]
[ 49.173243] watchdog: BUG: soft lockup - CPU#1 stuck for 25s!
[NetworkManager:782]
[ 49.174167] Modules linked in: rfkill i
Hi Eric,
> -Original Message-
> From: qemu-devel-
> bounces+shameerali.kolothum.thodi=huawei@nongnu.org devel-bounces+shameerali.kolothum.thodi=huawei@nongnu.org> On
> Behalf Of Eric Auger
> Sent: Monday, March 24, 2025 1:13 PM
> To: Shameerali Kolothum Thodi
> ; Nicolin Chen
>
>
On Mon, Mar 24, 2025 at 5:30 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Mon, Mar 24, 2025 at 12:20 PM wrote:
> >
> > From: Qiang Yu
> >
> > Signed-off-by: Qiang Yu
> > ---
> > meson.build| 2 +-
> > ui/spice-display.c | 65 +++---
> > 2 files cha
Hi,
I managed to fix a few issues while testing this patch series.
There is still one issue that I am unable to resolve. I thought
I would send this patch series for review in case I have missed
something.
The issue is that this patch series does not work every time. I
am able to ping L0 from L2
Introduce "struct vring_packed".
Modify VhostShadowVirtqueue so it can support split and packed virtqueue
formats.
Signed-off-by: Sahil Siddiq
---
Changes from v4 -> v5:
- This was commit #3 in v4. This has been reordered to commit #2
based on review comments.
- Place shadow_avail_idx, shadow_
Philippe Mathieu-Daudé writes:
> On 24/3/25 11:21, Alex Bennée wrote:
>> We've not yet deprecated but we should steer users away from these
>> helpers if they want to be in a single/heterogeneous binary.
>
> Why not deprecate?
I guess philosophically do we expect to eventually convert all fronte
On 3/24/25 03:21, Alex Bennée wrote:
The current helper.h functions rely on hard coded assumptions about
target endianess to use the tswap macros. We also end up double
swapping a bunch of values if the target can run in multiple endianess
modes. Avoid this by getting the target to pass the endia
On 23/3/25 23:49, BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Richard Henderson wrote:
On 3/23/25 15:13, BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Philippe Mathieu-Daudé wrote:
On 23/3/25 20:07, Richard Henderson wrote:
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 28fbbb8d
On 3/24/25 03:21, Alex Bennée wrote:
It's not used outside of the gdbstub code.
Reviewed-by: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
target/ppc/cpu.h | 1 -
target/ppc/gdbstub.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
Revie
On 24/3/25 11:21, Alex Bennée wrote:
This is a pretty simple conversion given a single set of registers and
an existing helper to probe endianess.
Signed-off-by: Alex Bennée
---
v2
- use mb_cpu_is_big_endian
- use explicit MO_32 size
- handle differing size of env->ear between user/sy
On 24/3/25 11:21, Alex Bennée wrote:
We've not yet deprecated but we should steer users away from these
helpers if they want to be in a single/heterogeneous binary.
Why not deprecate?
Signed-off-by: Alex Bennée
---
include/gdbstub/helpers.h | 4 +++-
1 file changed, 3 insertions(+), 1 del
On 24/3/25 10:09, Daniel P. Berrangé wrote:
On Mon, Mar 24, 2025 at 12:00:06AM +0100, Philippe Mathieu-Daudé wrote:
The break in the QEMU_OPTION_machine case is mis-placed.
I think that's largely a bikeshed colouring question. If you
look at other places in the outer switch using a block in
th
Replace the comma at the end of the line by a semicolon.
Fixes: 41868f846d2 ("s390x/cpumodel: "host" and "qemu" as CPU subclasses")
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 del
On 3/23/25 15:53, Philippe Mathieu-Daudé wrote:
@@ -772,7 +777,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
* If all bits are significant, and len is small,
* this devolves to tlb_flush_page.
*/
-if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
On 3/19/25 7:34 PM, Nicolin Chen wrote:
> On Wed, Mar 19, 2025 at 07:09:33PM +0100, Eric Auger wrote:
>>> Option means something like this:
>>> -device smmuv3,accel=on
>>> instead of
>>> -device "smmuv3-accel"
>>> ?
>>>
>>> Yea, I think that's good.
>> Yeah actually that's a big debate f
On Thu, Mar 20, 2025 at 08:21:18PM +0800, Haoqian He wrote:
2025年3月19日 22:50，Stefano Garzarella 写道：
On Fri, Mar 14, 2025 at 06:15:32AM -0400, Haoqian He wrote:
This patch contains two changes:
1. Add VM state change cb type VMChangeStateHandlerExt which has return
value for virtio devices V
Hi
On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
>
> On Mon, Mar 24, 2025 at 6:04 PM Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Mon, Mar 24, 2025 at 12:19 PM wrote:
> > >
> > > From: Qiang Yu
> > >
> > > mesa/radeonsi is going to support explicit midifier which
> > > may export a multi
Hi Jason,
On 3/19/25 1:31 AM, Jason Gunthorpe wrote:
> On Tue, Mar 18, 2025 at 07:31:36PM +0100, Eric Auger wrote:
>> Nevertheless I don't think anything prevents the acceleration granted
>> device from also working with virtio/vhost devices for instance unless
>> you unplug the existing infra.
>
On 2025-03-24 11:12, Daniel P. Berrangé wrote:
> On Wed, Mar 19, 2025 at 05:36:20PM +0100, Juraj Marcin wrote:
> > From: Juraj Marcin
> >
> > The default idle period for TCP connection could be even 2 hours.
> > However, in some cases, the application needs to be aware of a
> > connection issue m
This commit refactors vhost_svq_add_split and vhost_svq_add to simplify
their implementation and prepare for the addition of packed vqs in the
following commits.
Signed-off-by: Sahil Siddiq
---
No changes from v4 -> v5.
hw/virtio/vhost-shadow-virtqueue.c | 107 +++--
1 f
On 3/24/25 03:21, Alex Bennée wrote:
We can handle larger sized memops now, expand the range of the assert.
Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits)
Signed-off-by: Alex Bennée
---
v2
- instead of 128 use 1 << MO_SIZE for future proofing
---
include/exec/memop.h | 4 ++--
1 file
Allocate memory for the packed vq format and map them to the vdpa device.
Since "struct vring" and "struct vring_packed's vring" both have the same
memory layout, the implementation in SVQ start and SVQ stop should not
differ based on the vq's format.
Also initialize flags, counters and indices f
Validate transport device features required for utilizing packed SVQ
that both guests can use with the SVQ and SVQs can use with vdpa.
Signed-off-by: Sahil Siddiq
---
Changes from v4 -> v5:
- Split from commit #2 in v4.
hw/virtio/vhost-shadow-virtqueue.c | 3 +++
1 file changed, 3 insertions(+)
This commit is the first in a series to add support for packed
virtqueues in vhost_shadow_virtqueue.
Linux commit 1225c216d954 ("vp_vdpa: allow set vq state to initial
state after reset") enabled the vp_vdpa driver to set the vq state to
the device's initial state. This works differently for split
On Mon, Mar 24, 2025 at 04:42:28PM +0530, Ani Sinha wrote:
> On Mon, Mar 24, 2025 at 1:13 PM Gerd Hoffman wrote:
> >
> > Hi,
> >
> > > > Going ship the distro kernel as igvm image would work too. Will
> > > > simplify the measurement pre-calculation. Also there is no need to pass
> > > > aroun
On Fri, Mar 21, 2025 at 03:09:17PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> Calling qmp_block_set_io_throttle() will be blocked for a long time
> when a network disk is configured and the network failure is just about
> to occur.
>
> Therefore, we add a timeout parameter for qmp_block_s
On 3/23/25 15:40, Philippe Mathieu-Daudé wrote:
'cpu_list' might be defined per target, and force code to be
built per-target. We can avoid that by introducing a CPUClass
callback.
This series combined with another which converts CPU_RESOLVING_TYPE
to a runtime helper, allows to move most of cpu
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/xlnx-zynqmp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index d6022ff2d3d..ec2b3a41eda 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff -
The following patches are queued for QEMU stable v7.2.17:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2025-03-24 (frozen), and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any add
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
From: Thomas Huth
We've got a dedicated section for UI options nowadays, so the
D-Bus display should get reported here, too.
Signed-off-by: Thomas Huth
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 41f68d38069..205fb43bf7b 1
On Tue, Mar 25, 2025 at 9:51 AM Thomas Huth wrote:
>
> From: Thomas Huth
>
> We've got a dedicated section for UI options nowadays, so the
> D-Bus display should get reported here, too.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Marc-André Lureau
> ---
> meson.build | 2 +-
> 1 file changed
From: Richard Henderson
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_ch
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
From: Richard Henderson
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_ch
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
From: Guo Hongyu
Refer to the link below for a description of the vldi instructions:
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
Fixed errors in vldi instruction implementation.
Signed-off-by: Guo Hongyu
Tested-by: Xianglai Li
Signed-off-by: Xianglai Li
Reviewed
From: Santiago Monserrat Campanello
semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Reviewed-by: Alistair Francis
Reviewed-by: Thomas Huth
Message-ID: <20250305102632.91376-1-santimons...@gmail.com>
S
The following patches are queued for QEMU stable v9.2.3:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-03-24 (frozen), and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/9.2
Please respond here or CC qemu-sta...@nongnu.org on any addi
From: Chao Liu
Some vector instructions are special, such as the vlm.v instruction,
where setting its vl actually sets evl = (vl + 7) >> 3. To improve
maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to
check for the condition vstart >= vl. This function will also handle
cases inv
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
From: Harsh Prateek Bora
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-9.0) at that time.
This caused breakge in default cpu evaluation for older pseries
machines and hence this fix.
Fixes: 51113013f3 ("ppc/spapr: change pseries machine
From: Konstantin Shkolnyy
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Reviewed-by: Michael S.
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
From: Konstantin Shkolnyy
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Reviewed-by: Michael S.
Fixes: 9bc9e9511944 (make-release: switch to .xz format by default)
Signed-off-by: Michael Tokarev
Reviewed-by: Philippe Mathieu-Daudé
(cherry picked from commit 14fb6dbbc50f43057202c685c3aa017287cca37f)
Signed-off-by: Michael Tokarev
diff --git a/Makefile b/Makefile
index b65b0bd41a..c92a3cf78
From: Philippe Mathieu-Daudé
These warnings are breaking some build configurations since 2 months
now (https://gitlab.com/qemu-project/qemu/-/issues/2575):
ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated:
first deprecated in macOS 15.0 - use NSView.displayLink(targe
From: Nicholas Piggin
DSRR0/1 registers are in the BookE ISA not e200 specific, so
remove the duplicate e200 register definitions.
Cc: Roman Kapl
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768
Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging")
Signed-
From: Steven Lee
Updated the IRQ handler mask check to AND with select variable.
This ensures that the interrupt service routine is correctly triggered
for the interrupts within the same irq group.
For example, both `eth0` and the debug UART are handled in `GICINT132`.
Without this fix, the debu
On Tue, Mar 25, 2025 at 2:37 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Tue, Mar 25, 2025 at 7:26 AM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 10:06 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
> > > >
> > > > On Mon, Mar 24, 20
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
From: Richard Henderson
The third argument of the syscall contains the size of the
cpu mask in bytes, not bits. Nor is the size rounded up to
a multiple of sizeof(abi_ulong).
Cc: qemu-sta...@nongnu.org
Reported-by: Andreas Schwab
Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
From: Nicholas Piggin
DSRR0/1 registers are in the BookE ISA not e200 specific, so
remove the duplicate e200 register definitions.
Cc: Roman Kapl
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768
Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging")
Signed-
We include this header where needed. When includes set already have
ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the
include.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h |
This define is used only in accel/kvm/kvm-all.c, so we push directly the
definition there. Add more visibility to kvm_arch_on_sigbus_vcpu() to
allow removing this define from any header.
The architectures defining KVM_HAVE_MCE_INJECTION are i386, x86_64 and
aarch64.
Reviewed-by: Richard Henderson
Now we made sure important defines are included using their direct
path, we can remove cpu.h from cpu-all.h.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
accel/tcg/cpu-exec.c | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --gi
Those files will be compiled once per base architecture ("arm" in this
case), instead of being compiled for every variant/bitness of
architecture.
We make sure to not include target cpu definitions (exec/cpu-defs.h) by
defining header guard directly. This way, a given compilation unit can
access a
Directly condition associated calls in target/arm/helper.c for now.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/arm/helper.c | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/c
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 1 +
include/exec/poison.h | 1 +
accel/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/meson.build | 112 ++---
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 9e8c96059eb..09b1cfe5b57 100644
--- a/hw/arm/me
Do not rely on target dependent type, but use a fixed type instead.
Since the original type is unsigned, it should be safe to extend its
size without any side effect.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 10 --
target/arm/tcg/hflag
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index e5d852fbe2c..db44c0d3016 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -23,7 +2
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -971,7 +971,6 @@ str
From: Thomas Huth
This test currently fails if the "dbus" display has not been compiled
into the binary (which can happen when CFI has been enabled, for example).
Check for the error message to skip the test in that case.
While we're at it, also make sure that this test is covered in the
right s
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/ppc/mmu-hash64.h | 2 ++
target/i386/tcg/system/excp_helper.c | 1 +
target/i386/xsave_helper.c | 1 +
target/riscv/vector_helper.c | 1 +
5 files
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/xlnx-versal.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 278545a3f7b..f0b383b29ee 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/digic_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 2492fafeb85..466b8b84c0e 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
bibo mao writes:
> Markus,
>
> Thanks for your reviewing and guidance.
You're welcome!
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero; also allow folding
stack pointer offsets into the arithmetic.
So far, all offsets are 0.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 42 --
1 file change
On 3/23/25 10:37, Richard Henderson wrote:
Not that AVR has memory paging traps, but it's better
form to allow the memory operation to finish before
updating the cpu register.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 32 +++-
1 file changed, 1
Now we eliminated poisoned identifiers from headers, this file can now
be compiled once for all arm targets.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/boot.c | 1 +
hw/arm/meson.build | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/h
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
accel/tcg/tb-internal.h | 1 -
include/exec/cpu-all.h | 22 --
include/hw/core/cpu.h | 2 +-
include/qemu/bswap.h| 2 +-
target/alpha/cpu.h | 2 --
target/arm/cpu.h| 2 --
target/avr/c
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index eb029b65552..4a2cac1252d 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -19,7 +1
On 3/24/25 22:08, Michael Tokarev wrote:
24.03.2025 23:46, Cédric Le Goater wrote:
Is there anything in there worth to pick up for stable series?
you are fast !
I was just about to send final announcements for a bunch of next
stable releases, and noticed another pull request has been merged
Hi
On Tue, Mar 25, 2025 at 7:26 AM Qiang Yu wrote:
>
> On Mon, Mar 24, 2025 at 10:06 PM Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
> > >
> > > On Mon, Mar 24, 2025 at 6:04 PM Marc-André Lureau
> > > wrote:
> > > >
> > > > Hi
> > > >
> > > > On
Register x86_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/i386/cpu.h | 3 ---
target/i386/cpu.c | 3 ++-
2 files changed, 2 insertions(+),
Register sparc_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/sparc/cpu.h | 3 ---
target/sparc/cpu.c | 3 ++-
2 files changed, 2 insertions
On 3/24/25 03:21, Alex Bennée wrote:
For some of the helpers we need a temporary variable to copy from
although we could add some helpers to return pointers into env in
those cases if we wanted to.
Signed-off-by: Alex Bennée
---
v2
- use MO32/MO64 varients for reg sizes
- use wrappers fo
On Fri, Mar 21, 2025 at 11:17 AM Miles Glenn wrote:
>
> On Thu, 2025-03-20 at 16:09 -0400, Stefan Hajnoczi wrote:
> > On Thu, Mar 20, 2025 at 12:34 PM Miles Glenn wrote:
> > > Hello,
> > >
> > > I am attempting to simulate a system with multiple CPU
> > > architectures. To do this I am starting
23.03.2025 20:45, Cédric Le Goater wrote:
Jamin Lin (1):
hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
Steven Lee (1):
hw/intc/aspeed: Fix IRQ handler mask check
Troy Lee (1):
aspeed: Fix maximum number of spi controller
Is there anything in there worth
Since v2
- Added R-b tags
- Added missing s390x hunk
Since v1 (Thomas review comments)
- Move s390_set_qemu_cpu_model/s390_cpu_list to "cpu_models.h"
- Correct 'target/s390x: Register CPUClass:list_cpus' subject
'cpu_list' might be defined per target, and force code to be
built per-target. We can
On 3/24/25 12:03, Philippe Mathieu-Daudé wrote:
On 24/3/25 19:59, Pierrick Bouvier wrote:
On 3/24/25 11:46, Philippe Mathieu-Daudé wrote:
Since v1 (Thomas review comments)
- Move s390_set_qemu_cpu_model/s390_cpu_list to "cpu_models.h"
- Correct 'target/s390x: Register CPUClass:list_cpus' subjec
On 3/23/25 12:48, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 98a69846119..c367c2dcb99 100644
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, March 20, 2025 11:29 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; long...@lenovo.com
On 3/23/25 15:50, Philippe Mathieu-Daudé wrote:
The following macros:
- qemu_put_betl()
- qemu_get_betl()
- qemu_put_betls()
- qemu_get_betls()
- qemu_put_sbetl()
- qemu_get_sbetl()
- qemu_put_sbetls()
- qemu_get_sbetls()
are not used in the whole code base, remove them.
Signed
On 3/23/25 15:50, Philippe Mathieu-Daudé wrote:
We only use qemu_get_betl() and qemu_put_betl() once in
the whole code base. Inline them (checking TARGET_SPARC64
instead of TARGET_LONG_BITS == 64) so we can remove them
later as unused.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/ma
> -Original Message-
> From: Brian Cain
> Sent: Saturday, March 1, 2025 11:21 AM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsimp
On 3/23/25 15:50, Philippe Mathieu-Daudé wrote:
We only use qemu_get_betls() and qemu_put_betls() once in
the whole code base. Inline them (checking TARGET_MIPS64
instead of TARGET_LONG_BITS == 64) so we can remove them
later as unused.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/sy
On 3/23/25 12:37, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf
101 - 200 of 307 matches
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