On Thu, Mar 13, 2025 at 4:27 PM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> For privilege version 1.12 or newer, C always implies Zca. We can only
> check ext_zca to allow 16-bit aligned PC addresses. For older privilege
> versions, we only check C.
>
> Signed-off-by: Yu-Ming Chang
Please increm
On 3/18/25 17:42, Pierrick Bouvier wrote:
On 3/18/25 14:32, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/icount.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/exec/icount.h b/include/exec/icount.h
index 4964987ae4..7a26b4
On 3/18/25 14:32, Richard Henderson wrote:
This is include/system, so CONFIG_USER_ONLY will never be true.
Signed-off-by: Richard Henderson
---
include/system/qtest.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/system/qtest.h b/include/system/qtest.h
index 6c501b..84b1f8
In expression 1ULL << tlb_ps, left shifting by more than 63 bits has undefined
behavior.
The shift amount, tlb_ps, is as much as 64. check "tlb_ps >=64" to fix.
Resolves: Coverity CID 1593475
Fixes: d882c284a3 ("target/loongarch: check tlb_ps")
Suggested-by: Peter Maydell
Signed-off-by: Song G
On Tue, Mar 18, 2025 at 03:17:33PM +0100, Andreas Schwab wrote:
> On Mär 18 2025, Daniel P. Berrangé wrote:
>
> > That would get the synchronization behaviour of Linux vfork,
> > but I'm not sure it'd get the performance benefits (of avoiding
> > page table copying) which is what Andreas mentione
On 18/3/25 05:51, Pierrick Bouvier wrote:
This will affect zregs field for aarch32.
This field is used for MVE and SVE implementations. MVE implementation
is clipping index value to 0 or 1 for zregs[*].d[],
so we should not touch the rest of data in this case anyway.
We should describe why it i
On Wednesday, March 12, 2025 4:29:26 PM CET Greg Kurz wrote:
> QEMU 9.2 already fixed the long standing limitation of failing fstat() on
> unlinked files. This series does something similar for ftruncate().
>
> The following program can be straced inside the guest with a shared fs in
> passthrough
On 3/18/25 1:42 PM, Peter Maydell wrote:
On Fri, 7 Mar 2025 at 12:46, Daniel Henrique Barboza
wrote:
Coverity found the following issue:
>>> CID 1593156: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
>>> Potentially overflowing expression "0x10 << depth" with type
"int
On 3/18/25 14:31, Richard Henderson wrote:
Avoid testing CONFIG_USER_ONLY in semihost.h.
The only function that's required is semihosting_enabled.
Signed-off-by: Richard Henderson
---
include/semihosting/semihost.h | 29 ++---
semihosting/user.c | 15 +
On 3/18/25 14:31, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 58 ++
On Tue, Mar 18, 2025 at 07:31:36PM +0100, Eric Auger wrote:
> Nevertheless I don't think anything prevents the acceleration granted
> device from also working with virtio/vhost devices for instance unless
> you unplug the existing infra.
If the accel mode is using something like vcmdq then it is n
On 3/18/25 14:31, Richard Henderson wrote:
Relatively few objects in qemu care about watchpoints, so split
out to a new header. Removes an instance of CONFIG_USER_ONLY
from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/exec/watchpoint.h | 41 ++
On 3/18/25 14:31, Richard Henderson wrote:
Some of the headers used require CONFIG_USER_ONLY.
Do not move vl.c, because it has other include dependencies
that are present in system_ss.
Signed-off-by: Richard Henderson
---
system/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 del
On 3/18/25 14:31, Richard Henderson wrote:
We do not set CONFIG_SEMIHOSTING in
configs/targets/mips*-linux-user.mak.
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b
On 3/18/25 14:31, Richard Henderson wrote:
Headers used by these files require CONFIG_USER_ONLY.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
plugins/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/plugins/meson.build b/plugins/meson
On 3/18/25 14:32, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deleti
On 3/18/25 14:32, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/icount.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/exec/icount.h b/include/exec/icount.h
index 4964987ae4..7a26b40084 100644
--- a/include/exec/icount.h
+++
On 3/18/25 14:31, Richard Henderson wrote:
We do not set CONFIG_SEMIHOSTING in
configs/targets/xtensa*-linux-user.mak.
Do not raise SIGILL for user-only unconditionally.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 24 +++-
1 file changed, 11 insertio
On 3/18/25 14:32, Richard Henderson wrote:
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All
On 3/18/25 14:32, Richard Henderson wrote:
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-off-by: Richard Henderson
---
include/exec/icount.h| 68 +++
On 3/18/25 14:31, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_IDX
requires the cpu.h for a specific target, and so is restric
We already have two subdirectories for which we need
to build files twice, for user vs system modes.
Move this handling to the top level.
This cannot be combined with user_ss or system_ss,
because the formulation has not been extended to support
configuration symbols.
Reviewed-by: Pierrick Bouvie
On 3/18/25 15:36, Richard Henderson wrote:
On 3/18/25 15:25, Pierrick Bouvier wrote:
On 3/18/25 15:21, Richard Henderson wrote:
On 3/18/25 15:16, Pierrick Bouvier wrote:
This doesn't make any sense to me. CPU_INCLUDE is defined within the very file
that
you're trying to include by avoiding "
On 3/17/25 21:51, Pierrick Bouvier wrote:
To eliminate TARGET_AARCH64, we need to make various definitions common
between 32 and 64 bit Arm targets.
Added registers are used only by aarch64 code, and the only impact is on
the size of CPUARMState, and added zarray
(ARMVectorReg zarray[ARM_MAX_VQ *
Am 18.03.2025 um 11:58 hat ger...@altlinux.org geschrieben:
> From: Denis Rastyogin
>
> This error was discovered by fuzzing qemu-img.
>
> The qcow2_refresh_limits() is missing a check
> for the s->crypto pointer, which can lead to
> a null pointer dereference. This commit adds the necessary che
Add a unit test to cover some patterns accepted by vmstate_of and
vmstate_struct macros, which correspond to the following C version
macros:
* VMSTATE_BOOL_V
* VMSTATE_U64
* VMSTATE_STRUCT_VARRAY_UINT8
* (no C version) MULTIPLY variant of VMSTATE_STRUCT_VARRAY_UINT32
* VMSTATE_ARRAY
Signed-o
Shameer,
Hi,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen
Allocate and associate a vDEVICE object for the Guest device
with the vIOMMU. This will help the kernel to do the
vSID --> sid translation whenever required (eg: device specific
invalidations).
Signed-off-by: Nicoli
On Friday, March 7, 2025 10:24:12 AM CET Christian Schoenebeck wrote:
> Three fixes for 9p server's v9fs_reclaim_fd() function:
>
> * Patch 1 fixes a concurrency issue.
>
> * Patch 2 fixes a file descriptor leak and optimizes overall latency. On a
> test
> machine with ~800,000 FIDs, this redu
On 3/18/2025 2:14 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Sid Manning
Sent: Tuesday, March 18, 2025 1:34 PM
To: ltaylorsimp...@gmail.com; 'Brian Cain'
; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
(QUIC) ; a...@re
On 3/18/25 18:05, Richard Henderson wrote:
On 3/18/25 16:52, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
The code is very similar to do_
On 3/18/25 16:52, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
The code is very similar to do_ld*_mmu functions, so it's subtle to notice.
On 3/18/25 14:31, Richard Henderson wrote:
These routines are buggy in multiple ways:
- Use of target-endian loads, then a bswap that
depends on the host endiannness.
- A non-unwinding code load must set_helper_retaddr 1,
which is magic within adjust_signal_pc.
- cpu_ldq_code_m
On 3/18/25 17:02, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_IDX
requires the cpu
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, March 18, 2025 8:39 PM
> To: Troy Lee ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
> Cc: Yunlin Tang
> Subject: Re: [PAT
On 3/18/25 17:15, Pierrick Bouvier wrote:
@@ -329,7 +331,39 @@ static bool translator_ld(CPUArchState *env,
DisasContextBase *db,
host = db->host_addr[1];
}
- memcpy(dest, host + (pc - base), len);
+ do_read:
+ /*
+ * Assume aligned reads should be atomic, if possible.
For some paravirt KVM features, if user forces to enable it however
KVM does not support, qemu should fail to run and exit immediately,
rather than continue to run. Here set error message and return directly
in function kvm_arch_init_vcpu().
Fixes: 6edd2a9bec90 (target/loongarch/kvm: Implement Loo
This patch set solves errors reported by coccinelle tool with commands:
spatch --sp-file scripts/coccinelle/*.cocci --dir target/loongarch/
spatch --sp-file scripts/coccinelle/*.cocci --dir hw/loongarch/
The main problem is that qemu should fail to run when feature is forced
to enabled however
In function virt_cpu_irq_init(), there is notification with ipi and extioi
interrupt controller for cpu creation. Local variable with error type is
used, however there is no check with its return value.
Here set dest error object with error_abort, rather than local variable, so
application will ab
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff -
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source
high-performance RISC-V processor. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Note:
The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized
based on four RISC-V specifications: Volume I
On Tue, 18 Mar 2025 at 17:18, Daniel P. Berrangé wrote:
>
> On Tue, Mar 18, 2025 at 05:08:52PM +, Peter Maydell wrote:
> > On Tue, 18 Mar 2025 at 15:04, Peter Maydell
> > wrote:
> > > More generally, AIUI glibc expects that it has control over what's
> > > happening with threads, so it can s
Hi Alex,
Thanks and Sorry about the delay in responding. I had to figure out
many nuances for answering your questions.
Replies inline..
On 2/1/25 3:32 AM, Alex Williamson wrote:
On Fri, 31 Jan 2025 17:15:01 +
Shivaprasad G Bhat wrote:
Currently, the PCI_INTERRUPT_PIN alone is checked b
On Tue, Mar 18, 2025 at 07:31:36PM +0100, Eric Auger wrote:
> On 3/17/25 9:19 PM, Nicolin Chen wrote:
> > On Mon, Mar 17, 2025 at 04:24:53PM -0300, Jason Gunthorpe wrote:
> >> On Mon, Mar 17, 2025 at 12:10:19PM -0700, Nicolin Chen wrote:
> >>> Another question: how does an emulated device work with
qcow2_refresh_limits() assumes that s->crypto is non-NULL whenever
bs->encrypted is true. This is actually not the case: qcow2_do_open()
allows to open an image with a missing crypto header for BDRV_O_NO_IO,
and then bs->encrypted is true, but s->crypto is still NULL.
It doesn't make sense to open
On Tue, 18 Mar 2025 at 10:36, Helge Deller wrote:
>
> On 3/18/25 11:18, Andreas Schwab wrote:
> > Is there a generic way for a program to detect that is it being run
> > inside the linux-user emulation?
>
> Yes, having a reliable way to detect it would be good.
>
> My current (unreliable) way to d
These need to be per-target for 'abi_ptr'. Expand inline to
the *_data_ra api with ra == 0.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_common.c.inc | 89 --
2
On Wed, Mar 19, 2025 at 7:36 AM Richard Henderson
wrote:
>
> Perform aligned atomic reads in translator_ld, if possible.
> According to
>
> https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
>
> this is required for RISC-V Ziccif.
Thanks Richard!!
>
> Signed-off-by: Ric
Hi Lei,
On 3/18/2025 7:06 AM, Lei Yang wrote:
On Tue, Mar 18, 2025 at 10:15 AM Jason Wang wrote:
On Tue, Mar 18, 2025 at 9:55 AM Lei Yang wrote:
Hi Jonah
I tested this series with the vhost_vdpa device based on mellanox
ConnectX-6 DX nic and hit the host kernel crash. This problem can be
ea
On 3/18/25 14:31, Richard Henderson wrote:
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c |
Some of the headers used require CONFIG_USER_ONLY.
Do not move vl.c, because it has other include dependencies
that are present in system_ss.
Signed-off-by: Richard Henderson
---
system/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/system/meson.build b/sy
Am 18.03.2025 um 14:00 hat ger...@altlinux.org geschrieben:
> You can reproduce this issue by running ./qemu-img info segv.
> The segv file used for reproduction can be found here:
> https://github.com/Gerben100/reproduce_qemu-img_error
Thanks. Your patch makes sure that qemu-img doesn't crash a
On 3/18/25 09:59, Peter Maydell wrote:
On Sat, 15 Mar 2025 at 14:20, Guenter Roeck wrote:
Without psci_conduit, the Linux kernel crashes almost immediately.
psci: probing for conduit method from DT.
Internal error: Oops - Undefined instruction: 0200 [#1]
PREEMPT SMP
Fi
From: YannickV
This commit introduces a new machine, derived from xilinx-zynq-a9,
as a starting point for the Beckhoff CX7200 integration. Functions
and structs are renamed to delimit the CX7200 board emulation from
the existing Zynq emulation.
At this stage, the new machine is a direct copy of
We assert that env immediately follows CPUState in cpu-all.h.
Change the offsetof expressions to be based on CPUState instead
of ArchCPU.
Reviewed-by: Alex Bennée
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 13 +
accel/tcg/meson.build
These need to be per-target for 'abi_ptr'. Expand inline to
the *_mmuidx_ra api with a lookup of the target's cpu_mmu_index().
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 144 +---
accel/tcg/ldst_common.c.inc
Split out the *_mmu api, which no longer uses
target specific argument types.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu-ldst-common.h | 122 +
include/exec/cpu_ldst.h| 108 +
2 files ch
Convert the existing includes with sed.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
hw/net/i82596.h | 2 +-
hw/s390x/ipl.h| 2 +-
include/hw/misc/lasi.h| 2 +-
i
Convert the existing includes with sed.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/{exec => system}/ram_addr.h | 7 +++
accel/kvm/kvm-all.c | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c | 2 +-
hw/ppc/
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of this.
Remove exec/tswap.h from translator.c.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/tran
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 58 ++-
2 files changed,
On 3/18/25 15:25, Pierrick Bouvier wrote:
On 3/18/25 15:21, Richard Henderson wrote:
On 3/18/25 15:16, Pierrick Bouvier wrote:
This doesn't make any sense to me. CPU_INCLUDE is defined within the very file
that
you're trying to include by avoiding "cpu.h".
Every target/X/cpu.h includes cpu
On 3/18/25 14:41, Richard Henderson wrote:
On 3/17/25 21:51, Pierrick Bouvier wrote:
This identifier is already poisoned, so it can't be used from common
code anyway.
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
I
On Tue, Mar 18, 2025 at 09:11:43PM +0100, Kevin Wolf wrote:
> qcow2_refresh_limits() assumes that s->crypto is non-NULL whenever
> bs->encrypted is true. This is actually not the case: qcow2_do_open()
> allows to open an image with a missing crypto header for BDRV_O_NO_IO,
> and then bs->encrypted
Based-on: 20250317183417.285700-1-pierrick.bouv...@linaro.org
("[PATCH v6 00/18] make system memory API available for common code")
v1: 20250313034524.3069690-1-richard.hender...@linaro.org
A number of bugs have been fixed from v1, and small adjustments.
Phil came up with a better version of one
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 42 ++
Reviewed-by: Niek Linnenbank
On Tue, Mar 18, 2025 at 7:14 AM Thomas Huth wrote:
> From: Thomas Huth
>
> We don't use the term "integration tests" for these kind of tests
> anymore, it's "functional tests" nowadays.
>
> Suggested-by: Niek Linnenbank
> Signed-off-by: Thomas Huth
> ---
> docs/
Reviewed-by: Niek Linnenbank
On Tue, Mar 18, 2025 at 6:54 AM Thomas Huth wrote:
> From: Thomas Huth
>
> To avoid problems with the meson installation from the host
> system, we should always use the meson from our venv instead.
> Thus use this in the documentation, too.
>
> While we're at it,
On 3/17/25 21:51, Pierrick Bouvier wrote:
This will affect zregs field for aarch32.
This field is used for MVE and SVE implementations. MVE implementation
is clipping index value to 0 or 1 for zregs[*].d[],
so we should not touch the rest of data in this case anyway.
Signed-off-by: Pierrick Bouv
Doesn't this commit become moot, if accel becomes an smmuv3 option vs separate
device object altogether,
dynamically added if a pdev is attached to a host SMMUv3 that has accel
feature(s)?
Blocking w/virtio-iommu falls under the same situation mentioned in 03/20 wrt
mixing emulated & physica
While setup_post and has_memory will not be used for
CONFIG_USER_ONLY, let the struct have constant layout.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/include/qemu/accel.h
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-off-by: Richard Henderson
---
include/exec/icount.h| 68
include/system/cpu-timers.h |
As discussed in [1], this series modifies the SoC class be derived from
TYPE_SYS_BUS_DEVICE to fix the reset mechanism and to prevent it from being
user-creatable. It also removes an unused define.
v3:
* Fix reference counting in separate commit (Peter)
v2:
* Do not set user_creatable = false; (Z
Avoid testing CONFIG_USER_ONLY in semihost.h.
The only function that's required is semihosting_enabled.
Signed-off-by: Richard Henderson
---
include/semihosting/semihost.h | 29 ++---
semihosting/user.c | 15 +++
semihosting/meson.build| 2
On 3/17/25 21:51, Pierrick Bouvier wrote:
Do not rely on target dependent type, but use a fixed type instead.
Since the original type is unsigned, it should be safe to extend its
size without any side effect.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 2 +-
target/arm/tcg/h
From: Denis Rastyogin
This error was discovered by fuzzing qemu-img.
The qcow2_refresh_limits() is missing a check
for the s->crypto pointer, which can lead to
a null pointer dereference. This commit adds the necessary check.
Reported-by: Leonid Reviakin
Signed-off-by: Denis Rastyogin
---
bl
Remove the `unsafe` block of vmsd, because vmsd (passed to
vmstate_struct) is defined in Rust side now, and it doesn't need
`unsafe`.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/vmstate.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/q
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
which correspond to
Gather all VFIOcontainer related declarations into "container.h" to
reduce exposure of VFIO internals in "hw/vfio/vfio-common.h".
These declarations are made available externally for PPC and s390x.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h| 19 -
incl
On Tue, 18 Mar 2025 at 06:14, Thomas Huth wrote:
>
> From: Thomas Huth
>
> We don't use the term "integration tests" for these kind of tests
> anymore, it's "functional tests" nowadays.
>
> Suggested-by: Niek Linnenbank
> Signed-off-by: Thomas Huth
> ---
> docs/system/arm/bananapi_m2u.rst | 6
On 18/3/25 18:50, Peter Maydell wrote:
On Tue, 18 Mar 2025 at 17:42, Philippe Mathieu-Daudé wrote:
On 18/3/25 05:51, Pierrick Bouvier wrote:
Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/
TYPE_FSL_IMX8MP is created using object_new(), so must be realized with
qdev_realize_and_unref() to keep the reference counting intact.
Signed-off-by: Bernhard Beschow
---
hw/arm/imx8mp-evk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-
"hw/vfio/vfio-common.h" has been emptied of most of its declarations
by the previous changes and the only declarations left are related to
VFIODevice. Rename it to "hw/vfio/vfio-device.h" and make the
necessary adjustments.
Signed-off-by: Cédric Le Goater
---
hw/vfio/migration-multifd.h
The varry of structure created by vmstate_struct is different with
vmstate_of. This is because vmstate_struct uses the `vmsd` to traverse
the vmstates of structure's fields, rather than treating the structure
directly as a well-defined vmstate.
Therefore, there's no need to check array flag when b
The VMState type bound is not used in with_varray_flag().
And for vmstate_struct, Rust cannot infer the type of `num` from the
call_func_with_field(), so this causes the compiling error because it
complains "cannot satisfy `_: VMState`" in with_varray_flag().
Note Rust can infer the type in vmsta
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:29 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
> The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V,
> TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
> TV=1 does not contain a valid address translation information. If a request
> requ
This property enables the setting of the CLINT timebase frequency
through the command line, for example:
-machine microchip-icicle-kit,clint-timebase-frequency=1000
Signed-off-by: Sebastian Huber
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/microchip_pfsoc.c | 49
Mention that running the HSS no longer works. Document the changed boot
options. Reorder documentation blocks. Update URLs.
Signed-off-by: Sebastian Huber
---
docs/system/riscv/microchip-icicle-kit.rst | 124 +++--
1 file changed, 43 insertions(+), 81 deletions(-)
diff --git
Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine. If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.
For test runs, use an approach similar to
riscv_find_and_load_firmware().
S
Signed-off-by: Sebastian Huber
---
hw/misc/mchp_pfsoc_sysreg.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
index 7876fe0c5b..08196525aa 100644
--- a/hw/misc/mchp_pfsoc_sysreg.c
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -27,7 +27,
If the kernel entry is in the high DRAM area, place the FDT into this
area.
Signed-off-by: Sebastian Huber
Reviewed-by: Alistair Francis
---
hw/riscv/microchip_pfsoc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip
Bibo Mao writes:
> In function virt_cpu_irq_init(), there is notification with ipi and extioi
> interrupt controller for cpu creation. Local variable with error type is
> used, however there is no check with its return value.
Good catch.
When the first call fails, we pass non-null @err to the s
On Wed, Mar 19, 2025 at 12:22 PM Huang Borong wrote:
>
> This implementation provides emulation for the Xiangshan Kunminghu SoC,
> including support for UART, CLINT, IMSIC, and APLIC devices.
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
Can you add an entry to `docs
zhenwei pi writes:
> Hi Markus,
>
> Current code style seems buggy, I think the main reason is that the Error
> *errp is not generated at right place. keyctl_pkey_XXX fails without new
> error, qcrypto_akcipher_XXX fails with new error, but they are in the same
> switch-case code block. If we
Hi,
This is my v3, based on aa90f1161bb17 ("Merge tag 'migration-20250314-pull
-request' of https://gitlab.com/farosas/qemu into staging") at master
branch.
Compared with v2:
* the patch 10 drops `with_exist_check()` and `with_validate_flag()`.
* patch 15 is newly added to clen up VMStateFlags
On Fri, 14 Mar 2025 at 18:32, Bernhard Beschow wrote:
>
> The SoC has three SPI controllers, not four. Remove the extra define of an SPI
> IRQ.
>
> Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
> Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, Mar 13, 2025 at 4:27 PM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> For privilege version 1.12 or newer, C always implies Zca. We can only
> check ext_zca to allow 16-bit aligned PC addresses. For older privilege
> versions, we only check C.
>
> Signed-off-by: Yu-Ming Chang
Thanks!
Appl
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
which correspond to
Our KVM code includes backwards compatibility support for ancient
kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl. This
ioctl was introduced in kernel commit 42c4e0c77ac91 in September
2013 and is in v3.12, so it's reasonable to assume it's present.
(We already dropped support for
Bibo Mao writes:
> There is NULL pointer checking function error_propagate() already,
> it is not necessary to add checking for function parameter. Here remove
> NULL pointer checking with function parameter.
I believe the title "Remove unnecessary NULL pointer" and this paragraph
are remnants o
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