From: Philippe Mathieu-Daudé
There is no TARGET_ARM_64 definition. Luckily enough,
when TARGET_AARCH64 is defined, TARGET_ARM also is.
Fixes: 733766cd373 ("hw/arm: introduce xenpvh machine")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Mes
From: Peter Maydell
When the smc91c111 transmits a packet, it must read a control byte
which is at the end of the data area and CRC. However, we don't
sanitize the length field in the packet buffer, so if the guest sets
the length field to something large we will try to read past the end
of the
From: Peter Maydell
Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer. This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at
Add skeleton for handle "ibm,configure-kernel-dump" rtas call in QEMU.
Verify basic details mandated by the PAPR, such as number of
inputs/output, and add handling for the three fadump commands:
regiser/unregister/invalidate.
Currently fadump register will always return HARDWARE ERROR, since it's
Platform (ie. QEMU) is expected to pass few device tree properties for
details for fadump:
* "ibm,configure-kernel-dump-sizes": Space required to store dump data
for firmware provided dump sections (ie. CPU & HPTE regions)
* "ibm,configure-kernel-dump-version": Versions of fadump supported
With all support in place for preserving memory regions, enable fadump by
exporting the "ibm,kernel-dump" property in the device tree, representing
the fadump dump information, in case of a crash.
Currently "ibm,configure-kernel-dump" RTAS call is already registered,
which tells the kernel that th
From: Peter Maydell
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check
which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not
AArch64. This has been there since the GIC was first implemented,
but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ
then
From: Khem Raj
glibc 2.41+ has added [1] definitions for sched_setattr and
sched_getattr functions and struct sched_attr. Therefore, it needs
to be checked for here as well before defining sched_attr, to avoid
a compilation failure.
Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0
From: Peter Maydell
The pseudocode for the accessors for the LOR sysregs says they
are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong
syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-sta...@nongnu.org
Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension
From: Peter Maydell
The SMC91C111 includes an MMU Command register which permits
the guest to remove entries from the RX FIFO. The datasheet
does not specify what happens if the guest tries to do this
when the FIFO is already empty; there are no status registers
containing error bits which might
From: Peter Maydell
The smc91c111 uses packet numbers as an index into its internal
s->data[][] array. Valid packet numbers are between 0 and 3, but
the code does not generally check this, and there are various
places where the guest can hand us an arbitrary packet number
and cause an out-of-boun
From: Rodrigo Dias Correa
Instead of migrating the raw tick_offset, goldfish_rtc migrates a
recalculated value based on QEMU_CLOCK_VIRTUAL. As QEMU_CLOCK_VIRTUAL
stands still across a save-and-restore cycle, the guest RTC becomes out
of sync with the host RTC when the VM is restored.
As describe
From: Mikael Szreder
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and
From: Stefano Garzarella
The function `vhost_dev_init()` expects the `struct vhost_dev`
(passed as a parameter) to be fully initialized. This is important
because some parts of the code check whether `vhost_dev->config_ops`
is NULL to determine if it has been set (e.g. later via
`vhost_dev_set_co
From: Bernhard Beschow
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extractin
The following patches are queued for QEMU stable v7.2.17:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2025-03-24, and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any additional p
From: Philippe Mathieu-Daudé
By accessing MemoryRegion internals, amdvi_init() gives the false
idea that the PCI BAR can be modified. However this isn't true
(at least the model isn't ready for that): the device is explicitly
maps at the BAR at the fixed AMDVI_BASE_ADDR address in
amdvi_sysbus_re
From: Peter Maydell
In system register access pseudocode the common pattern for
AArch32 registers with access traps to EL3 is:
at EL1 and EL2:
if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure registered through the
ibm,configure-kernel-dump call, the platform must process each
registere
From: Greg Kurz
This was missed at the time.
Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise")
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250306174113.427116-1-gr...@kaod.org>
Signed-off-by: Thomas Huth
(cherry picked from commit
From: Nicholas Piggin
The commit to fix the OCC common area sensor mappings didn't update the
register offsets to match.
Before this change, skiboot reports:
[0.347100086,3] OCC: Chip 0 sensor data invalid
Afterward, there is no error and the sensor_groups directory appears
under /sys/firm
From: Kevin Wolf
Block drivers assume in their .bdrv_open() implementation that their
state in bs->opaque has been zeroed; it is initially allocated with
g_malloc0() in bdrv_open_driver().
bdrv_snapshot_goto() needs to make sure that it is zeroed again before
calling drv->bdrv_open() to avoid th
From: Patrick Venture
The reg isn't validated to be a possible register before
it's dereferenced for one case. The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.
Cc: qemu-sta...@nongnu.org
Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nu
From: Max Chou
According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=0, no operation is performed and the destination register is not
updated."
The vd should be updated when vl is larger than 0.
Fixes: fe5c9ab1fc ("target/riscv: vector single-width
From: Peter Maydell
For accesses to the 91c111 data register, the address within the
packet's data frame is determined by a combination of the pointer
register and the offset used to access the data register, so that you
can access data at effectively wider than byte width. The pointer
register'
From: Volker Rümelin
Windows only:
The libSDL2 Windows message loop needs the libSDL2 Windows low
level keyboard hook procedure to grab the left and right Windows
keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
Since SDL2 2.30.4 the SDL2 keyboard hook procedure also filters
o
From: Daniel Henrique Barboza
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size defaults to XLEN.
At this moment we're using def_size = 8 regardless of CPU
From: Denis Rastyogin
This error was discovered by fuzzing qemu-img.
In the QED block driver, the need_check_timer timer is freed in
bdrv_qed_detach_aio_context, but the pointer to the timer is not
set to NULL. This can lead to a use-after-free scenario
in bdrv_qed_drain_begin().
The need_check
From: Peter Maydell
The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and
CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED
from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the
access function in these cases, which means that we report the wrong
syndrome v
From: Sairaj Kodilkar
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not
enabled")
Signed-off-by: Sairaj K
From: Peter Maydell
When the smc91c111 transmits a packet, it must read a control byte
which is at the end of the data area and CRC. However, we don't
sanitize the length field in the packet buffer, so if the guest sets
the length field to something large we will try to read past the end
of the
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/hyperv/meson.build b/hw/hyperv/meson.build
index d3d2668c71a..f4aa0a5ada9 100644
--- a/hw/hyperv/meson.build
+++ b/hw/hyperv/meson.build
@@ -2,4 +2,5 @@ specific_ss.a
On 13/3/25 10:54, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 13/3/25 04:44, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/t
Hi Cedric,
> Cc: Troy Lee
> Subject: Re: [PATCH v4 18/23] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On 3/3/25 10:54, Jamin Lin wrote:
> > The design of INTC controllers has significantly changed in AST2700 A1.
> >
> > There are a total of 480 interrupt so
On 3/13/25 16:03, Tomita Moeko wrote:
A previous change made the OpRegion and LPC quirks independent of the
existing legacy mode, update the documentation accordingly. More related
topics, like creating EFI Option ROM of IGD for OVMF, how to solve the
VFIO_DMA_MAP Invalid Argument warning, as wel
cpu_memory_rw_debug() system implementation is defined in
system/physmem.c. Move the user one to accel/tcg/user-exec.c
to simplify cpu-target.c maintenance.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250217130610.18313-6-phi...@linaro.org>
---
accel/tcg/
On 3/12/25 20:45, Richard Henderson wrote:
Headers used by these files require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
plugins/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/plugins/meson.build b/plugins/meson.build
index 3be8245a69..5383c7
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for little-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-2-phi...@linaro.org>
---
target/alpha/cpu.c | 1 +
From: Stefano Stabellini
On IOREQ_TYPE_INVALIDATE we need to invalidate the mapcache for regular
mappings. Since recently we started reusing the mapcache also to keep
track of grants mappings. However, there is no need to remove grant
mappings on IOREQ_TYPE_INVALIDATE requests, we shouldn't do th
Currently the fetch code does not fail gracefully when retry limit is
exceeded, it just falls through the loop with no file, which ends up
hitting other errors.
Add a check for non-existing file, which indicates the retry limit was
exceeded.
Signed-off-by: Nicholas Piggin
---
tests/functional/q
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 8df6a97a28..c25c966278 100755
--- a/tests/fu
This commit introduces support for the ASPEED AST2700 full core
machine. It includes the initialization of CA35, SSP, and TSP components
with their respective memory regions and clocks. The new file
aspeed_ast27x0-fc.c defines the machine type "ast2700fc-a0" and its
initialization functions. Additi
On 2025/3/14 下午1:38, Markus Armbruster wrote:
bibo mao writes:
On 2025/3/13 下午6:32, Markus Armbruster wrote:
[...]
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index a5840ff968..4674bd9163 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -859,30 +859,29 @@ static vo
From: Bernhard Beschow
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extractin
The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
move their definitions to cpregs.h. There's no need to have them
defined in all the code that includes cpu.h.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpregs.h | 28 +++
On 09/03/25 19:40, Cédric Le Goater wrote:
On 3/8/25 21:51, Aditya Gupta wrote:
Update skiboot.lid to below commit which adds support for booting on
Power11:
commit 785a5e3070a8 ("platform: Identify correct bmc platform
based on bmc hw version")
Built with glibc 2.40 and gcc 14.2 (Fedo
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/includ
On 3/10/25 08:25, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
Will allow to make system/memory.c common later.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
I guess this was split from p
From: Peter Maydell
R_NYXTL says that these AT insns should be UNDEFINED if they
would operate on an EL lower than EL3 and SCR_EL3.{NSE,NS} is
set to the Reserved {1, 0}. We were incorrectly reporting
them with the wrong syndrome; use CP_ACCESS_TRAP_UNCATEGORIZED
so they are reported as UNDEFINED
John Snow writes:
> Although "unstable" is a feature (and *will* appear in the features
> list), add a special :unstable: option to generate an eye-catch that
> makes this information very hard to miss.
>
> (The intent is to modify qapidoc.py to add this option whenever it
> detects that the feat
On Mon, Mar 10, 2025 at 07:50:57AM +0100, Thomas Huth wrote:
> On 09/03/2025 19.55, Pierrick Bouvier wrote:
> > On 6/3/24 05:18, Daniel P. Berrangé wrote:
> > > On Fri, May 31, 2024 at 06:47:45AM +0200, Thomas Huth wrote:
> > > > On 30/05/2024 09.45, Philippe Mathieu-Daudé wrote:
> > > > > We are t
We want to capture potential Rust backtraces on panics in our test
logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in
the add_test_setup environments, so that all our tests get run with
this environment variable set.
This makes the setting of that variable in the gitlab CI templa
Add a derive macro that makes it easy to peel off all the layers of
specialness (UnsafeCell, MaybeUninit, etc.) and just get a pointer
to the wrapped type; and likewise add them back starting from a
*mut.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst |
Dear QEMU Developers,
I would like to propose the development of a video subsystem in QEMU, with
the initial
implementation focusing on UVC video device emulation and support for
multiple
backends, including V4L2, GStreamer, and libcamera.
This work is already in progress at 9elements, and we wou
On Thu, Mar 6, 2025 at 4:33 PM Michael Tokarev wrote:
>
> 21.01.2025 20:06, Daniel Henrique Barboza wrote:
> > Hi,
> >
> > In this new version, in patch 2, we're using the address 'size' val from
> > riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN.
> >
> > No other changes made. Pat
As discussed in [1], this series modifies the SoC class be derived from
TYPE_SYS_BUS_DEVICE to fix the reset mechanism and to prevent it from being
user-creatable. It also removes an unused define.
v2:
* Do not set user_creatable = false; (Zoltan, Peter)
[1]
https://lore.kernel.org/qemu-devel/1c
On 3/5/25 22:41, Pierrick Bouvier wrote:
Work towards having a single binary, by removing duplicated object files.
hw/hyperv/hyperv.c was excluded at this time, because it depends on target
dependent symbols:
- from system/kvm.h
- kvm_check_extension
- kvm_vm_ioctl
- from exec/cpu-all.
On 10/03/2025 17.51, Alex Bennée wrote:
David Milosevic writes:
Dear QEMU Developers,
I would like to propose the development of a video subsystem in QEMU, with the
initial
implementation focusing on UVC video device emulation and support for multiple
backends, including V4L2, GStreamer, and
Hi David & Alexey,
To keep the bitmap aligned, I add the undo operation for
set_memory_attributes() and use the bitmap + replay callback to do
set_memory_attributes(). Does this change make sense?
Alexey, I didn't add your Reivewed-by since this patch introduced some
new changes.
On 3/10/2025 4:
On Thu, 6 Mar 2025, Pierrick Bouvier wrote:
On 3/6/25 07:28, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 02:45:52PM +0100, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzin
The MCD implementation follows a remote procedure call approach
and uses QMP as the communication protocol:
* mcdserver implements the MCD API
* mcd.json and mcdstub_qapi.c declare and implement the server stub
Our client stub supporting QMP can be found at:
https://gitlab.com/lauterbach/mcdrefsr
SR-IOV requires PCI Express.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 109b2ebcccba..a5b546abe8bb 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -42,6 +42,11 @@ bool
On 09/03/2025 19.55, Pierrick Bouvier wrote:
On 6/3/24 05:18, Daniel P. Berrangé wrote:
On Fri, May 31, 2024 at 06:47:45AM +0200, Thomas Huth wrote:
On 30/05/2024 09.45, Philippe Mathieu-Daudé wrote:
We are trying to unify all qemu-system-FOO to a single binary.
In order to do that we need to
Some files don't rely on any target-specific knowledge
and can be compiled once:
- helpers.c
- container-base.c
- migration.c (removing unnecessary "exec/ram_addr.h")
- migration-multifd.c
- cpr.c
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/migration.c | 1 -
hw/vfio/meson.build | 1
From: Peter Xu
The newly introduced device state buffer can be used for either storing
VFIO's read() raw data, but already also possible to store generic device
states. After noticing that device states may not easily provide a max
buffer size (also the fact that RAM MultiFDPages_t after all als
On 30/1/25 14:43, Cédric Le Goater wrote:
The Intel CPU has a complex history regarding setting of the physical
address space width on KVM. A 'phys_bits' field and a "phys-bits"
property were added by commit af45907a1328 ("target-i386: Allow
physical address bits to be set") to tune this value.
Allows them to be available for common compilation units.
Signed-off-by: Pierrick Bouvier
---
include/hw/hyperv/hyperv-proto.h | 12
target/i386/kvm/hyperv-proto.h | 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/include/hw/hyperv/hyperv-proto.h
The storage keys are part of the machine memory.
Introduce the TYPE_DUMP_SKEYS_INTERFACE type,
allowing machine using storage keys to dump them
when a DumpSKeysInterface::qmp_dump_skeys() callback
is provided.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/s390x/storage-keys.h | 15 ++
The functions arm_current_el() and arm_el_is_aa64() are used only in
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
query internal state of the CPU. Move them out of cpu.h and into
internals.h.
This means we need to include internals.h in arm_gicv3_cpuif.c, but
this is justi
On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> The NSR has a (so far unused) grouping level field. When a interrupt
> is presented, that field tells the hypervisor or OS if the interrupt
> is for an individual VP or for a VP-group/crowd. This patch reworks
>
cc: trivial
On 11/03/2025 14:27, Laurent Vivier wrote:
Add a chapter to explain how to use passt(1) instead of '-net user'.
passt(1) can be connected to QEMU using UNIX socket or vhost-user.
With vhost-user, migration of the VM is allowed and internal state of
passt(1) is transfered from one sid
On 3/9/25 00:09, Philippe Mathieu-Daudé wrote:
The file doesn't use any target-specific knowledge anymore,
move it to system_ss[] to build it once.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/vfio/meson.build | 5 +++--
1 file changed, 3 ins
Am 12.03.2025 um 15:37 hat Markus Armbruster geschrieben:
> bdrv_activate() returns failure without setting an error when
> !bs->drv. This is suspicious. Turns out it used to succeed then,
> until commit 5416645fcf82 changed it to return -ENOMEDIUM.
>
> Return zero instead.
>
> Fixes: 5416645fc
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/as
Add a unit test for pcf8563_rtc module
- Check default value after initialization
- Check set/get time
- Check minute alarm
- Check hour alarm
- Check day alarm
- Check wday alarm
- Check minute & hour alarm
- Check minute & day alarm
- Check day & wday alarm
- Check timer
---
v1->v2
Phil:
- Add h
On 3/9/25 21:58, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On Sat, Mar 15, 2025 at 5:01 PM Niek Linnenbank
wrote:
>
> Hello Stefan,
>
> As of today, it seems the URL is working properly again. I've done a few
> downloads without any error.
> What I did notice is that NetBSD provides a 'cdn.netbsd.org' also, but I
> can't see any noticable difference yet
On 3/9/25 12:08 AM, Philippe Mathieu-Daudé wrote:
> is already include by "system/kvm.h" in the next line.
included
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Pierrick Bouvier
> Reviewed-by: Richard Henderson
> Reviewed-by: Cédric Le Goater
> ---
> hw/vfio/spapr.c | 3 ---
>
On Fri, Mar 14, 2025 at 03:21:49PM +0100, Paolo Bonzini wrote:
> On 3/12/25 15:23, Daniel P. Berrangé wrote:
> > > > My question is, is this expected behavior or is this a bug?
> > >
> > > Your configure args don't include "--enable-debug", so I would
> > > not have expected -gsplit-dwarf to have
On Sun, Mar 9, 2025 at 5:03 PM Markus Armbruster wrote:
> John Snow writes:
>
> > This method adds the options/preamble to each definition block. Notably,
> > :since: and :ifcond: are added, as are any "special features" such as
> > :deprecated: and :unstable:.
> >
> > Signed-off-by: John Snow
On 2/17/25 12:49, Aditya Gupta wrote:
When MPIPL is used, OPAL/Linux registers memory regions to be preserved
on a Memory-Preserving boot ('crashkernel boot').
The regions are added to two tables: MDST and MDDT (source and
destination tables)
The MDST contains the start address of the region
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Remove #ifdef'ry since more work is required before
being able to emulate a user process.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250121142341.17001-3-phi.
On Sat, Mar 15, 2025 at 12:54:25PM +, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 14 Mar 2025 at 16:06, Tom Rini wrote:
> >
> > On Fri, Mar 14, 2025 at 02:44:35PM +, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Fri, 7 Mar 2025 at 14:23, Tom Rini wrote:
> > > >
> > > > On Thu, Mar 06, 202
Richard Henderson writes:
> We assert that env immediately follows CPUState in cpu-all.h.
> Change the offsetof expressions to be based on CPUState instead
> of ArchCPU.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Seems 'Asset' got missed in the documentation by mistake.
Also fix the one spellcheck issue pointed by spellcheck
Signed-off-by: Aditya Gupta
---
docs/devel/testing/functional.rst | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/docs/devel/testing/functional.rst
b/docs
On 3/9/25 21:58, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
This patch series introduces support for the Multi-Core Debug (MCD) API, a
commonly used debug interface by emulators. The MCD API, defined through a
header file, consists of 54 functions for implementing debug and trace.
However, since it is a header-file-only interface, MCD does not specify a
com
In preparation to make @dump-skeys command generic,
extract s390_qmp_dump_skeys() out of qmp_dump_skeys().
Register it as CCW qmp_dump_skeys() callback.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/s390x/storage-keys.h | 1 +
hw/s390x/s390-skeys.c | 7 ++-
hw/s390x/s390-vir
On 3/6/25 08:19, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/syndbg.c| 7 ---
hw/hyperv/meson.build | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/h
On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> If an END has the 'i' bit set (ignore), then it targets a group of
> VPs. The size of the group depends on the VP index of the target
> (first 0 found when looking at the least significant bits of the
> index) s
On 3/9/25 21:58, Pierrick Bouvier wrote:
diff --git a/page-vary-target.c b/page-vary-target.c
index 3f81144cda8..12fda410bb0 100644
--- a/page-vary-target.c
+++ b/page-vary-target.c
@@ -20,8 +20,9 @@
#define IN_PAGE_VARY 1
#include "qemu/osdep.h"
-#include "exec/page-vary.h"
#include "e
While cpu-exec.c is build for each target,tcg_flags helpers
aren't target specific. Move them to cpu-exec-common.c to
build them once.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-8-phi...@linaro.org>
---
accel/tcg/cpu-exec-common.c | 33
On 3/10/25 09:43, Pierrick Bouvier wrote:
On 3/10/25 09:37, Richard Henderson wrote:
On 3/10/25 09:14, Pierrick Bouvier wrote:
On 3/10/25 09:08, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
For now, they are duplicate of the same macros in cpu-all.h that we
eliminate in n
Steve Sistare writes:
> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
> in the migration stream file and recreate them later, because the physical
> memory for the blocks is pinned and registered for vfio. Add a blocker
> for volatile ram blocks.
>
> Also add a blocke
On 10/3/25 11:29, Peter Maydell wrote:
We want to capture potential Rust backtraces on panics in our test
logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in
the add_test_setup environments, so that all our tests get run with
this environment variable set.
This makes the setting
On 3/10/25 10:58, Richard Henderson wrote:
On 3/10/25 10:47, Pierrick Bouvier wrote:
Maybe better as
MemOp mop = (target_words_bigendian() ? MO_BE : MO_LE) |
size_memop(size);
adjust_endianness(mr, &mrfd.data, size_memop(size), mop);
Do you think defining MO_TE as this express
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-9.0) at that time.
This caused breakge in default cpu evaluation for older pseries
machines and hence this fix.
Fixes: 51113013f3 ("ppc/spapr: change pseries machine default to POWER10 CPU")
C
On Fri, 14 Mar 2025 at 08:15, Akihiko Odaki wrote:
>
> On 2025/03/14 3:34, Peter Maydell wrote:
> > On Thu, 13 Mar 2025 at 07:16, Akihiko Odaki
> > wrote:
> >>
> >> PMCNTENCLR_EL0 and PMINTENCLR_EL1 clears written bits so we need an
> >> alternative raw write functions, which will be used to cop
Hello Stefan,
As of today, it seems the URL is working properly again. I've done a few
downloads without any error.
What I did notice is that NetBSD provides a 'cdn.netbsd.org' also, but I
can't see any noticable difference yet.
Tests are also running OK now, at least on my local system:
$ QEMU_
Add "Return:" field list syntax to QAPI Commands.
Like "Arguments:" and "Errors:", the type name isn't currently processed
for cross-referencing, but this will be addressed in a forthcoming
commit.
The syntax of the new field is:
:return TypeName: description
description cont'd
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