Adding reviewer information to the patch and rebasing on top of master.
Previous versions:
- v1:
https://lore.kernel.org/all/20250129144435.82451-1-paolo.sav...@embecosm.com/
- v2:
https://lore.kernel.org/all/20250221155320.59159-1-paolo.sav...@embecosm.com/
Cc: Richard Handerson
Cc: Palmer D
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop that iterated over each element
so that when a fl
> -Original Message-
> From: Sid Manning
> Sent: Wednesday, March 12, 2025 2:10 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) ; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) ;
On 12/3/25 15:35, Markus Armbruster wrote:
Tracked down with scripts/coccinelle/err-bad-newline.cocci.
Signed-off-by: Markus Armbruster
---
net/vmnet-common.m | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Subsequently smmuv3-accel will provide these callbacks
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmu-common.c | 27 +++
> include/hw/arm/smmu-common.h | 5 +
> 2 files changed, 32 insertions(+)
>
> di
On Wed, Mar 12, 2025 at 04:34:18PM +, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
> > -Original Message-
> > From: Eric Auger
> > Sent: Wednesday, March 12, 2025 4:08 PM
> > To: Shameerali Kolothum Thodi
> > ; qemu-...@nongnu.org;
> > qemu-devel@nongnu.org
> > Cc: peter.mayd...@lina
On Wed, 12 Mar 2025 23:50:02 +0800
Tomita Moeko wrote:
> A previous change made the OpRegion and LPC quirks independent of the
> exising legacy mode, update the docoumentation accordingly. More related
> topics, like creating EFI Option ROM of IGD for OVMF, how to solve the
> VFIO_DMA_MAP Invalid
On 3/12/25 5:22 PM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: qemu-devel-
>> bounces+shameerali.kolothum.thodi=huawei@nongnu.org > devel-bounces+shameerali.kolothum.thodi=huawei@nongnu.org> On
>> Behalf Of Eric Auger
>> Sent: Wednesday, March 12, 2025 4:1
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Subsequent patches for smmuv3-accel will make use of this
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
Eric
> ---
> hw/arm/smmu-common.c | 48 ++--
> include/h
> -Original Message-
> From: qemu-devel-
> bounces+shameerali.kolothum.thodi=huawei@nongnu.org devel-bounces+shameerali.kolothum.thodi=huawei@nongnu.org> On
> Behalf Of Eric Auger
> Sent: Wednesday, March 12, 2025 4:13 PM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
>
If the server provides a Content-Length header, use that to verify the
size of the downloaded file. This catches cases where the connection
terminates early, and gives the opportunity to retry. Without this, the
checksum will likely mismatch and fail without retry.
Signed-off-by: Nicholas Piggin
> -Original Message-
> From: Eric Auger
> Sent: Wednesday, March 12, 2025 4:28 PM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; nath...@nvid
On Wed, Mar 12, 2025 at 02:47:16PM +, Peter Maydell wrote:
> On Wed, 12 Mar 2025 at 14:24, Daniel P. Berrangé wrote:
> >
> > On Wed, Mar 12, 2025 at 02:05:09PM +, Daniel P. Berrangé wrote:
> > > On Wed, Mar 12, 2025 at 03:52:45PM +0200, Konstantin Kostiuk wrote:
> > > > Hi All,
> > > >
> >
On Wed, Mar 12, 2025 at 06:05:43PM +, Jonathan Cameron wrote:
>
> Longer term I remain a little unconvinced by whether this is the best approach
> because I also want a single management path (so fake CCI etc) and that may
> need to be exposed to one of the hosts for tests purposes. In the cu
On 1/3/25 06:26, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 36a93cc22f..2b6a707fca 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/
The purpose of the prepare script is to invoke `cpp` to preprocess input
to idef-parser by expanding a few select macros. On mac osx `cpp`
expands into `clang ... -traditional-cpp` which breaks macro
concatenation. Replace `cpp` with `${compiler} -E`
and replace the script with a meson custom_tar
On Wed, 12 Mar 2025 19:27:14 + Sid Manning wrote:
>
> > From: Sid Manning
> > > From: ltaylorsimp...@gmail.com
> > > > From: Brian Cain
> > > >
> > > > +uint32_t hexagon_sreg_read(CPUHexagonState *env, uint32_t reg) {
> > > > +return sreg_read(env, reg);
> > > > +}
> > > > +
> > >
> > >
A default macOS build with xcode cli tools installed lacks the `indent`
program needed by the idef-parser postprocess step, remove this step.
Additionally `cpp` used by the idef-parser preprocess step expands into
`clang ... -traditional-cpp` and doesn't support macro concatenation
among other th
The indent command is not available on a default mac osx setup with
xcode cli tools installed. While it does make idef-parser generated
code nicer to debug, it's not crucial and can be dropped.
Signed-off-by: Anton Johansson
---
target/hexagon/meson.build | 21 ++---
1 file chan
On 12/03/2025 13.18, Philippe Mathieu-Daudé wrote:
Hi Thomas,
(patch merged as commit 4f7689f0817)
On 16/8/23 23:07, Thomas Huth wrote:
When starting a guest via libvirt with "virsh start --console ...",
the first second of the console output is missing. This is especially
annoying on s390x th
On Wed, Mar 12, 2025 at 10:25:58PM +1000, Nicholas Piggin wrote:
> Assets are uniquely identified by human-readable-ish url, so make an
> AssetError exception class that prints url with error message.
>
> A property 'transient' is used to capture whether the client may retry
> or try again later,
On Tue, 11 Mar 2025 at 15:37, Paolo Bonzini wrote:
>
> The guest does not control whether characters are sent on the UART.
> Sending them before the guest happens to boot will now result in a
> "guest error" log entry that is only because of timing, even if the
> guest _would_ later setup the rece
On Wed, Mar 12, 2025 at 12:06 AM Kevin Wolf wrote:
>
> The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
>
> Merge tag 'migration-20250310-pull-request' of
> https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07 +0800)
>
> are available in the Git reposito
On Tue, 11 Mar 2025 14:27:14 +0100
Laurent Vivier wrote:
> Add a chapter to explain how to use passt(1) instead of '-net user'.
> passt(1) can be connected to QEMU using UNIX socket or vhost-user.
> With vhost-user, migration of the VM is allowed and internal state of
> passt(1) is transfered fro
On Wed, 12 Mar 2025 at 13:36, Peter Maydell wrote:
>
> On Tue, 11 Mar 2025 at 15:37, Paolo Bonzini wrote:
> >
> > The guest does not control whether characters are sent on the UART.
> > Sending them before the guest happens to boot will now result in a
> > "guest error" log entry that is only bec
On 3/11/25 16:16, Rorie Reyes wrote:
Changelog:
v4:
- allocating cfg_chg_event before inserting into the queue
- calling nt0_have_event in if loop to check if there are any
elemenets in the queue, then calling QTAILQ_FIRST when the check
passes
- moving memset() after the check
v3:
- changes th
On 3/11/25 11:16 AM, Rorie Reyes wrote:
Creates an object indicating that an AP configuration change event
has been received and stores it in a queue. These objects will later
be used to store event information for an AP configuration change
when the CHSC instruction is intercepted.
Signed-o
On 3/12/25 03:38, Philippe Mathieu-Daudé wrote:
The x86 architecture is only implemented as little-endian.
The MO_TE definition always expands to MO_LE.
Replace:
- MO_TEUQ -> MO_LE | MO_UQ
- MO_TE -> MO_LE
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/tcg/emit.c.inc | 7 ---
Hi Shameer,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -Find an existing S2 hwpt to test attach() or allocate a new one
>(Devices behind the same physical SMMU should share an S2 HWPT.)
> -Attach the device to the S2 hwp
>
On 3/12/25 03:48, Philippe Mathieu-Daudé wrote:
We only build ARM system emulators using little
endianness, so the MO_TE definition always expands to
MO_LE, and DEVICE_TARGET_ENDIAN to DEVICE_LITTLE_ENDIAN.
Replace the definitions by their expanded value, making
it closer to the Armv7-M Architec
On 3/11/25 11:16 AM, Rorie Reyes wrote:
These functions can be invoked by the function that handles interception
of the CHSC SEI instruction for requests indicating the accessibility of
one or more adjunct processors has changed.
Signed-off-by: Rorie Reyes
Reviewed-by: Anthony Krowiak
Ping^3 ? Anybody home?
thanks
-- PMM
On Fri, 7 Mar 2025 at 10:38, Peter Maydell wrote:
>
> Ping^2 for pickup of reviewed patches.
>
> thanks
> -- PMM
>
> On Mon, 24 Feb 2025 at 14:47, Peter Maydell wrote:
> >
> > Ping? Would an i386 maintainer like to pick these up?
> >
> > thanks
> > -- PMM
>
Assets are uniquely identified by human-readable-ish url, so make an
AssetError exception class that prints url with error message.
A property 'transient' is used to capture whether the client may retry
or try again later, or if it is a serious and likely permanent error.
This is used to retain th
If the server provides a Content-Length header, use that to verify the
size of the downloaded file. This catches cases where the connection
terminates early, and gives the opportunity to retry. Without this, the
checksum will likely mismatch and fail without retry.
Signed-off-by: Nicholas Piggin
On Wed, Mar 12, 2025 at 10:25:56PM +1000, Nicholas Piggin wrote:
> Currently the fetch code does not fail gracefully when retry limit is
> exceeded, it just falls through the loop with no file, which ends up
> hitting other errors.
>
> Add a check for non-existing file, which indicates the retry l
On 12/03/2025 00.41, Nicholas Piggin wrote:
...
I think *no* precaching errors including 404 should cause
failure because you would still want other tests to proceed
(in some cases).
But the failure should be caught when the test case tries to
fetch the asset, so you can still easily identify th
On 3/12/25 16:10, Markus Armbruster wrote:
scripts/coccinelle/error-use-after-free.cocci led me to this function:
static void cryptodev_lkcf_execute_task(CryptoDevLKCFTask *task)
{
CryptoDevBackendLKCFSession *session = task->sess;
CryptoDevBackendAsymOpInfo *asym_
On 2025/3/12 18:03, Philippe Mathieu-Daudé wrote:
Hi Markus,
(Cc'ing Yi, Clément and Zhenzhong for commit eda4c9b5b3c)
On 12/3/25 10:45, Markus Armbruster wrote:
I stumbled over commits that carry the author's Reviewed-by.
There may be cases where the recorded author isn't the lone author, an
On Mon, 10 Mar 2025 at 20:36, Joe Komlodi wrote:
>
> On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
> an ISB to be executed during cache maintenance, which could lead to QEMU
> executing TBs containing garbage instructions.
>
> This seems to be because the ISB finishes ex
On 12/3/25 13:29, Thomas Huth wrote:
On 12/03/2025 13.18, Philippe Mathieu-Daudé wrote:
Hi Thomas,
(patch merged as commit 4f7689f0817)
On 16/8/23 23:07, Thomas Huth wrote:
When starting a guest via libvirt with "virsh start --console ...",
the first second of the console output is missing. T
scripts/coccinelle/error-use-after-free.cocci led me to this function:
static void cryptodev_lkcf_execute_task(CryptoDevLKCFTask *task)
{
CryptoDevBackendLKCFSession *session = task->sess;
CryptoDevBackendAsymOpInfo *asym_op_info;
bool kick = false;
int ret,
I can provide the full log, but I see on GitLab CI the same results
https://gitlab.com/qemu-project/qemu/-/jobs/9368756844
[3417/3430] Linking target tests/qtest/fuzz-e1000e-test.exe
/usr/lib/gcc/x86_64-w64-mingw32/14.1.1/../../../../x86_64-w64-mingw32/bin/ld:
tests/qtest/fuzz-e1000e-test.exe:/4:
On Tuesday, March 11, 2025 6:28:09 PM CET Greg Kurz wrote:
> Enhance the `use-after-unlink` test with a new check for the
> case where the client wants to alter the size of an unlinked
> file for which it still has an active fid.
>
> Suggested-by: Christian Schoenebeck
> Signed-off-by: Greg Kurz
On Wed, 12 Mar 2025 15:07:20 +0100
Christian Schoenebeck wrote:
> On Tuesday, March 11, 2025 6:28:06 PM CET Greg Kurz wrote:
> > Add an ftruncate operation to the fs driver and use if when a fid has
> > a valid file descriptor. This is required to support more cases where
> > the client wants to
On 12/3/25 13:52, Richard Henderson wrote:
On 3/12/25 03:38, Philippe Mathieu-Daudé wrote:
The x86 architecture is only implemented as little-endian.
The MO_TE definition always expands to MO_LE.
Replace:
- MO_TEUQ -> MO_LE | MO_UQ
- MO_TE -> MO_LE
Signed-off-by: Philippe Mathieu-Daudé
-
On Wed, 12 Mar 2025 at 13:36, Peter Maydell wrote:
>
> On Tue, 11 Mar 2025 at 15:37, Paolo Bonzini wrote:
> >
> > The guest does not control whether characters are sent on the UART.
> > Sending them before the guest happens to boot will now result in a
> > "guest error" log entry that is only bec
Hi Shameer,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Also introduce a struct SMMUv3AccelDevice to hold accelerator specific
> device info. This will be populated accordingly in subsequent patches.
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-accel.c | 36 +
When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.
The issue of CPU access to non-CPU address space via IOMMU was previously
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
this patch.
You can use a customized
The entire valid transaction must fit within a single IOPMP entry.
However, during IOMMU translation, the transaction size is not
available. This structure defines the transaction information required
by the IOPMP.
Signed-off-by: Ethan Chen
---
include/hw/misc/riscv_iopmp_txn_info.h | 38 +++
> -Original Message-
> From: Daniel P. Berrangé
> Sent: Wednesday, March 12, 2025 4:39 PM
> To: Shameerali Kolothum Thodi
> Cc: eric.au...@redhat.com; qemu-...@nongnu.org; qemu-
> de...@nongnu.org; peter.mayd...@linaro.org; j...@nvidia.com;
> nicol...@nvidia.com; ddut...@redhat.com; nat
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Subsequently smmuv3-accel will provide these callbacks
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmu-common.c | 27 +++
> include/hw/arm/smmu-common.h | 5 +
> 2 files changed, 32 insertions(+)
>
> di
** Changed in: qemu (Ubuntu Noble)
Status: Triaged => In Progress
** Changed in: qemu (Ubuntu Noble)
Assignee: (unassigned) => Lukas Märdian (slyon)
** Changed in: qemu (Ubuntu Oracular)
Assignee: (unassigned) => Lukas Märdian (slyon)
** Changed in: qemu (Ubuntu Oracular)
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Am 12. März 2025 11:13:01 UTC schrieb Peter Maydell :
>On Wed, 12 Mar 2025 at 10:44, Cédric Le Goater wrote:
>>
>> On 3/12/25 11:27, Philippe Mathieu-Daudé wrote:
>> > + Cédric for Aspeed
>> >
>> > On 12/3/25 11:20, Peter Maydell wrote:
>> >> The bug is that this is directly inheriting from TYP
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 3/12/25 5:34 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Wednesday, March 12, 2025 4:08 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; n
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
A previous change made the OpRegion and LPC quirks independent of the
exising legacy mode, update the docoumentation accordingly. More related
topics, like creating EFI Option ROM of IGD for OVMF, how to solve the
VFIO_DMA_MAP Invalid Argument warning, as well as details on IGD memory
internals, ar
Ping.
Michael/Marcel, would you mind taking a look? Thanks!
Jason
Daniel Henrique Barboza 於 2025年3月7日 週五 下午8:40寫道：
>
>
> On 3/2/25 6:12 AM, Jason Chien wrote:
> > This commit adds the BDF to the memory attributes for DMA operations.
> >
> > Signed-off-by: Jason Chien
> > ---
>
> This looks s
Hi Eric,
> -Original Message-
> From: Eric Auger
> Sent: Wednesday, March 12, 2025 4:08 PM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; nath
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On Wed, 12 Mar 2025 12:04:49 -0500 wrote:
>
> > -Original Message-
> > From: Brian Cain
> >
> > +void hex_mmu_realize(CPUHexagonState *env) {
> > +CPUState *cs = env_cpu(env);
> > +if (cs->cpu_index == 0) {
> > +env->hex_tlb = g_malloc0(sizeof(CPUHexagonTLBContext));
> > +
On Wed, 5 Mar 2025 18:35:40 +0800
Yuquan Wang wrote:
> >
> > On Tue, 4 Mar 2025 14:22:48 +0800
> > Yuquan Wang wrote:
> >
> > > >
> > > > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > > > > On Mon, 17 Feb 2025 19:20:39 +0800
> > > > > Yuquan Wang wrote:
> > > >
On Mon, 10 Mar 2025 16:02:45 +0800
Junjie Fu wrote:
> > Note though that there is a long way to go before we can do what you
> > want. The steps I'd expect to see along the way:
> >
> > 1) Emulate an Multi Headed Device.
> >Initially connect two heads to different host bridges on a single QE
> +/*
> + * If KVM_CAP_PMU_CAPABILITY is not supported, there is no way to
> + * disable the AMD pmu virtualization.
> + *
> + * If KVM_CAP_PMU_CAPABILITY is supported !cpu->enable_pmu
> + * indicates the KVM has already disabled the PMU virtual
zhenwei pi writes:
> On 3/12/25 16:10, Markus Armbruster wrote:
>> scripts/coccinelle/error-use-after-free.cocci led me to this function:
>>
>> static void cryptodev_lkcf_execute_task(CryptoDevLKCFTask *task)
>> {
>> CryptoDevBackendLKCFSession *session = task->sess;
>> Cr
Hi Markus,
(Cc'ing Yi, Clément and Zhenzhong for commit eda4c9b5b3c)
On 12/3/25 10:45, Markus Armbruster wrote:
I stumbled over commits that carry the author's Reviewed-by.
There may be cases where the recorded author isn't the lone author, and
the recorded author did some meaningful review of
On 12/3/25 10:40, Thomas Huth wrote:
On 25/02/2025 19.04, Peter Maydell wrote:
From: Bernhard Beschow
As a first step, implement the bare minimum: CPUs, RAM, interrupt
controller,
serial. All other devices of the A53 memory map are represented as
TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole mem
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; Matheus Bernardino (QUIC)
> ; a...@rev.ng; a...@rev.ng; Marco Liebel
> (QUIC) ; ltaylorsimp
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 12, 2025 2:20 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; Matheus Bernardino (QUIC)
> ; a...@rev.ng; a...@rev.ng; Marco Liebel
> (QUIC) ; ltaylorsimp...@gmail.com;
> alex.ben.
Ah, It is a pity and bad news that I contribute almost 30% of it :(
LoongArch system actually needs more people participation and I need
notice this also. It should happens in future again in LoongArch subsystem.
Any reviewing comments is welcome and I will slow down for deeper
considerations.
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt
Add namespaces, turn on QGA and QSD.
John Snow (11):
docs/qapi_domain: isolate TYPE_CHECKING imports
docs/qapi-domain: always store fully qualified name in signode
docs/qapi_domain: add namespace support to FQN
docs/qapi-domain: add :namespace: override option
docs/qapi-domain: add qapi:
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
---
hw/arm/aspeed_ast27x0.c | 28 ++--
1 f
On 13/03/2025 03.22, Stefan Hajnoczi wrote:
Hi,
CI jobs that run test_arm_orangepi.py are failing:
https://gitlab.com/qemu-project/qemu/-/jobs/9390048284#L1138
Please consider how to resolve this so the CI job passes again. If you
are in contact with the archive.netbsd.org administrators, maybe
On 13/03/2025 03.34, Stefan Hajnoczi wrote:
On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin wrote:
The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
Merge tag 'migration-20250310-pull-request' of
https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07
bibo mao writes:
> Ah, It is a pity and bad news that I contribute almost 30% of it :(
> LoongArch system actually needs more people participation and I need notice
> this also. It should happens in future again in LoongArch subsystem.
>
> Any reviewing comments is welcome and I will slow down f
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add su
Maps following unimplemented devices in SoC memory
- dpmcu
- iomem
- iomem0
- iomem1
- ltpi
Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
memory ranges 0x0 - 0x100, 0x12000 - 0x12100 and
0x1400 - 0x14100.
For instance:
- USB hub at 0x1201
- eSPI at 0x14
For the s390x target, it's possible to build the QEMU binary without
CONFIG_VIRTIO_PCI and only have the virtio-mem device via the ccw
transport. In that case, QEMU currently fails to link correctly:
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_d
John Snow writes:
> Akin to the :module: override option, the :namespace: options allows you
> to forcibly override the contextual namespace associatied with a
> definition.
>
> We don't necessarily actually need this, but I felt compelled to stick
> close to how the Python domain works that offe
On 12/03/2025 13:54, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 2025/3/12 18:03, Philippe Mathieu-Daudé wrote:
>> Hi Markus,
>>
>> (Cc'ing Yi, Clément and Zhenzhong fo
John Snow writes:
> This patch does three things:
>
> 1. Record the current namespace context in pending_xrefs so it can be
>used for link resolution later,
> 2. Pass that recorded namespace context to find_obj() when resolving a
>reference, and
> 3. Wildly and completely rewrite find_obj
I'm proposing to add a feature to offload virtio-net RSS/hash report to
Linux. This series contain patches to utilize the proposed Linux feature.
The patches for Linux are available at:
https://lore.kernel.org/r/20250307-rss-v9-0-df7662402...@daynix.com/
This work was presented at LPC 2024:
https:
John Snow writes:
> This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
>
> Signed-off-by: John Snow
[...]
> diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
> index 995594aaf43..35ec0e7db31 100644
> --- a/qga/qapi-schema.json
> +++ b/qga/qapi-schema.json
> @@ -3,6
DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO()
as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference
is that DEFINE_PROP_ON_OFF_AUTO_BIT64() exposes OnOffAuto instead of
bool.
Signed-off-by: Akihiko Odaki
---
include/hw/qdev-properties.h | 18
It is no longer used.
Signed-off-by: Akihiko Odaki
---
net/vhost-vdpa.c | 8
1 file changed, 8 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 0e9f4482ce7a..d35348b1e742 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -238,12 +238,6 @@ static void vhost_vdpa
This is necessary to offload hashing to tap.
Signed-off-by: Akihiko Odaki
---
hw/net/virtio-net.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index e125478ae834..edfc76a5308e 100644
--- a/hw/net/virtio-net.c
++
This allows offloading virtio-net hashing to tap on Linux.
Signed-off-by: Akihiko Odaki
---
net/tap-linux.h | 1 +
net/tap_int.h | 1 +
net/tap-bsd.c | 5 +
net/tap-linux.c | 13 +
net/tap-solaris.c | 5 +
net/tap-stub.c| 5 +
net/tap.c | 8 +
This adds set_vnet_hash() to configure virtio hashing and implements it
for Linux's tap. vDPA will have an empty function as configuring virtio
hashing is done with the load().
Signed-off-by: Akihiko Odaki
---
include/net/net.h | 17 +
net/tap-linux.h | 1 +
net/tap_int.h
Report hashing capability so that virtio-net can deliver the correct
capability information to the guest.
Signed-off-by: Akihiko Odaki
---
include/net/net.h | 3 +++
net/net.c | 9 +
net/vhost-vdpa.c | 28
3 files changed, 40 insertions(+)
diff --
This is necessary to offload hashing to tap.
Signed-off-by: Akihiko Odaki
---
hw/net/virtio-net.c | 77 -
1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index b0f2ad78cb39..e125478ae834
The implementation of cpu_mmu_index was split between
cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY.
Unify within a new header and include only where needed.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 6 --
include/exec/cpu-common.h | 20 ---
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of this.
Remove exec/tswap.h from translator.c.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 49 +
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/net/i82596.h | 2 +-
hw/s390x/ipl.h| 2 +-
include/hw/misc/lasi.h| 2 +-
include/hw/nubus/nubus.h | 2 +-
include/hw/ppc/vof.
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered that we have already added files to
common_ss which indirectly depend on CONFIG_USER_ONLY. Sometimes
this is harmless, and sometimes it re
We assert that env immediately follows CPUState in cpu-all.h.
Change the offsetof expressions to be based on CPUState instead
of ArchCPU.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 13 +
accel/tcg/meson.build | 7 ---
2 files changed, 9 insertions(+), 11 dele
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 57 ++-
2 files changed,
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