Fixes: ca056f4499c2 (Python: Drop support for Python 3.7)
Signed-off-by: Markus Armbruster
---
docs/about/build-platforms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst
index 482b09819c..1552b1a704 100644
---
On Thu Feb 27, 2025 at 11:48 AM AEST, BALATON Zoltan wrote:
> On Thu, 27 Feb 2025, Nicholas Piggin wrote:
>> On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
>>> The board has a battery backed NVRAM where U-Boot environment is
>>> stored which is also accessed by AmigaOS and e.g. C:NVGetV
We use OrderedDict to ensure dictionary order is insertion order.
Plain dict does that since Python 3.6, but it wasn't guaranteed until
3.7. Since we have 3.7 now, replace OrderedDict by dict.
Signed-off-by: Markus Armbruster
---
scripts/qapi/parser.py | 5 ++---
scripts/qapi/schema.py
On 2/25/25 10:52 PM, Alex Williamson wrote:
> The memory and IO BARs for devices are only accessible in the D0 power
> state. In other power states the PCI spec defines that the device
> responds to TLPs and messages with an Unsupported Request response.
>
> To approximate this behavior, consi
On 2/25/25 10:52 PM, Alex Williamson wrote:
> Switch callers directly initializing the PCI PM capability with
> pci_add_capability() to use pci_pm_init().
>
> Cc: Dmitry Fleytman
> Cc: Akihiko Odaki
> Cc: Jason Wang
> Cc: Stefan Weil
> Cc: Sriram Yagnaraman
> Cc: Keith Busch
> Cc: Klaus J
Hi Cédric,
On 2/26/25 9:47 AM, Cédric Le Goater wrote:
> VFIO Platforms was designed for Aarch64. Restrict availability to
> 64-bit host platforms.
>
> Cc: Eric Auger
> Signed-off-by: Cédric Le Goater
Reviewed-by: Eric Auger
As an outcome from last KVM forum, next step may be to simply remove
Hello Tomita,
+Corvin
On 2/24/25 19:29, Tomita Moeko wrote:
This patchset removes some legacy checks and converts the legacy mode
implicitly enabled by BDF 00:02.0 into x-igd-* options, including:
* Removing PCI ROM BAR and VGA IO/MMIO range check before applying quirk
* Using unified x-igd-opr
The QAPI code generator code still contains a few minor oddities to
make it work with versions of Python we no longer support. Bury them.
I'm leaving two things for later because I don't know what to do about
them:
* scripts/qapi/source.py has a "Replace with @dataclass in Python
3.7+" comment
A TODO comment in class Annotated reminds us to simplify it once we
can use @dataclass, new in Python 3.7. We have that now, so do it.
There's a similar comment in scripts/qapi/source.py, but I can't
figure out how to use @dataclass there. Left for another day.
Signed-off-by: Markus Armbruster
On Thu Feb 27, 2025 at 4:49 PM AEST, Aditya Gupta wrote:
> Hi Nick,
>
> On 27/02/25 08:37, Nicholas Piggin wrote:
>> On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
>>> Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU.
>>>
>>> Currently the handler just does basic ch
On 26/2/25 22:52, Richard Henderson wrote:
On 2/26/25 13:51, Philippe Mathieu-Daudé wrote:
On 22/2/25 18:41, Richard Henderson wrote:
On 2/20/25 14:17, Philippe Mathieu-Daudé wrote:
@@ -1794,23 +1715,19 @@ void tcg_gen_andi_i64(TCGv_i64 ret,
TCGv_i64 arg1, int64_t arg2)
case -1:
On Thu Feb 27, 2025 at 5:07 PM AEST, Aditya Gupta wrote:
> On 27/02/25 09:03, Nicholas Piggin wrote:
>
>> On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
>>> With all support in place, enable fadump by exporting the
>>> "ibm,configure-kernel-dump" RTAS call in the device tree.
>>>
>>> Pres
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 20 ++--
tcg/aarch64/tcg-target.c.inc | 18 +++---
tcg/arm/tcg-target.c.inc | 14 ++
tcg/i386/tcg-target.c.inc| 16 +
PropertyInfo member @type is externally visible via QMP
device-list-properties and qom-list-properies.
Its meaning is not documented at its definition.
It gets passed to as @type argument to object_property_add() and
object_class_property_add(). This argument's documentation isn't of
much help,
QOM properties could use similar work. Left for another day.
v2: Rebased
Markus Armbruster (6):
qdev: Delete unused qdev_prop_enum
qdev: Change qdev_prop_pci_devfn member @name from "int32" to "str"
qdev: Rename PropertyInfo member @name to @type
qdev: Change values of PropertyInfo membe
Consistently use format "DESCRIPTION (VALUE/VALUE...)".
Signed-off-by: Markus Armbruster
---
hw/core/qdev-properties-system.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index
Signed-off-by: Markus Armbruster
---
hw/block/xen-block.c | 2 +-
hw/core/qdev-properties-system.c | 2 +-
hw/core/qdev-properties.c| 1 +
hw/s390x/ccw-device.c| 4 ++--
target/sparc/cpu.c | 1 +
5 files changed, 6 insertions(+), 4 deletions(-)
diff
PropertyInfo member @name becomes ObjectProperty member @type, while
Property member @name becomes ObjectProperty member @name. Rename the
former.
Signed-off-by: Markus Armbruster
---
include/hw/qdev-properties.h | 2 +-
backends/tpm/tpm_util.c | 2 +-
hw/block/xen-block.c
On Thu Feb 27, 2025 at 12:18 PM AEST, BALATON Zoltan wrote:
> On Thu, 27 Feb 2025, Nicholas Piggin wrote:
>> On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
>>> Initialise empty NVRAM with default values. This also enables IDE UDMA
>>> mode in AmigaOS that is faster but has to be enabled
Signed-off-by: Markus Armbruster
---
include/hw/qdev-properties.h | 1 -
hw/core/qdev-properties.c| 7 ---
2 files changed, 8 deletions(-)
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index bf27375a3c..ae6ec2b990 100644
--- a/include/hw/qdev-properties.h
+++ b
Properties using qdev_prop_pci_devfn initially accepted a string of
the form "DEV.FN" or "DEV" where DEV and FN are in hexadecimal.
Member @name was "pci-devfn" initially.
Commit b403298adb5 (qdev: make the non-legacy pci address property
accept an integer) changed them to additionally accept inte
On Thu, Feb 20, 2025 at 09:02:14AM +0100, Philippe Mathieu-Daudé wrote:
> Introduce a helper to get the default shared library
> suffix used on the host.
>
> Suggested-by: Pierrick Bouvier
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Pierrick Bouvier
> ---
> tests/functional/qemu_tes
On Wed, Feb 26, 2025 at 02:03:25PM +, Alex Bennée wrote:
> From: Philippe Mathieu-Daudé
>
> Not all platforms use the '.so' suffix for shared libraries,
> which is how plugins are built. Use the recently introduced
> dso_suffix() helper to get the proper host suffix.
>
> Resolves: https://gi
On Thu, Feb 27, 2025 at 09:07:55AM +0100, Markus Armbruster wrote:
> Fixes: ca056f4499c2 (Python: Drop support for Python 3.7)
> Signed-off-by: Markus Armbruster
> ---
> docs/about/build-platforms.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Daniel P. Berrangé
With
On Wed Feb 26, 2025 at 5:38 AM AEST, Richard Henderson wrote:
> On 2/25/25 11:33, Richard Henderson wrote:
>> On 2/25/25 10:46, Alex Bennée wrote:
>>> @@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error
>>> **errp)
>>> cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIR
On Thu, Feb 27, 2025 at 09:07:57AM +0100, Markus Armbruster wrote:
> A TODO comment in class Annotated reminds us to simplify it once we
> can use @dataclass, new in Python 3.7. We have that now, so do it.
>
> There's a similar comment in scripts/qapi/source.py, but I can't
> figure out how to us
On Thu, Feb 27, 2025 at 09:07:56AM +0100, Markus Armbruster wrote:
> We use OrderedDict to ensure dictionary order is insertion order.
> Plain dict does that since Python 3.6, but it wasn't guaranteed until
> 3.7. Since we have 3.7 now, replace OrderedDict by dict.
>
> Signed-off-by: Markus Armbr
Hello, thank you for taking the time to review the patch,
and tell us what we could improve.
The values passed to qdev_get_gpio_in(DEVICE(&s->gic), ...)
should be GIC_SPI_INTERRUPT_* values, which we define in
include/hw/arm/bcm2838_peripherals.h. You can add new ones for
the four timers.
Hm,
Daniel P. Berrangé writes:
> On Thu, Feb 27, 2025 at 09:56:01AM +0100, Markus Armbruster wrote:
>> Signed-off-by: Markus Armbruster
>> ---
>> hw/block/xen-block.c | 2 +-
>> hw/core/qdev-properties-system.c | 2 +-
>> hw/core/qdev-properties.c| 1 +
>> hw/s390x/ccw-device.c
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported, by
using:
$ ghes_inject.py arm
which produces those warnings on Linux:
[ 705.0
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
Em Thu, 27 Feb 2025 10:54:54 +0100
Igor Mammedov escreveu:
> On Fri, 21 Feb 2025 15:35:09 +0100
> Mauro Carvalho Chehab wrote:
>
> > Now that the ghes preparation patches were merged, let's add support
> > for error injection.
> >
> > On this series, the first 6 patches chang to the math used
The current code is actually dependent on having just one error
structure with a single source, as any change there would cause
migration issues.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, and how many errors can be
reported at th
Now that HEST table is checked for aarch64, add the current
firmware file.
Signed-off-by: Mauro Carvalho Chehab
---
tests/data/acpi/aarch64/virt/HEST | Bin 0 -> 132 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/
Move the check logic into a common function and simplify the
code which checks if GHES is enabled and was properly setup.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes-stub.c| 7 ---
hw/acpi/ghes.c | 38
While the HEST layout didn't change, there are some internal
changes related to how offsets are calculated and how memory error
events are triggered.
Update specs to reflect such changes.
Signed-off-by: Mauro Carvalho Chehab
---
docs/specs/acpi_hest_ghes.rst | 28 +---
1
Instead of having a function to check if ACPI is enabled
(acpi_ghes_present), change its logic to be more generic,
returing a pointed to AcpiGhesState.
Such change allows cleanup the ghes GED state code, avoiding
to read it multiple times, and simplifying the code.
Signed-off-by: Mauro Carvalho C
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 20 +++-
include/hw/acpi/ghes.h | 7 ++-
2 files changed
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
Now that we have everything in place, enable using HEST GPA
instead of etc/hardware_errors GPA.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_devic
Such file will be used to track HEST table changes.
For now, disallow HEST table check until we update it to the
current data.
Signed-off-by: Mauro Carvalho Chehab
---
tests/data/acpi/aarch64/virt/HEST | 0
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
2 files changed, 1 insertio
Currently, aarch64 can generate a HEST table when loaded with
-machine ras=on. Add support for it.
Signed-off-by: Mauro Carvalho Chehab
---
tests/qtest/bios-tables-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-
--- /tmp/asl-38PE22.dsl 2025-02-26 16:25:32.362148388 +0100
+++ /tmp/asl-HSPE22.dsl 2025-02-26 16:25:32.361148402 +0100
@@ -1,39 +1,39 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Dis
The test checks some entries in /proc and the output of some commands ...
we put these checks into exportable functions now so that they can
be re-used more easily.
Additionally the linux_ssh_mips_malta.py uses SSH to test the networking
of the guest. Since we don't have a SSH module in the functi
Re-use the test function from the 32-bit big endian test to easily
convert the 64-bit big endian Wheezy mips test.
Since this was the last test in tests/avocado/linux_ssh_mips_malta.py,
we can remove this avocado file now, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS
Re-use the test function from the 32-bit big endian test to easily
convert the 64-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build| 1 +
tests/functional/test_mips64el_malta.py | 22
We are going to use this code in other tests, too, so let's move it
to the qemu_test module to be able to re-use it more easily.
Signed-off-by: Thomas Huth
---
tests/functional/qemu_test/linuxkernel.py | 26 ++-
tests/functional/test_intel_iommu.py | 22 +
Re-use the test function from the big endian test to easily
convert the 32-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build | 1 +
tests/functional/test_mipsel_malta.py | 22
Convert the linux_ssh_mips_malta.py avocado test to the functional
framework. Since this test was exercising the network via ssh, and
we don't have the ssh commands in the functional framework, we
rather run the commands via the serial console now and use a HTTP
download for testing whether the net
The kernel has a driver for the pcnet NIC included, and the initrd has
a "tftp" command, so we can test a simple network transfer here, too.
Signed-off-by: Thomas Huth
---
tests/functional/test_mips_malta.py | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a
在2025年2月25日二月 下午12:33，bibo mao写道：
> On 2025/2/25 下午8:08, Jiaxun Yang wrote:
>>
>>
>> 在2025年2月25日二月 上午8:50，bibo mao写道：
>>> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still many
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the read ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error blo
--- /tmp/asl-L7J912.dsl 2025-02-26 16:22:26.539657960 +0100
+++ /tmp/asl-T9N912.dsl 2025-02-26 16:22:26.536658001 +0100
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Dis
We'll be adding a new GED device for HEST GPIO notification and
increasing the number of entries at the HEST table.
Blocklist testing HEST and DSDT tables until such changes
are completed.
Signed-off-by: Mauro Carvalho Chehab
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file ch
Add a new ags flag to change the way HEST offsets are calculated.
Currently, offsets needed to store ACPI HEST offsets and read ack
are calculated based on a previous knowledge from the logic
which creates the HEST table.
Such logic is not generic, not allowing to easily add more HEST
entries nor
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
Now that the ghes preparation patches were merged, let's add support
for error injection.
On this version, HEST table got added to ACPI tables testing for aarch64 virt.
There are also some patch reorder to help reviewers to check the changes.
The code itself is almost identical to v4, with just
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 5 -
include/hw/acpi/ghes.h | 3 +++
2 files
Em Thu, 27 Feb 2025 12:03:40 +0100
Mauro Carvalho Chehab escreveu:
> Instead of having a function to check if ACPI is enabled
> (acpi_ghes_present), change its logic to be more generic,
> returing a pointed to AcpiGhesState.
>
> Such change allows cleanup the ghes GED state code, avoiding
> to r
On Thu, 27 Feb 2025 12:03:31 +0100
Mauro Carvalho Chehab wrote:
> Such file will be used to track HEST table changes.
>
> For now, disallow HEST table check until we update it to the
> current data.
>
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
> ---
> tests/data/acpi/aa
On 26.02.25 22:00, Matthew Rosato wrote:
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin the entirety of
guest memory into the host iommu.
Pinning
On Thu, 27 Feb 2025 12:03:33 +0100
Mauro Carvalho Chehab wrote:
> Now that HEST table is checked for aarch64, add the current
> firmware file.
>
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
> ---
> tests/data/acpi/aarch64/virt/HEST | Bin 0 -> 132 bytes
> tests/q
On Thu, 27 Feb 2025 12:03:32 +0100
Mauro Carvalho Chehab wrote:
> Currently, aarch64 can generate a HEST table when loaded with
> -machine ras=on. Add support for it.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test.c | 2 +-
> 1 file
On 27/02/25 14:18, Nicholas Piggin wrote:
On Thu Feb 27, 2025 at 4:49 PM AEST, Aditya Gupta wrote:
Hi Nick,
On 27/02/25 08:37, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
<...snip...>
Ah, that is problematic agreed. I tried to move around things, but
arrive
Thomas Huth writes:
> These tests are based on the cloudinit functions from Avocado.
> The cloudinit is very, very slow compared to our other tests,
> so most of these Avocado tests have either been disabled by default
> with a decorator, or have been marked to only run with KVM.
I have no objec
On Thu, 27 Feb 2025 12:45:38 +0100
Mauro Carvalho Chehab wrote:
> Em Wed, 26 Feb 2025 15:37:14 +0100
> Igor Mammedov escreveu:
>
> > On Fri, 21 Feb 2025 15:35:10 +0100
> > Mauro Carvalho Chehab wrote:
> >
>
> > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > > index
On 2025/2/27 下午6:44, Jiaxun Yang wrote:
在2025年2月25日二月 下午12:33，bibo mao写道：
On 2025/2/25 下午8:08, Jiaxun Yang wrote:
在2025年2月25日二月 上午8:50，bibo mao写道：
On 2025/2/25 上午8:40, Jiaxun Yang wrote:
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still
Em Wed, 26 Feb 2025 15:37:14 +0100
Igor Mammedov escreveu:
> On Fri, 21 Feb 2025 15:35:10 +0100
> Mauro Carvalho Chehab wrote:
>
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index 3ac8f8e17861..8ab8d11b6536 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests/
From: Clement Mathieu--Drif
We add a convenient way to initialize an device-iotlb notifier.
This is meant to be used by ATS-capable devices.
pci_device_iommu_memory_region_pasid is introduces in this commit and
will be used in several other SVM-related functions exposed in
the PCI API.
Signed-o
From: Clement Mathieu--Drif
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added (define
From: Clement Mathieu--Drif
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files
From: Clement Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed-of
From: Clement Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
We decided not to use the existing translation operation for 2 reasons.
First, ATS is d
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 74 --
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
From: Clement Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 24
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pci
From: Clement Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index eee625a9c6..4d240cad1c 100644
--- a/inclu
From: Clement Mathieu--Drif
The region returned by this operation will be used as the input region
for ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/hw/pci/pci.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 4002
From: Clement Mathieu--Drif
As the SVM-capable devices will need to cache translations, we provide
an first implementation.
This cache uses a two-level design based on hash tables.
The first level is indexed by a PASID and the second by a virtual addresse.
Signed-off-by: Clement Mathieu--Drif
From: Clement Mathieu--Drif
PASID value must be used by devices as a key (or part of a key)
when populating their ATC with the IOTLB entries returned by the IOMMU.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/inte
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 17 -
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a360119fbe..d3772
From: Clement Mathieu--Drif
This patch set belongs to a list of series that add SVM support for VT-d.
Here we focus on implementing ATS support in the IOMMU and adding a
PCI-level API to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is
From: Clement Mathieu--Drif
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5.
This is needed by devices that support ATS.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/i38
From: Clement Mathieu--Drif
The cached is_master value is necessary to know if a device is
allowed to issue ATS requests or not.
This behavior is implemented in an upcoming patch.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c| 25 +++--
include/hw/pc
From: Clement Mathieu--Drif
PSS field of the ecap register stores the supported PASID size minus 1.
Thus, this commit adds support for 20bits PASIDs.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2 inserti
From: Clement Mathieu--Drif
This will be useful for devices that support ATS
and need to store entries in an ATC (device IOTLB).
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
inde
From: Clement Mathieu--Drif
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2 fil
These tests are based on the cloudinit functions from Avocado.
The cloudinit is very, very slow compared to our other tests,
so most of these Avocado tests have either been disabled by default
with a decorator, or have been marked to only run with KVM.
We won't include this sluggish cloudinit stuf
On Thu, 27 Feb 2025 at 10:20, Paolo Bonzini wrote:
>
> On 2/27/25 11:07, Joel Granados wrote:
> > Here is the error I see:
> > cmd:
> >meson introspect --buildoptions /home/joel/src/qemu/meson.build
> >
> > output:
> >meson.build:88:12: ERROR: Unknown compiler(s): [['rustc']]
> >The fo
On 27.02.25 04:26, Chenyi Qiang wrote:
On 2/26/2025 8:43 PM, Chenyi Qiang wrote:
On 2/25/2025 5:41 PM, David Hildenbrand wrote:
On 25.02.25 03:00, Chenyi Qiang wrote:
On 2/21/2025 6:04 PM, Chenyi Qiang wrote:
On 2/21/2025 4:09 PM, David Hildenbrand wrote:
On 21.02.25 03:25, Chenyi Qi
在2025年2月27日二月 下午12:21，bibo mao写道：
[...]
int pin.
>>> Thanks for the information, Would you like to emulate LoongArch32
>>> chiplap FPGA board in qemu side or other LoongArch32 boards?
>>
>> My plan is to use current virt machine (with EXTIOI and so on) for
>> Loon
chardev is using qio functions, so express that in the Meson internal
dependency. (I found this when adding character devices bindings for
Rust; they initially needed the io dependency added by hand).
Signed-off-by: Paolo Bonzini
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Thu, Feb 27, 2025 at 01:50:03PM +0100, Paolo Bonzini wrote:
> chardev is using qio functions, so express that in the Meson internal
> dependency. (I found this when adding character devices bindings for
> Rust; they initially needed the io dependency added by hand).
>
> Signed-off-by: Paolo Bo
On Thu, 27 Feb 2025 12:03:47 +0100
Mauro Carvalho Chehab wrote:
squash this patch into the next one
Also at this point there is no visible HEST changes yet, so a soon as you remove
white-list without enabling new HEST, the tests should start failing.
I suggest to move 20/21 before this patch,
a
On Thu, 27 Feb 2025 14:10:38 +0100
Igor Mammedov wrote:
> On Thu, 27 Feb 2025 12:03:47 +0100
> Mauro Carvalho Chehab wrote:
>
> squash this patch into the next one
>
> Also at this point there is no visible HEST changes yet, so a soon as you
> remove
> white-list without enabling new HEST, th
Ping for this patch:
https://patchew.org/QEMU/cabnabob99xzcbwswyqkkjt3amwzodazmtmm6ab7utvz._5fun._5f...@mail.gmail.com/
Though not used by recent(__FreeBSD_version >= 120) base libc,
this syscall is used by concurrent (like the newest v4.0.2)
cosmopolitan libc. Wrong emulation leads to things
On Thu, 27 Feb 2025 12:03:49 +0100
Mauro Carvalho Chehab wrote:
> While the HEST layout didn't change, there are some internal
> changes related to how offsets are calculated and how memory error
> events are triggered.
>
> Update specs to reflect such changes.
>
> Signed-off-by: Mauro Carvalho
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