Hi Patrick,
On Thu, 2025-02-27 at 15:42 +, Patrick Venture wrote:
> eth_hdr requires 2 byte alignment
>
> Signed-off-by: Patrick Venture
> ---
> hw/net/ftgmac100.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac10
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH rfcv2 02/20] vfio/iommufd: Add properties and handlers to
>TYPE_HOST_IOMMU_DEVICE_IOMMUFD
>
>Hi Zhenzhong,
>
>
>On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> New added properties include IOMMUFD handle, devid and hwpt_id.
On Wed, Jan 22, 2025 at 6:49 PM Ethan Chen via wrote:
>
> The entire valid transaction must fit within a single IOPMP entry.
> However, during IOMMU translation, the transaction size is not
> available. This structure defines the transaction information required
> by the IOPMP.
>
> Signed-off-by:
On Wed, Jan 22, 2025 at 6:48 PM Ethan Chen via wrote:
>
> This device determines the target IOPMP device for forwarding information
> based on:
> * Address: For parallel IOPMP devices
> * Stage: For cascading IOPMP devices
>
> Signed-off-by: Ethan Chen
> ---
> hw/misc/meson.build
On Wed, Jan 22, 2025 at 6:49 PM Ethan Chen via wrote:
>
> - Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
> to protect all regions of system memory.
>
> Signed-off-by: Ethan Chen
> ---
> docs/system/riscv/virt.rst | 7
> hw/riscv/Kconfig | 1 +
> hw
On Mon, Feb 24, 2025 at 12:58 PM Yong-Xuan Wang
wrote:
>
> Reorder the code to reduce the conditional checking and remove
> unnecessary resource setting when using in-kernl AIA irqchip.
>
> ---
> v2:
> - remove the code reordering of the riscv-virt machine since it can't
> work with NUMA setting
On Wed, Jan 22, 2025 at 6:48 PM Ethan Chen via wrote:
>
> Support IOPMP specification v0.9.2RC3.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.2-RC3
>
> The IOPMP checks whether memory access from a device or CPU is valid.
> This implementation uses an IO
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Signed-off-by: Sebastian Huber
Acked-by: Alistair Francis
Alistair
> ---
> hw/misc/mchp_pfsoc_sysreg.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
> index
On Tue, Jan 28, 2025 at 4:29 AM Andrea Bolognani wrote:
>
> Until now, the script has worked under the assumption that a
> host CPU can run binaries targeting any CPU in the same family.
> That's a fair enough assumption when it comes to running i386
> binaries on x86_64, but it doesn't quite appl
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and not as the guest is
being prepared for launch.
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit
address in the table. There is LoongArch system support from ACPI
Specification 6.4 and later, XSDT is supported by LoongArch system.
Here replace RSDT with XSDT table.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt-acpi-buil
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and not as the guest is
being prepared for launch.
On 2/27/2025 7:27 PM, David Hildenbrand wrote:
> On 27.02.25 04:26, Chenyi Qiang wrote:
>>
>>
>> On 2/26/2025 8:43 PM, Chenyi Qiang wrote:
>>>
>>>
>>> On 2/25/2025 5:41 PM, David Hildenbrand wrote:
On 25.02.25 03:00, Chenyi Qiang wrote:
>
>
> On 2/21/2025 6:04 PM, Chenyi Qiang w
On Thu, 27 Feb 2025 at 16:48, Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/hw/char/pl011/src/device.rs| 7 +-
> rust/hw/char/pl011/src/lib.rs | 509 +---
> rust/hw/char/pl011/src/registers.rs | 507 +++
> 3 files c
On Wed, Feb 26, 2025 at 09:55:18AM +0100, Thomas Huth wrote:
> > > Though, that does not look like the thread from the simpletrace, but
> > > the the QEMU RCU thread instead ... so no clue where that writer
> > > thread might have gone...
> >
> > OK, I think I now understood the problem: qemu-nbd
Convert some printf() calls for attempts to access nonexistent
registers into LOG_GUEST_ERROR logging.
Signed-off-by: Peter Maydell
---
hw/arm/versatilepb.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 941616cd25b..3
On Tue, 25 Feb 2025 02:29:17 +0800
Tomita Moeko wrote:
> This patchset removes some legacy checks and converts the legacy mode
> implicitly enabled by BDF 00:02.0 into x-igd-* options, including:
> * Removing PCI ROM BAR and VGA IO/MMIO range check before applying quirk
> * Using unified x-igd-op
On 26.02.2025 18:46, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
---
hw
On 27.02.2025 07:48, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Allow capping the maximum count of in-flight VFIO device state buffers
queued at the destination, otherwise a malicious QEMU source could
theoretically cause the target QEMU to
On 26.02.2025 18:28, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
---
hw
Hello,
v2:
- change unused read function to g_assert_not_reached()
- new patch to add defines to constants
- added R-b tags
This series adds NVRAM and support for -kernel, -initrd and -append
options to the amigaone machine. This makes it easier to boot AmigaOS
and avoids a crash in the guest whe
Again really sorry, missed this due to some issue with my mail filters
and came to know about it via qemu-devel weblink. :)
On 25/02/25 2:37 pm, Daniel P. Berrangé wrote:
!---|
CAUTION: External Email
|-
I noticed while looking at the sx1 functional tests that
the omap1 device emulation code prints to stdout
"omap_clkm_write: clocking scheme set to synchronous scalable"
which the test dutifully captures to its default.log.
Printing this kind of debug or information message to stdout
is definitely
Remove an ifdeffed out debug printf from the static_write() function in
omap_sx1.c. In theory we could turn this into a tracepoint, but for
code this old it doesn't seem worthwhile. We can add tracepoints if
and when we have a reason to debug something.
Signed-off-by: Peter Maydell
---
hw/arm/om
On Thu, 27 Feb 2025, Nicholas Piggin wrote:
On Thu Feb 27, 2025 at 12:18 PM AEST, BALATON Zoltan wrote:
On Thu, 27 Feb 2025, Nicholas Piggin wrote:
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
Initialise empty NVRAM with default values. This also enables IDE UDMA
mode in AmigaOS
On 2/27/2025 3:29 PM, Roy Hopkins wrote:
IGVM support has been implemented for Confidential Guests that support
AMD SEV and AMD SEV-ES. Add some documentation that gives some
background on the IGVM format and how to use it to configure a
confidential guest.
Signed-off-by: Roy Hopkins
Reviewed-b
In omap1.c, there are some debug printfs in the omap_rtc_write()
function that are guardad by ifdef ALMDEBUG. ALMDEBUG is never
set, so this is all dead code.
It's not worth the effort of converting all of these to tracepoints;
a modern tracepoint approach would probably have a single tracepoint
c
On Fri, 2025-01-24 at 08:20 -0500, Xiaoyao Li wrote:
> KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow
> for
> KVM_SET_LAPIC[*].
>
> Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the
> path
>
> do_kvm_cpu_synchronize_state()
> -> kvm_arch_get_registers()
>
On 2/27/25 06:13, Peter Maydell wrote:
GCC versions at least 12 through 15 incorrectly report a warning
about code in sha1.c:
tests/tcg/multiarch/sha1.c:161:13: warning: ‘SHA1Transform’ reading 64 bytes
from a region of size 0 [-Wstringop-overread]
161 | SHA1Transform(context->st
omap1.c is very old code, and it contains numerous calls direct to
printf() for various error and information cases.
In this commit, convert the printf() calls that are for either guest
error or unimplemented functionality to qemu_log_mask() calls.
This leaves the printf() calls that are informat
The omap1 code uses raw printf() statements to print information
about some events; convert these to tracepoints.
In particular, this will stop the functional test for the sx1
from printing the not-very-helpful note
"omap_clkm_write: clocking scheme set to synchronous scalable"
to the test's defa
On 2/27/2025 3:29 PM, Roy Hopkins wrote:
When an SEV guest is started, the reset vector and state are
extracted from metadata that is contained in the firmware volume.
In preparation for using IGVM to setup the initial CPU state,
the code has been refactored to populate vmcb_save_area for each
C
On Thu, 27 Feb 2025 at 16:48, Paolo Bonzini wrote:
>
> Switch bindings::CharBackend with chardev::CharBackend. This removes
> occurrences of "unsafe" due to FFI and switches the wrappers for receive,
> can_receive and event callbacks to the common ones implemented by
> chardev::CharBackend.
>
> S
This allows access to errno values.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/Cargo.lock | 7
rust/qemu-api/Cargo.toml | 1 +
scripts/archive-source.sh | 2 +-
scripts/make-release
On Thu, 27 Feb 2025 09:32:46 +0100
Eric Auger wrote:
> Hi Cédric,
>
> On 2/26/25 9:47 AM, Cédric Le Goater wrote:
> > VFIO Platforms was designed for Aarch64. Restrict availability to
> > 64-bit host platforms.
> >
> > Cc: Eric Auger
> > Signed-off-by: Cédric Le Goater
> Reviewed-by: Eric Au
Generalize timer_and_addr() to decode all registers into a single enum
HPETRegister, and use the TryInto derive to separate valid and
invalid values.
The main advantage lies in checking that all registers are enumerated
in the "match" statements.
Signed-off-by: Paolo Bonzini
---
rust/Cargo.toml
On 2/27/25 06:27, Peter Maydell wrote:
Our STRD implementation doesn't correctly implement the requirement:
* if the address is 8-aligned the access must be a 64-bit
single-copy atomic access, not two 32-bit accesses
Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
of a v
On 2/27/25 06:27, Peter Maydell wrote:
All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
zero for the address_offset, so we can remove that argument.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate.c | 26 +-
1 file changed, 13 insertions
On Wed, 26 Feb 2025 14:58:46 +1000
Gavin Shan wrote:
> On 2/25/25 9:19 PM, Igor Mammedov wrote:
> > On Fri, 21 Feb 2025 11:04:35 +
> > Jonathan Cameron wrote:
> >>
> >> Ideally I'd like whatever we choose to look like what a bare metal machine
> >> does - mostly because we are less likely
On Wed, Jan 22, 2025 at 6:49 PM Ethan Chen via wrote:
>
> The entire valid transaction must fit within a single IOPMP entry.
> However, during IOMMU translation, the transaction size is not
> available. This structure defines the transaction information required
> by the IOPMP.
>
> Signed-off-by:
Use a similar terminology smmu_hash_remove_by_sid_range() as the one
being used for other hash table matching functions since
smmuv3_invalidate_ste() name is not self explanatory, and introduce a
helper that invokes the g_hash_table_foreach_remove.
No functional change intended.
Signed-off-by: Ji
On Tue, Jan 28, 2025 at 4:29 AM Andrea Bolognani wrote:
>
> Changes from [v1]:
>
> * adopt a completely different, more general approach.
>
> [v1] https://mail.gnu.org/archive/html/qemu-devel/2024-12/msg00459.html
>
> Andrea Bolognani (3):
> binfmt: Shuffle things around
> binfmt: Normalize
On 27-02-2025 07:26, Nicholas Piggin wrote:
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
There is a possibility that SPI controller can get into loop due to indefinite
RDR match failures. Hence put a limit to failures and stop the sequencer.
Signed-off-by: Chalapathi V
---
hw/ss
This commit adds failback routine for `virtio_pci_realize` to
fix the memory leak of an address space and the virtio-net device object.
If the realization of the device failed, the address space should be
destroyed too.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2845
Signed-off-by:
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH rfcv2 01/20] backends/iommufd: Add helpers for invalidating
>user-managed HWPT
>
>Hi Zhenzhong,
>
>
>On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> Signed-off-by: Nicolin Chen
>> Signed-off-by: Zhenzhong Duan
>in the titl
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and not as the guest is
being prepared for launch.
Hello Nick,
Thank You for reviewing this series.
On 27-02-2025 07:09, Nicholas Piggin wrote:
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
In PnvXferBuffer dynamically allocating and freeing is a
process overhead. Hence used an existing Fifo8 buffer with
capacity of 16 bytes.
Signed
On 27-02-2025 07:24, Nicholas Piggin wrote:
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
Create a spi buses with distict names on each socket so that responders
are attached to correct SPI controllers.
QOM tree on a 2 socket machine:
(qemu) info qom-tree
/machine (powernv10-machine)
On 2/28/25 04:03, Chalapathi V wrote:
On 27-02-2025 07:24, Nicholas Piggin wrote:
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
Create a spi buses with distict names on each socket so that responders
are attached to correct SPI controllers.
QOM tree on a 2 socket machine:
(qemu) inf
On Thu, Feb 27, 2025 at 8:08 AM Patrick Venture wrote:
>
>
> On Thu, Feb 27, 2025 at 8:01 AM Peter Maydell
> wrote:
>
>> On Thu, 27 Feb 2025 at 15:55, Patrick Venture wrote:
>> >
>> >
>> >
>> > On Thu, Feb 27, 2025 at 7:52 AM Peter Maydell
>> wrote:
>> >>
>> >> On Thu, 27 Feb 2025 at 15:40, Pa
On 2/27/2025 00:33, Michael Tokarev wrote:
25.02.2025 15:39, Konstantin Shkolnyy wrote:
On 2/25/2025 03:30, Michael Tokarev wrote:
This looks like a qemu-stable material.
Please let me know if it is not.
It won't help without my other "[PATCH v2] vdpa: Allow vDPA to work on
big-endian mach
This bug was fixed in the package qemu - 1:9.2.1+ds-1ubuntu3
---
qemu (1:9.2.1+ds-1ubuntu3) plucky; urgency=medium
* Fix qemu-aarch64-static segfaults running ldconfig.real (LP: #2072564)
- lp-2072564-elfload-Fix-alignment-when-unmapping-excess-reservat.patch
Thanks to Dimit
On Thu, 27 Feb 2025 at 18:12, Patrick Venture wrote:
>
>
>
> On Thu, Feb 27, 2025 at 8:08 AM Patrick Venture wrote:
>>
>>
>>
>> On Thu, Feb 27, 2025 at 8:01 AM Peter Maydell
>> wrote:
>>>
>>> On Thu, 27 Feb 2025 at 15:55, Patrick Venture wrote:
>>> >
>>> >
>>> >
>>> > On Thu, Feb 27, 2025 at 7
At least the simple trace backend works by spawning a helper thread,
and setting up an atexit() handler that coordinates completion with
the helper thread. But since atexit registrations survive fork() but
helper threads do not, this means that qemu-nbd configured to use the
simple trace will dead
On Thu, Feb 27, 2025 at 10:30:31PM +0530, Manish wrote:
> Again really sorry, missed this due to some issue with my mail filters and
> came to know about it via qemu-devel weblink. :)
>
> On 25/02/25 2:37 pm, Daniel P. Berrangé wrote:
> > !--
On Thu, 27 Feb 2025 at 17:41, Richard Henderson
wrote:
>
> On 2/27/25 06:27, Peter Maydell wrote:
> > +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
> > +{
> > +/*
> > + * LDRD is required to be an atomic 64-bit access if the
> > + * address is 8-aligned, tw
On Thu, Feb 27, 2025 at 6:25 PM Peter Maydell wrote:
> On Thu, 27 Feb 2025 at 16:48, Paolo Bonzini wrote:
> > Switch bindings::CharBackend with chardev::CharBackend. This removes
> > occurrences of "unsafe" due to FFI and switches the wrappers for receive,
> > can_receive and event callbacks to
From: Nabih Estefan
Dump sys.stdin when it errors on meson-buildoptions.py, letting us debug
the build errors instead of just saying "Couldn't parse"
Signed-off-by: Nabih Estefan
Signed-off-by: Patrick Venture
---
scripts/meson-buildoptions.py | 10 --
1 file changed, 8 insertions(+),
On 2/27/25 06:27, Peter Maydell wrote:
Our LDRD implementation is wrong in two respects:
* if the address is 4-aligned and the load crosses a page boundary
and the second load faults and the first load was to the
base register (as in cases like "ldrd r2, r3, [r2]", then we
must not
On 2/27/25 09:01, Peter Maydell wrote:
Peter Maydell (5):
hw/arm/omap1: Convert raw printfs to qemu_log_mask()
hw/arm/omap1: Drop ALMDEBUG ifdeffed out code
hw/arm/omap1: Convert information printfs to tracepoints
hw/arm/omap_sx1.c: Remove ifdeffed out debug printf
hw/arm/versatile
On 27.02.2025 07:59, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Update the VFIO documentation at docs/devel/migration describing the
changes brought by the multifd device state transfer.
Signed-off-by: Maciej S. Szmigiero
---
docs/devel
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 24 +++--
tcg/aarch64/tcg-target.c.inc | 4 +++
tcg/arm/tcg-target.c.inc | 4 +++
tcg/i386/tcg-target.c.inc| 17
tcg/loongarch64
On 2/27/25 18:28, Peter Maydell wrote:
On Thu, 27 Feb 2025 at 16:48, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs| 7 +-
rust/hw/char/pl011/src/lib.rs | 509 +---
rust/hw/char/pl011/src/registers.rs | 507 ++
On 2/27/25 18:28, Peter Maydell wrote:
On Thu, 27 Feb 2025 at 16:48, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs| 7 +-
rust/hw/char/pl011/src/lib.rs | 509 +---
rust/hw/char/pl011/src/registers.rs | 507 ++
On 27/02/25 11:26 pm, Peter Xu wrote:
!---|
CAUTION: External Email
|---!
On Thu, Feb 27, 2025 at 10:30:31PM +0530, Manish wrote:
Again really sorry, missed this
On Thu, 27 Feb 2025 at 18:02, Paolo Bonzini wrote:
>
> On Thu, Feb 27, 2025 at 6:25 PM Peter Maydell
> wrote:
> > Thinking about other devices, presumably for more complex
> > devices we might need to pass more than just a single 'bool'
> > back from PL011Registers::write. What other kinds of th
On 2/27/25 09:58, Peter Maydell wrote:
On Thu, 27 Feb 2025 at 17:41, Richard Henderson
wrote:
On 2/27/25 06:27, Peter Maydell wrote:
+static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+/*
+ * LDRD is required to be an atomic 64-bit access if the
+ * addr
On 27/2/25 18:01, Peter Maydell wrote:
In omap1.c, there are some debug printfs in the omap_rtc_write()
function that are guardad by ifdef ALMDEBUG. ALMDEBUG is never
set, so this is all dead code.
It's not worth the effort of converting all of these to tracepoints;
a modern tracepoint approach
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 6 ++-
tcg/aarch64/tcg-target.c.inc | 18 ---
tcg/arm/tcg-target.c.inc | 23
tcg/i386/tcg-target.c.inc| 47 +---
tcg/loongarch64/
On 27/2/25 18:01, Peter Maydell wrote:
The omap1 code uses raw printf() statements to print information
about some events; convert these to tracepoints.
In particular, this will stop the functional test for the sx1
from printing the not-very-helpful note
"omap_clkm_write: clocking scheme set t
On 27/2/25 18:01, Peter Maydell wrote:
Convert some printf() calls for attempts to access nonexistent
registers into LOG_GUEST_ERROR logging.
Signed-off-by: Peter Maydell
---
hw/arm/versatilepb.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Dau
On 27/2/25 15:27, Peter Maydell wrote:
All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
zero for the address_offset, so we can remove that argument.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate.c | 26 +-
1 file changed, 13 insertion
Peter Maydell writes:
> GCC versions at least 12 through 15 incorrectly report a warning
> about code in sha1.c:
>
> tests/tcg/multiarch/sha1.c:161:13: warning: ‘SHA1Transform’ reading 64 bytes
> from a region of size 0 [-Wstringop-overread]
> 161 | SHA1Transform(context->state, &d
On 27/2/25 18:01, Peter Maydell wrote:
omap1.c is very old code, and it contains numerous calls direct to
printf() for various error and information cases.
In this commit, convert the printf() calls that are for either guest
error or unimplemented functionality to qemu_log_mask() calls.
This le
On Wed, Feb 19, 2025 at 04:23:26PM +0530, prashant patil wrote:
> Hello All,
> Hope this email finds you well.
>
> I have been trying with qemu for a while now, and have come across a
> problem specific to dirty bitmaps. I have enabled bitmap on the qcow2 disk
> image using 'qemu-img bitmap' comma
On Wed, Feb 26, 2025 at 09:50:15AM +0100, Thomas Huth wrote:
> When compiling QEMU with --enable-trace-backends=simple , the
> iotest 233 is currently hanging. This happens because qemu-nbd
> calls trace_init_backends() first - which causes simpletrace to
> install its writer thread and the atexit(
On Tue, Feb 25, 2025 at 08:06:50AM +0100, Thomas Huth wrote:
> Test 162 recently started failing for me for no obvious reasons (I
> did not spot any suspicious commits in this area), but looking in
> the 162.out.bad log file, there was a suspicious message at the end:
>
> qemu-nbd: Cannot lock pi
On Wed, Jan 22, 2025 at 6:39 PM Ethan Chen via wrote:
>
> Allow memory regions to have different behaviors for read and fetch
> operations.
>
> For example, the RISC-V IOPMP could raise an interrupt when the CPU
> tries to fetch from a non-executable region.
>
> If the fetch operation for a memory
From: Klaus Jensen
The specification states that,
> The controller shall set all three processing limit fields (i.e., the
> DMRL, DMRSL and DMSL fields) to non-zero values or shall clear all
> three processing limit fields to 0h.
So, set the DMRL and DMSL fields in addition to DMRSL.
Reviewed-
/birkelund/qemu.git tags/pull-nvme-20250227
for you to fetch changes up to cad58ada8f104bf342097a7a683ef594ac949c8d:
hw/nvme: remove nvme_aio_err() (2025-02-26 12:40:35 +0100)
From: Klaus Jensen
Virtualization Management needs sriov-related parameters. Only report
support for the command when that conditions are true.
Reviewed-by: Jesper Wendel Devantier
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 25 ++---
hw/nvme/nvme.h | 4 +
On Thu, Feb 27, 2025 at 09:56:01AM +0100, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> hw/block/xen-block.c | 2 +-
> hw/core/qdev-properties-system.c | 2 +-
> hw/core/qdev-properties.c| 1 +
> hw/s390x/ccw-device.c| 4 ++--
> target/sparc/c
From: Klaus Jensen
The status codes related to I/O Command Sets are in the wrong group.
Reviewed-by: Jesper Wendel Devantier
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 4 ++--
include/block/nvme.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/nvme/ctr
Hello Jamin,
On 2/26/25 07:38, Jamin Lin wrote:
Hi Cedric,
On 2/13/25 04:35, Jamin Lin wrote:
According to the design of the AST2600, it has a Silicon Revision ID
Register, specifically SCU004 and SCU014, to set the Revision ID for the
AST2600.
For the AST2600 A3, SCU004 is set to 0x050303
From: Klaus Jensen
The Command Abort Requested status code should only be set if the
command was explicitly cancelled due to an Abort command. Or, in the
case the cancel was due to Submission Queue deletion, set the status
code to Command Aborted due to SQ Deletion.
Reviewed-by: Jesper Wendel De
From: Klaus Jensen
nvme_rw_complete_cb() is the only remaining user of nvme_aio_err(), so
open code the status code setting instead.
Reviewed-by: Jesper Wendel Devantier
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 60 +++---
1 file changed, 23
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h| 2 --
On Thu, Feb 27, 2025 at 09:55:56AM +0100, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> include/hw/qdev-properties.h | 1 -
> hw/core/qdev-properties.c| 7 ---
> 2 files changed, 8 deletions(-)
Reviewed-by: Daniel P. Berrangé
With regards,
Daniel
--
|: https://b
On Thu, Feb 27, 2025 at 09:55:59AM +0100, Markus Armbruster wrote:
> PropertyInfo member @type is externally visible via QMP
> device-list-properties and qom-list-properies.
>
> Its meaning is not documented at its definition.
>
> It gets passed to as @type argument to object_property_add() and
On Thu, Feb 27, 2025 at 09:56:00AM +0100, Markus Armbruster wrote:
> Consistently use format "DESCRIPTION (VALUE/VALUE...)".
>
> Signed-off-by: Markus Armbruster
> ---
> hw/core/qdev-properties-system.c | 26 +++---
> 1 file changed, 11 insertions(+), 15 deletions(-)
Reviewe
From: Stephen Bates
The Open Compute Project [1] includes a Datacenter NVMe
SSD Specification [2]. The most recent version of this specification
(as of November 2024) is 2.6.1. This specification layers on top of
the NVM Express specifications [3] to provide additional
functionality. A key part o
Hi,
On 2/21/25 4:10 AM, JianChunfu wrote:
> SMMUTransCfg->ttb is never used in QEMU, TT base address
> can be accessed by SMMUTransCfg->tt[i]->ttb.
>
> Signed-off-by: JianChunfu
Reviewed-by: Eric Auger
Thanks!
Eric
> ---
> include/hw/arm/smmu-common.h | 1 -
> 1 file changed, 1 deletion(-)
>
>
From: Klaus Jensen
Add a 'dbcs' knob to allow Doorbell Buffer Config command to be
disabled.
Reviewed-by: Jesper Wendel Devantier
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 11 ---
hw/nvme/nvme.h | 1 +
include/block/nvme.h | 2 +-
3 files changed, 10 insertions(+)
On Thu, Feb 27, 2025 at 09:55:57AM +0100, Markus Armbruster wrote:
> Properties using qdev_prop_pci_devfn initially accepted a string of
> the form "DEV.FN" or "DEV" where DEV and FN are in hexadecimal.
> Member @name was "pci-devfn" initially.
>
> Commit b403298adb5 (qdev: make the non-legacy pci
On Wed, 26 Feb 2025 17:14:06 +0100
Mauro Carvalho Chehab wrote:
> Em Tue, 25 Feb 2025 10:43:27 +0100
> Igor Mammedov escreveu:
>
> > On Fri, 21 Feb 2025 07:02:21 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Em Mon, 3 Feb 2025 15:34:23 +0100
> > > Igor Mammedov escreveu:
> > >
> >
On Thu, Feb 27, 2025 at 09:55:58AM +0100, Markus Armbruster wrote:
> PropertyInfo member @name becomes ObjectProperty member @type, while
> Property member @name becomes ObjectProperty member @name. Rename the
> former.
>
> Signed-off-by: Markus Armbruster
> ---
> include/hw/qdev-properties.h
From: Klaus Jensen
If no nvme-subsys is explicitly configured, instantiate one.
Reviewed-by: Jesper Wendel Devantier
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 36 +++-
hw/nvme/ns.c | 64 +-
2 files changed, 42 in
From: Klaus Jensen
The controller incorrectly allows a zoned namespace to be attached even
if CS.CSS is configured to only support the NVM command set for I/O
queues.
Rework handling of namespace command sets in general by attaching
supported namespaces when the controller is started instead of,
From: Klaus Jensen
The nvme_aio_err() does not handle Verify, Compare, Copy and other misc
commands and defaults to setting the error status code to Internal
Device Error. For some of these commands, we know better, so set it
explicitly.
For the commands using the nvme_misc_cb() callback (Copy,
On Thu, 27 Feb 2025 08:26:38 +0100
Mauro Carvalho Chehab wrote:
> Em Thu, 27 Feb 2025 08:19:27 +0100
> Mauro Carvalho Chehab escreveu:
>
> > Em Wed, 26 Feb 2025 16:52:26 +0100
> > Igor Mammedov escreveu:
> >
> > > On Fri, 21 Feb 2025 15:35:17 +0100
> > > Mauro Carvalho Chehab wrote:
> > >
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