On 2/25/25 03:08, Alex Bennée wrote:
There is very little in loader that is different between builds save
for a tiny user/system mode difference in the plugin_info structure.
Create two new files, user and system to hold mode specific helpers
and move loader into common_ss.
Signed-off-by: Alex B
We deprecate versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the deprecated.rst document that always
has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 7 +++
docs/conf.py | 33 +++
On 25/02/2025 21.04, Daniel P. Berrangé wrote:
We remove versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the removed-features.rst document that
always has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/removed-features.rst |
We remove versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the removed-features.rst document that
always has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/removed-features.rst | 10 ++
docs/conf.py|
On 2/25/25 10:46, Alex Bennée wrote:
From: Igor Mammedov
that will enable assert_cpu_is_self when QEMU is configured with
--enable-debug
without need for manual patching DEBUG_TLB_GATE define.
Need to manually path DEBUG_TLB_GATE define to enable assert,
let regression caused by [1] creep
On 25/02/2025 21.04, Daniel P. Berrangé wrote:
If we change the deprecation logic in include/hw/boards.h, we must make
a corresponding change to docs/conf.py and docs/about/deprecated.rst.
Add comments to these files as a warning to future maintainers to keep
these files in sync.
Signed-off-by:
On 25/2/25 20:20, Richard Henderson wrote:
On 2/25/25 10:17, Philippe Mathieu-Daudé wrote:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-
target.c.inc
index a0f050ff9c..08106b6e4c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
+sta
On 25/2/25 20:25, Richard Henderson wrote:
On 2/25/25 10:40, Philippe Mathieu-Daudé wrote:
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1115d1e38d..01010dfdc0 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
+static void tgen_andi(TCGContext
On 25/02/2025 08.06, Thomas Huth wrote:
Test 162 recently started failing for me for no obvious reasons (I
did not spot any suspicious commits in this area), but looking in
the 162.out.bad log file, there was a suspicious message at the end:
qemu-nbd: Cannot lock pid file: Resource temporarily
On 25/02/2025 21.04, Daniel P. Berrangé wrote:
We deprecate versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the deprecated.rst document that always
has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 7 +
Functions to serialize and de-serialize EFI signature databases. This
is needed to merge signature databases (happens in practice when
appending dbx updates) and also to extract the certificates for
pkcs7 signature verification.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-siglist.c | 2
This is the core code for guest <-> host communication. This accepts
request messages from the guest, dispatches them to the service called,
and sends back the response message.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-core.c | 321 +
1 file chang
Allow the device being added to x86_64 pc and q35 VMs.
Signed-off-by: Gerd Hoffmann
---
hw/i386/pc_piix.c | 2 ++
hw/i386/pc_q35.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 04d2957adcd7..6c91e2d29298 100644
--- a/hw/i386/pc_piix.c
+++ b/h
Add utility functions. Helpers for UEFI (ucs2) string handling.
Helpers for readable trace messages. Compare UEFI time stamps.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-utils.c | 241
1 file changed, 241 insertions(+)
create mode 100644 hw/uefi/
This file defines the register interface of the uefi-vars device.
It's only a handful of registers: magic value, command and status
registers, location and size of the communication buffer.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Laszlo Ersek
---
include/hw/uefi/var-service-api.h | 48 +++
On Tue, 25 Feb 2025 12:42:24 +
Alex Bennée wrote:
> Igor Mammedov writes:
>
> > 1)
> > This reverts commit 30933c4fb4f3df95ae44c4c3c86a5df049852c01.
> > ("tcg/cputlb: remove other-cpu capability from TLB flushing")
> >
> > The commit caused a regression which went unnoticed due to
> > aff
On 25/02/2025 18.44, Thomas Huth wrote:
On 25/02/2025 11.12, Kevin Wolf wrote:
Am 25.02.2025 um 08:20 hat Thomas Huth geschrieben:
Hi!
I'm facing a weird hang in iotest 233 on my Fedora 41 laptop. When running
./check -raw 233
the test simply hangs. Looking at the log, the last message
On 25/02/2025 11.12, Kevin Wolf wrote:
Am 25.02.2025 um 08:20 hat Thomas Huth geschrieben:
Hi!
I'm facing a weird hang in iotest 233 on my Fedora 41 laptop. When running
./check -raw 233
the test simply hangs. Looking at the log, the last message is "== check
plain client to TLS server f
On Wed, Feb 19, 2025 at 09:33:49PM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> All callers to migration_incoming_state_destroy() other than
> postcopy_ram_listen_thread() do this call with BQL held.
>
> Since migration_incoming_state_destroy() ultimately calls "load_clean
On 2/21/25 12:53 PM, Paolo Savini wrote:
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop tha
On 2/21/25 1:20 PM, Paolo Savini wrote:
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface t
Hi hikalium,
This commit actually breaks one of our use cases with Ubuntu host when the
display scaling factor is
set to 200%. It seems like gtk_widget_get_scale_factor is only way to get that
DPI scaling factor
and without this, mouse movement on the guest wouldn't be able to go across
certain
On 2/25/25 11:33, Richard Henderson wrote:
On 2/25/25 10:46, Alex Bennée wrote:
@@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
hppa_cpu_alarm_timer, cpu);
On 2/25/25 10:46, Alex Bennée wrote:
The commit 30933c4fb4 (tcg/cputlb: remove other-cpu capability from
TLB flushing) introduced a regression that only shows up when
--enable-debug-tcg is used. The main use case of tlb_flush outside of
the current_cpu context is for handling reset and CPU creati
Since we deprecate and remove versioned machine types on a fixed
schedule, we can automatically ensure that the docs reflect the
latest version info, rather than requiring manual updates on each
dev cycle.
The first patch in this series fixes the logic to ensure dev snapshots
and release candidate
When VERSION is set to a development snapshot (micro >= 50), or a release
candidate (micro >= 90) we have an off-by-1 in determining deprecation
and deletion thresholds for versioned machine types. In such cases we need
to use the next major/minor version in threshold checks.
This adapts the depre
On 2/25/25 12:02, Richard Henderson wrote:
Not checked here are any of the other reasons a flush might be ok:
(2) The system as a whole is stopped, on the way in from migration/vmload.
(3) The cpu is offline, on the way in from poweroff/reset.
(4) Running in round-robin mode, so there is *never
If we change the deprecation logic in include/hw/boards.h, we must make
a corresponding change to docs/conf.py and docs/about/deprecated.rst.
Add comments to these files as a warning to future maintainers to keep
these files in sync.
Signed-off-by: Daniel P. Berrangé
---
docs/conf.py| 4
This patch adds a virtual device to qemu which the uefi firmware can use
to store variables. This moves the UEFI variable management from
privileged guest code (managing vars in pflash) to the host. Main
advantage is that the need to have privilege separation in the guest
goes away.
On x86 privi
Add variables for a bunch of UEFI GUIDs we will need.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-guid.c | 99 ++
1 file changed, 99 insertions(+)
create mode 100644 hw/uefi/var-service-guid.c
diff --git a/hw/uefi/var-service-guid.c b/hw/uefi/var-se
Wire up uefi-vars in the build system.
Signed-off-by: Gerd Hoffmann
---
hw/meson.build | 1 +
hw/uefi/meson.build | 19 +++
meson.build | 1 +
3 files changed, 21 insertions(+)
diff --git a/hw/meson.build b/hw/meson.build
index b827c82c5d7b..138f5d59e178 100644
--
This is the uefi variable service (EfiSmmVariableProtocol), providing
functions for listing, reading and updating variables.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-vars.c | 725 +
1 file changed, 725 insertions(+)
create mode 100644 hw/uefi/var-
On Thu, Feb 20, 2025 at 06:59:34PM +0800, Zhao Liu wrote:
> And one more thing :-) ...
>
> > static const CPUCaches epyc_rome_cache_info = {
> > .l1d_cache = &(CPUCacheInfo) {
> > .type = DATA_CACHE,
> > @@ -5207,6 +5261,25 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >
This implements pkcs7 signature verification using gnutls.
Needed to check authenticated variable updates.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-pkcs7.c | 436
1 file changed, 436 insertions(+)
create mode 100644 hw/uefi/var-service-pkcs7.c
d
Allow the device being added to aarch64 virt VMs.
Signed-off-by: Gerd Hoffmann
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4a5a9666e916..046835836fc5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -81,6 +81,7 @@
#include "hw/mem
Since 30933c4fb4 (tcg/cputlb: remove other-cpu capability from TLB flushing)
we don't expect non-CPU callers to the tlb_flush() code. Normally I
would drop the call anyway as the common cpu_reset() code will call
tlb_flush anyway. However as the flush function does more than that,
and is called fro
Richard Henderson writes:
> On 2/25/25 03:08, Alex Bennée wrote:
>> To move the main api.c to a single build compilation object we need to
>> start splitting out user and system specific code. As we need to grob
>> around host headers we move these particular helpers into the *-user
>> mode direc
The commit 30933c4fb4 (tcg/cputlb: remove other-cpu capability from
TLB flushing) introduced a regression that only shows up when
--enable-debug-tcg is used. The main use case of tlb_flush outside of
the current_cpu context is for handling reset and CPU creation. Rather
than revert the commit intro
This is based on one of the fixes from Igor's series:
20250207162048.1890669-1-imamm...@redhat.com
Rather than reverting the patch I cleaned up a couple of cases where
we either didn't need to do a flush or we could trivially defer to
when the CPU started running. For the other cases I introduc
From: Igor Mammedov
that will enable assert_cpu_is_self when QEMU is configured with
--enable-debug
without need for manual patching DEBUG_TLB_GATE define.
Need to manually path DEBUG_TLB_GATE define to enable assert,
let regression caused by [1] creep in unnoticed.
1) 30933c4fb4f3d ("tcg/cp
On 2/25/25 03:08, Alex Bennée wrote:
Now all the softmmu/user-mode stuff has been split out we can build
this compilation unit only once.
Signed-off-by: Alex Bennée
---
plugins/api.c | 11 ---
plugins/meson.build | 3 +--
2 files changed, 1 insertion(+), 13 deletions(-)
Revi
Richard Henderson writes:
> Add infrastructure for more consolidated output of opcodes.
> The base structure allows for constraints to be either static
> or dynamic, and for the existence of those constraints to
> replace TCG_TARGET_HAS_* and the bulk of tcg_op_supported.
>
> Signed-off-by: Richa
The vCPU parent already triggers a tb_flush so this is un-needed:
#0 tlb_flush_other_cpu (cpu=0x56df8630) at ../../accel/tcg/cputlb.c:419
#1 0x55ee38c9 in tcg_cpu_reset_hold (cpu=0x56df8630) at
../../accel/tcg/tcg-accel-ops.c:88
#2 0x55bc29e5 in cpu_exec_reset_hol
On 25.02.2025 18:16, Peter Xu wrote:
On Wed, Feb 19, 2025 at 09:33:49PM +0100, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
All callers to migration_incoming_state_destroy() other than
postcopy_ram_listen_thread() do this call with BQL held.
Since migration_incoming_state_destroy()
+/* Ram device is remapped in new QEMU */
+if (memory_region_is_ram_device(mr)) {
+return true;
+}
+
+/* Named files are remapped in new QEMU, same contents if shared (no COW)
*/
+if (qemu_ram_is_shared(rb) && qemu_ram_is_named_file(rb)) {
+return true;
+}
On Wed, 15 Jan 2025 12:44:54 -0500
Peter Xu wrote:
> On Wed, Jan 15, 2025 at 11:19:28AM +0100, Igor Mammedov wrote:
> > Another question is if it's safe to move/rename device withing QOM tree
> > wrt migration (i.e. when 1st instance has old QOM tree and 2nd a modified
> > one)
> >
> > quick sm
Daniel P. Berrangé writes:
> The 'qapi.backend.QAPIBackend' class defines an API contract for code
> generators. The current generator is put into a new class
> 'qapi.backend.QAPICBackend' and made to be the default impl.
>
> A custom generator can be requested using the '-k' arg which takes a
M
The global used_memslots or used_shared_memslots is updated to 0 unexpectly
when a vhost device destroyed. This can occur during scenarios such as live
detaching a vhost device or restarting a vhost-user net backend (e.g.,
OVS-DPDK):
#0 vhost_commit(listener) at hw/virtio/vhost.c:439
#1 listen
From: Kun Qin
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2625
This change aims to add a TPM device for SBSA ref machine.
The implementation adds a TPM create routine during machine
initialization.
The backend can be the same as the rest of TPM support, by using swtpm.
Signed-off-
On Tue, Feb 25, 2025 at 06:21:20AM +, Zhijian Li (Fujitsu) wrote:
>
>
> On 25/02/2025 04:00, Peter Xu wrote:
> > On Fri, Feb 21, 2025 at 02:36:11PM +0800, Li Zhijian wrote:
> >> Since we have disabled RDMA + postcopy, it's safe to remove
> >> the migration_in_postcopy() that follows the migr
On 25/2/25 12:08, Alex Bennée wrote:
Requiring TARGET_PAGE_MASK to be defined gets in the way of building
this unit once. As tcg_ctx has the value lets use it.
Signed-off-by: Alex Bennée
---
plugins/api.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-D
On 25/2/25 12:08, Alex Bennée wrote:
We have a function we can call for this, lets not rely on macros that
stop us building once.
Signed-off-by: Alex Bennée
---
plugins/loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
The vCPU parent already triggers a tb_flush so this is un-needed:
#0 tlb_flush_other_cpu (cpu=0x56df8630) at ../../accel/tcg/cputlb.c:419
#1 0x55ee38c9 in tcg_cpu_reset_hold (cpu=0x56df8630) at
../../accel/tcg/tcg-accel-ops.c:88
#2 0x55bc29e5 in cpu_exec_reset_hol
On 17/2/25 00:07, Richard Henderson wrote:
Add infrastructure for more consolidated output of opcodes.
The base structure allows for constraints to be either static
or dynamic, and for the existence of those constraints to
replace TCG_TARGET_HAS_* and the bulk of tcg_op_supported.
Signed-off-by:
On Tue, 25 Feb 2025, Alex Bennée wrote:
The vCPU parent already triggers a tb_flush so this is un-needed:
Typo in subject: cpu_reset
#0 tlb_flush_other_cpu (cpu=0x56df8630) at ../../accel/tcg/cputlb.c:419
#1 0x55ee38c9 in tcg_cpu_reset_hold (cpu=0x56df8630) at
../../accel
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
> serial. All other devices of the A53 memory map are represented as
> TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
> for running
On 2/18/2025 11:10 AM, Peter Xu wrote:
On Fri, Feb 14, 2025 at 03:12:22PM -0500, Steven Sistare wrote:
On 1/30/2025 12:01 PM, Peter Xu wrote:
On Wed, Jan 29, 2025 at 01:20:13PM -0500, Steven Sistare wrote:
On 1/17/2025 6:57 PM, Peter Xu wrote:
On Fri, Jan 17, 2025 at 02:10:14PM -0500, Steven
On 2/25/25 04:58, Peter Maydell wrote:
On Tue, 25 Feb 2025 at 12:44, Marek Szyprowski wrote:
This patch adds support for the AARCH64 ILP32 ABI [1] to the QEMU
linux-user AARCH64 port.
The ILP32 ABI was initially developed quite some time ago [2] to
facilitate porting legacy code to the new AA
The vCPU parent already triggers a tb_flush so this is un-needed:
#0 tlb_flush_other_cpu (cpu=0x56df8630) at ../../accel/tcg/cputlb.c:419
#1 0x55ee38c9 in tcg_cpu_reset_hold (cpu=0x56df8630) at
../../accel/tcg/tcg-accel-ops.c:88
#2 0x55bc29e5 in cpu_exec_reset_hol
Igor Mammedov writes:
> that will enable assert_cpu_is_self when QEMU is configured with
>--enable-debug
> without need for manual patching DEBUG_TLB_GATE define.
>
> Need to manually path DEBUG_TLB_GATE define to enable assert,
> let regression caused by [1] creep in unnoticed.
>
> 1) 30933c
Hi
On Tue, Feb 25, 2025 at 2:47 PM Haoqian He wrote:
>
> If the chardev is client, the socket file path in localAddr may be NULL.
> This is because the socket path comes from getsockname(), according
> to man page, getsockname() returns the current address bound by the
> socket sockfd. If the cha
When gitlab initializes the repo checkout for a CI job, it will have
done a shallow clone with only partial history. Periodically the objects
that are omitted cause trouble with the check-patch/check-dco jobs. This
is exhibited as reporting strange errors being unable to fetch certain
objects that
Igor Mammedov writes:
> target_reset_cpu() static inlines have no user,
> remove them.
>
> Signed-off-by: Igor Mammedov
> ---
> CC: Warner Losh
> CC: Kyle Evans
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On 25/2/25 01:40, Jiaxun Yang wrote:
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/csr_helper.c
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> This series adds a new aarch64 machine to QEMU: i.MX 8M Plus EVK [1]. It
> allows
> for running Linux distributions such as Buildroot
> (freescale_imx8mpevk_defconfig) and Arch Linux [2] via direct kernel boot.
> U-Boot does not work yet.
On 25/2/25 01:40, Jiaxun Yang wrote:
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c
On Tue, Feb 25, 2025 at 06:37:21AM +, Zhijian Li (Fujitsu) wrote:
>
>
> On 25/02/2025 03:58, Peter Xu wrote:
> > On Fri, Feb 21, 2025 at 02:36:09PM +0800, Li Zhijian wrote:
> >> Similar to migration_channels_and_transport_compatible(), introduce a
> >> new helper migration_capabilities_and_tr
Property kvm-pv-ipi is added to paravirt ipi feature, it is specially
for kvm mode.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.h| 1 +
target/loongarch/kvm/kvm.c| 18 ++
target/loongarch/loongarch-qmp-cmds.c | 2 +-
3 fil
The similiar with cpucfg register, paravirt ipi feature is set in
function kvm_arch_put_registers(). Instead the paravirt feature can
be enabled only once, it cannot be changed dynamically.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 36 +++
tags/pull-loongarch-20250225
for you to fetch changes up to db369c11c90b35f3a6ab59ad78564aea5b30c3da:
target/loongarch: Enable virtual extioi feature (2025-02-25 16:05:31 +0800)
pull-loongarch-2025
Paravirt ipi feature is OnOffAuto type, feature detection is added
to check whether it is supported by KVM host.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.h | 2 ++
target/loongarch/kvm/kvm.c | 36 +++-
2 files changed, 37 insert
LBT and PMU feature is supported only in kvm mode, move property
about these two features to function kvm_loongarch_cpu_post_init().
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.c | 40 ++
target/loongarch/kvm/kvm.c | 35
On 3A5000 system, the physical address space width for host is 48,
however 47 bit for KVM VM. For KVM VM, size of physical address space is
the same with that of virtual user space address.
Here modify physical address space width with 47 bit in KVM mode.
Signed-off-by: Bibo Mao
Reviewed-by: Bib
Feature virtual extioi is loongArch virt machine property rather than
vCPU property in qemu side. However it is vCPU property in KVM kernel
side, here add loongArch virt machine property checking and enable virt
extioi feature when vCPU is created.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
-
Write operation with R32 (orig_a0) and R34 (CSR_BADV) is discarded on
gdbstub implementation for LoongArch system. And return value should
be register size rather than 0, since it is used to calculate offset of
next register such as R33 (PC) in function handle_write_all_regs().
Cc: qemu-sta...@non
Paravirt steal time feature is OnOffAuto type, feature detection is added
to check whether it is supported on KVM host.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.h | 1 +
target/loongarch/kvm/kvm.c | 20
2 files changed, 21 insertions(+)
d
Property kvm-steal-time is added for kvm steal time feature, it is
specially for kvm mode.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.h| 1 +
target/loongarch/kvm/kvm.c| 18 ++
target/loongarch/loongarch-qmp-cmds.c | 2 +-
Some features such as LBT and PMU are implemented in kvm mode,
With paravirt features in future, post init function is added
for kvm mode, so that property for these features will be created
in kvm post init function.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.c
From: Xianglai Li
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwise the kernel will return an error and the command word
will fail to be sent.
Signed-off-by: Xianglai Li
Rev
On Thu, Feb 20, 2025 at 08:58:17AM +0100, Markus Armbruster wrote:
> Cc: John for advice on my somewhat nebulous mypy worries at the end.
>
> Daniel P. Berrangé writes:
>
> > The 'qapi.backend.QAPIBackend' class defines an API contract for
> > code generators. The current generator is put into a
On 2/25/25 03:08, Alex Bennée wrote:
Requiring TARGET_PAGE_MASK to be defined gets in the way of building
this unit once. As tcg_ctx has the value lets use it.
Signed-off-by: Alex Bennée
---
plugins/api.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/plugins/api.c b/plu
Signed-off-by: Loïc Lefort
---
target/riscv/pmp.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ddb7e0d23c..b7f1430ff8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -31,6 +31,15 @@ static bo
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3, 7, 9, 11, 13, 15 for
Hi,
These patches fix Smepmp implementation to make it compliant with the spec.
First patch limits RLB to CSR changes since RLB should not affect privilege
evaluation. Patch 2 extracts some common code into a function (to be used in
patch 3). Patch 3 fixes validation of pmpcfg CSR writes in order
On Fri, 21 Feb 2025 11:04:35 +
Jonathan Cameron wrote:
> On Fri, 21 Feb 2025 15:27:36 +1000
> Gavin Shan wrote:
>
> > On 2/20/25 3:55 AM, Igor Mammedov wrote:
> > > On Fri, 14 Feb 2025 14:16:35 +1000
> > > Gavin Shan wrote:
> > >
> > >> The error -1 is returned if the previously rep
在2025年2月25日二月 上午8:50，bibo mao写道：
> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>> Hi all,
>>
>> This series is a collection of small fixes I made to TCG for
>> LoongArch32.
>>
>> There are still many thing broken, especially on CSRs. More
>> series following. However this is sufficient to boot 32b
On Tue, Feb 25, 2025 at 07:04:11AM +0100, Markus Armbruster wrote:
> John, how does this mix with the linting parts of your "[PATCH 00/10]
> qapi: misc testing and doc patches"?
Since this is only an RFC, I would expect that John's patch series can
simply ignore this & merge when ready. If we deci
> -Original Message-
> From: Cédric Le Goater
> Sent: 17 February 2025 11:05 PM
> To: qemu-devel@nongnu.org
> Cc: Alex Williamson ;
> tomitamo...@gmail.com; corvin.koe...@gmail.com; Kirti Wankhede
> ; Joao Martins ;
> Cédric Le Goater ; Tony Krowiak
> ; Eric Farman ; Eric Auger
>
> Subj
Igor Mammedov writes:
> From: Philippe Mathieu-Daudé
>
> Let vCPUs wait for themselves being ready first, then other ones.
> This allows the first thread to starts without the global vcpu
> queue (thus &first_cpu) being populated.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Signed-off-by: Igor
On Thu, 21 Nov 2024 14:07:55 +0800
yuanminghao wrote:
> The global used_memslots or used_shared_memslots is updated to 0 unexpectly
it shouldn't be 0 in practice, as it comes from number of RAM regions VM has.
It's likely a bug somewhere else.
Please describe a way to reproduce the issue.
> wh
On 2/21/2025 7:38 AM, Michael S. Tsirkin wrote:
On Wed, Feb 12, 2025 at 05:44:49AM +, Suravee Suthikulpanit wrote:
Current amd-iommu model internally creates an AMDVI-PCI device. Here is
a snippet from info qtree:
bus: main-system-bus
type System
dev: amd-iommu, id ""
Igor Mammedov writes:
> Reseting vcpu before its thread is created, caused various issues in the past
> for other targets. It doesn't cause issues for m68k at the moment but
> to be consistent with the rest of targets, move reset during realize time
> after qemu_init_vcpu().
>
> That basically pr
On Mon, 24 Feb 2025 at 20:51, Pierrick Bouvier
wrote:
>
> Regression introduced by cf76c4
> (hw/misc: Add nr_regs and cold_reset_values to NPCM CLK)
>
> cold_reset_values has a different size, depending on device used
> (NPCM7xx vs NPCM8xx). However, s->regs has a fixed size, which matches
> NPCM8
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> On a real device, the boot ROM contains the very first instructions the CPU
> executes. Also, U-Boot calls into the ROM to determine the boot device. While
> we're not actually implementing this here, let's create the infrastructure and
> a
Il ven 21 feb 2025, 11:41 Zhao Liu ha scritto:
> Hi Paolo,
>
> > It is a common convention in QEMU to return a positive value in case of
> > success, and a negated errno value in case of error. Unfortunately,
> > using errno portably in Rust is a bit complicated; on Unix the errno
> > values are
On Mon, 24 Feb 2025 at 16:57, Joelle van Dyne wrote:
>
> macOS 15.2's Hypervisor.framework exposes SME feature on M4 Macs.
> However, HVF does not properly support it yet causing QEMU to
> fail to start when HVF accelerator is used on these systems.
>
> Signed-off-by: Joelle van Dyne
> ---
> tar
On Mon, 24 Feb 2025 at 18:41, Joelle van Dyne wrote:
>
> According to the ARM manual, when SSE=1 the data item must be sign
> extended.
>
> Signed-off-by: Joelle van Dyne
> ---
> target/arm/hvf/hvf.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/h
On 2/24/25 1:39 AM, zhouq...@iscas.ac.cn wrote:
From: Quan Zhou
When the Sscofpmf/Svade/Svadu/Smnpm/Ssnpm exts is available
expose it to the guest so that guest can use it.
Signed-off-by: Quan Zhou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/kvm/kvm-cpu.c | 5 +
1 fil
On 2/19/2025 6:58 PM, Francesco Lavra wrote:
On Fri, 2025-01-24 at 08:20 -0500, Xiaoyao Li wrote:
+int tdvf_parse_metadata(TdxFirmware *fw, void *flash_ptr, int size)
+{
+ g_autofree TdvfSectionEntry *sections = NULL;
+ TdvfMetadata *metadata;
+ ssize_t entries_size;
+ int i;
+
+
On Tue, Feb 25, 2025 at 01:31:56PM +0100, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > The 'qapi.backend.QAPIBackend' class defines an API contract for code
> > generators. The current generator is put into a new class
> > 'qapi.backend.QAPICBackend' and made to be the default impl
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