From: Li Zhijian
Address a memory leak issue by ensuring `regs->special_ops` is freed when
`msix_init_exclusive_bar()` encounters an error during CXL Type3 device
initialization.
Additionally, this patch renames err_address_space_free to err_msix_uninit
for better clarity and logical flow
Signe
From: Li Zhijian
msix_uninit_exclusive_bar() should be paired with msix_init_exclusive_bar()
Ensure proper resource cleanup by adding the missing
`msix_uninit_exclusive_bar()` call for the Type3 CXL device.
Signed-off-by: Li Zhijian
Signed-off-by: Jonathan Cameron
Message-Id: <20250203161908.
From: Jonah Palmer
Minor update to some of the documentation / comments in
hw/virtio/vhost-iova-tree.c.
Signed-off-by: Jonah Palmer
Reviewed-by: Eugenio Pérez
Tested-by: Lei Yang
Message-Id: <20250217144936.3589907-4-jonah.pal...@oracle.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Mic
We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but
in no particular order and missing some of them (like env->mstatus).
Create a helper to do that, unclogging reset_vcpu(), and initialize
env->mstatus as well. Keep the regs in the same order they appear in
struct kvm_riscv_cs
From: Stefano Garzarella
The function `vhost_dev_init()` expects the `struct vhost_dev`
(passed as a parameter) to be fully initialized. This is important
because some parts of the code check whether `vhost_dev->config_ops`
is NULL to determine if it has been set (e.g. later via
`vhost_dev_set_co
From: Eric Auger
To avoid any translation faults, the IOMMUs are expected to be
reset after the devices they protect. Document that we expect
DMA requests to be stopped during the 'enter' or 'hold' phase
while IOMMUs should be reset during the 'exit' phase.
Signed-off-by: Eric Auger
Reviewed-by
From: Thomas Huth
All other vhost-user tests here use modern virtio, too, so let's
adjust the vhost-user-net test accordingly.
Signed-off-by: Thomas Huth
Message-Id: <20250203124346.169607-1-th...@redhat.com>
Reviewed-by: Fabiano Rosas
Reviewed-by: Stefano Garzarella
Reviewed-by: Michael S. T
From: Eric Auger
Currently the IOMMU may be reset before the devices
it protects. For example this happens with virtio devices
but also with VFIO devices. In this latter case this
produces spurious translation faults on host.
Let's use 3-phase reset mechanism and reset the IOMMU on
exit phase af
From: Akihiko Odaki
pcie_sriov doesn't have code to restore its state after migration, but
igb, which uses pcie_sriov, naively claimed its migration capability.
Add code to register VFs after migration and fix igb migration.
Fixes: 3a977deebe6b ("Intrdocue igb device emulation")
Signed-off-by:
From: Akihiko Odaki
When an eBPF program cannot be attached, virtio_net_load_ebpf() returns
false, and virtio_net_device_realize() enters the code path to handle
errors because of this, but it causes NULL dereference because no error
is generated.
Change virtio_net_load_ebpf() to return false on
On Tue, Feb 18, 2025 at 01:38:53PM -0300, Daniel Henrique Barboza wrote:
> At this moment ziccrse is a TCG always enable ext that has no flag. KVM
> will expose ziccrse to users, allowing them to turn it on/off.
KVM won't allow this to be disabled, since it can't be (there's no way
to turn off the
From: Thomas Huth
We now have a general note about versioned machine types getting
deprecated and removed at the beginning of the deprecated.rst file,
so we should also have a general note about this in removed-features.rst
(which will also apply to versioned non-x86 machine types) instead of
lis
On Tue, Feb 18, 2025 at 01:38:54PM -0300, Daniel Henrique Barboza wrote:
> Expose ziccrse, zabha and svvptc.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kv
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
> is passed to host to construct nested page table. We need to check
> compatibility of some critical IOMMU capabilities between vIOMMU and
> host IOMMU to ensure gue
On 17/2/25 13:50, Peter Maydell wrote:
In Intel terminology, a floatx80 Infinity with the explicit integer
bit clear is a "pseudo-infinity"; for x86 these are not valid
infinity values. m68k is looser and does not care whether the
Integer bit is set or clear in an infinity.
Move this setting to
On 17/2/25 13:50, Peter Maydell wrote:
Because floatx80 has an explicit integer bit, this permits some
odd encodings where the integer bit is not set correctly for the
floating point value type. In In Intel terminology the
categories are:
exp == 0, int = 0, mantissa == 0 : zeroes
exp == 0
From: Akihiko Odaki
The guest cannot use VFs due to the lack of multifunction support but
can use PFs.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-4-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/s390x/s390-pci-bus.c | 9 +++
riscv_cpu_reset_hold() does a lot of TCG-related initializations that
aren't relevant for KVM, but nevertheless are impacting the reset state
of KVM vcpus.
When running a KVM guest, kvm_riscv_reset_vcpu() is called at the end of
reset_hold(). At that point env->mstatus is initialized to a non-zero
From: Konstantin Shkolnyy
VDPA didn't work on a big-endian machine due to missing/incorrect
CPU<->LE data format conversions.
Signed-off-by: Konstantin Shkolnyy
Message-Id: <20250212164923.1971538-1-k...@linux.ibm.com>
Fixes: 10857ec0ad ("vhost: Add VhostShadowVirtqueue")
Acked-by: Eugenio Pére
From: Eric Auger
Currently the iommu may be reset before the devices
it protects. For example this happens with virtio-net.
Let's use 3-phase reset mechanism and reset the IOMMU on
exit phase after all DMA capable devices have been
reset during the 'enter' or 'hold' phase.
Signed-off-by: Eric A
From: Sairaj Kodilkar
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.
Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodi
On 20/02/2025 19.39, Peter Maydell wrote:
I'm trying to debug some functional tests that fail for me
with 'make check-functional' on a debug build. Consistently
(well, same set of tests in two runs) when I run
'make -j8 check-functional' these fail:
7/44 qemu:func-thorough+func-arm-thorough+th
On 21/02/2025 13.54, Thomas Huth wrote:
On 20/02/2025 19.39, Peter Maydell wrote:
I'm trying to debug some functional tests that fail for me
with 'make check-functional' on a debug build. Consistently
(well, same set of tests in two runs) when I run
'make -j8 check-functional' these fail:
7/4
On Fri, 21 Feb 2025 at 13:08, Thomas Huth wrote:
>
> On 21/02/2025 13.54, Thomas Huth wrote:
> > diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/
> > test_arm_sx1.py
> > --- a/tests/functional/test_arm_sx1.py
> > +++ b/tests/functional/test_arm_sx1.py
> > @@ -43,7 +43,8 @@ def tes
In case of multiple chunks, code in qxl_unpack_chunks() takes size of the
wrong (next in the chain) chunk, instead of using current chunk size.
This leads to wrong number of bytes being copied, and to crashes if next
chunk size is larger than the current one.
Based on the code by Gao Yong.
Resolv
On 17/2/25 13:50, Peter Maydell wrote:
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so w
On 2/21/25 06:43, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the
Crypto Manager Self Test
On 2/13/25 04:35, Jamin Lin wrote:
Currently, it does not support the CRYPT command. Instead, it only
sends an interrupt to notify the firmware that
We want to refactor HVF's instruction emulator to a common component. Renaming
hvf_mmio_buf removes the association between HVF and the instruction emulator.
The definition of the field is still guarded by CONFIG_HVF for now, since it is
the only user.
No functional change.
Signed-off-by: Wei Li
This will be used to remove HVF specific code from the instruction emulator.
For now we only introduce two hooks for x86_decode.c. More hooks will be added
when the code is refactored.
The emulator initialization function now takes in a pointer to the ops
structure.
Signed-off-by: Wei Liu
---
Hi,
Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
Hypervisor (MSHV for short). The driver is being upstreamed. The first
supported VMM is Cloud Hypervisor. QEMU will be the second supported
VMM.
The plan is to write an mshv accelerator in QEMU. The accelerator is stil
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 6 ++
target/i386/hvf/x86_emu.c | 8
target/i386/hvf/x86_emu.h | 1 +
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index 533b05577d..e108e2bbe6 100644
--- a/target/
Signed-off-by: Wei Liu
---
target/i386/meson.build | 1 +
target/i386/x86-insn-emul/meson.build | 0
2 files changed, 1 insertion(+)
create mode 100644 target/i386/x86-insn-emul/meson.build
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 2e9c472f49..e93c1c20ca
The prefix x68 is wrong. Change it to x86.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86.c | 4 ++--
target/i386/hvf/x86.h | 8
target/i386/hvf/x86_descr.c | 8
target/i386/hvf/x86_descr.h | 6 +++---
target/i386/hvf/x86_tas
Move x86_decode, x86_emu, x86_flags and some headers to the new location.
Fix up all the inclusion sites in hvf.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 8
target/i386/hvf/meson.build | 3 ---
target/i386/hvf/vmx.h
They contain HVF specific code. Move them to a better location and
add "hvf_" prefix. Fix up all the call sites.
No functional change.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 71 +++---
target/i386/hvf/x86_emu.c | 46
tar
The macros will be used by the instruction emulator. The code is the same as
the one under hvf.
Signed-off-by: Wei Liu
---
target/i386/x86-insn-emul/panic.h | 45 +++
1 file changed, 45 insertions(+)
create mode 100644 target/i386/x86-insn-emul/panic.h
diff --git a/
The same structure and code can be used by other accelerators. Drop
the hvf prefix in the type and field name.
No functional change.
Signed-off-by: Wei Liu
---
target/i386/cpu.h | 6 ++--
target/i386/hvf/x86_flags.c | 56 ++---
2 files changed, 31 inse
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_emu.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 84f97ed386..44ef068bef 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -1240,10 +1240,6 @@ static void
This requires making raise_exception non-static. That function needs to be
renamed to avoid clashing with a function in TCG.
Mostly code movement. No functional change.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf-i386.h | 2 +
target/i386/hvf/hvf.c | 216 ++
This drops the calls to hvf_handle_io from x86_emu.c.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 1 +
target/i386/hvf/x86_emu.c | 30 +++---
target/i386/hvf/x86_emu.h | 2 ++
3 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/target/i386/hvf/hv
Change the first argument's type to be CPUState to match other hooks.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf-i386.h | 4 ++--
target/i386/hvf/hvf.c | 18 ++
target/i386/hvf/x86_emu.c | 4 ++--
target/i386/hvf/x86_emu.h | 2 ++
4 files changed, 16 insertions(+),
Make the code to rely on the segment definition for checking cs.db.
This allows removing HVF specific VMX related definition from the
decoder.
Introduce a function for retrieving the CS descriptor.
No functional change intended.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_decode.c | 20
These headers will be moved out to its own component.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86.h| 4 ++--
target/i386/hvf/x86_decode.h | 4 ++--
target/i386/hvf/x86_flags.h | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/i386/hvf/x86.h b/target/i3
On my local machine, for a debug build, sbsaref_alpine takes
nearly 900s:
$ (cd build/x86 && ./pyvenv/bin/meson test --setup thorough --suite
func-thorough func-aarch64-aarch64_sbsaref_alpine
)
1/1 qemu:func-thorough+func-aarch64-thorough+thorough /
func-aarch64-aarch64_sbsaref_alpine
On 21/2/25 14:28, Peter Maydell wrote:
On Fri, 21 Feb 2025 at 13:05, Philippe Mathieu-Daudé wrote:
Hi Peter,
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision oper
On 2/21/25 03:23, Jamin Lin wrote:
Hi Cedric,
Cc: Troy Lee
Subject: Re: [PATCH v3 04/28] hw/arm/aspeed: Rename IRQ table and machine
name for AST2700 A0
On 2/13/25 04:35, Jamin Lin wrote:
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename
its IRQ table and machine name.
From: Akihiko Odaki
Release VFs failed to realize just as we do in unregister_vfs().
Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-9-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Si
On 21/02/2025 11:57, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Fri, Feb 21, 2025 at 08:07:25AM +, CLEMENT MATHIEU--DRIF wrote:
>> From: Clement Mathieu
From: Eric Auger
Currently the iommu may be reset before the devices
it protects. For example this happens with virtio-scsi-pci.
when system_reset is issued from qmp monitor: spurious
"virtio: zero sized buffers are not allowed" warnings can
be observed. This happens because outstanding DMA reque
From: Nicholas Piggin
The PCI Local Bus Specification says the result of writes to MSI-X
PBA memory is undefined. QEMU implements them as no-ops, so remove
the pointless write from qpci_msix_pending().
Signed-off-by: Nicholas Piggin
Message-Id: <20250117172244.406206-2-npig...@gmail.com>
Review
From: Akihiko Odaki
The SR-IOV PFs set the multifunction bit during device realization so
check them after that. There is no functional change because we
explicitly ignore the multifunction bit for SR-IOV devices.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-5-7cb370606...@dayni
From: Akihiko Odaki
Disabled means it is a disabled SR-IOV VF and hidden from the guest.
Do not create DT when starting the system and also keep the disabled PCI
device not linked to DRC, which generates DT in case of hotplug.
Signed-off-by: Akihiko Odaki
Reviewed-by: Shivaprasad G Bhat
Tested-
From: Thomas Huth
QEMU currently crashes when you try to inspect the machines based on
TYPE_PC_MACHINE for their properties:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "pc-q35-10.0-machine"}}' \
| ./q
On Fri, 21 Feb 2025 at 12:54, Thomas Huth wrote:
>
> On 20/02/2025 19.39, Peter Maydell wrote:
> > Any suggestions for how to debug?
>
> Some TCG-based tests are slowing down very much when running on a shared
> hyperthreaded CPU ... Do you have 8 real cores in your system, or rather 4
> real co
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Introduce a new structure VTDHostIOMMUDevice which replaces
> HostIOMMUDevice to be stored in hash table.
>
> It includes a reference to HostIOMMUDevice and IntelIOMMUState,
> also includes BDF information which will be used in future
> patches.
>
> S
Hi Peter,
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision operation, and the
Linux-user NWFPE emulation nominally supports it, but these are
minor.) x86 and m68k dis
On Fri, 21 Feb 2025 at 13:05, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 17/2/25 13:50, Peter Maydell wrote:
>
> > (1) floatx80 behaviours
> >
> > Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
> > use in the xsrqpxp round-to-80-bit-precision operation, and the
> > Li
On 17/2/25 13:50, Peter Maydell wrote:
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so w
There is a conflicting declaration for hvf_handle_io in x86_emu.c. The type of
the first argument is wrong. There has never been a problem because the first
argument is not used in hvf_handle_io.
That being said, the code shouldn't contain such an error. Use the proper
declaration from hvf-i386.
Update headers to retrieve the latest KVM caps for RISC-V.
Signed-off-by: Daniel Henrique Barboza
---
include/standard-headers/linux/ethtool.h | 4 +
include/standard-headers/linux/fuse.h | 76 ++-
.../linux/input-event-codes.h | 1 +
include/standa
At this moment ziccrse is a TCG always enabled named feature for
priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
the KVM driver update ziccrse as well, turning it on/off depending on
host settings, but for that we'll need an ext_ziccrse flag in the CPU
state.
Create an exc
On 2/21/25 1:49 PM, Eric Auger wrote:
> Hi Zhenzhong,
>
>
> On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
>> is passed to host to construct nested page table. We need to check
>> compatibility of some critical IOMMU capabi
Hi,
In this version all changes were made in patch 2. In the first posting I
forgot to update how riscv,isa was going to be calculated when
ext_ziccrse is set by KVM.
A change was made in isa_edata_arr[] to use ext_ziccrse, instead of
'has_priv_1_11', and TCG code were changed to set ext_ziccrse
Expose ziccrse, zabha and svvptc.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 23ce779359..471fd554b3 100644
--- a/target/riscv
On 20/2/25 19:54, Peter Maydell wrote:
On Thu, 20 Feb 2025 at 18:39, Richard Henderson
wrote:
On 2/20/25 09:12, Peter Maydell wrote:
That suggests that we are correctly implementing the x87
required behaviour in QEMU, and so that the TODO comment
I add in this patch isn't right. But then I'm
From: Jonah Palmer
Creates and supports a GPA->IOVA tree and a partial IOVA->HVA tree by
splitting up guest-backed memory maps and host-only memory maps from the
full IOVA->HVA tree. That is, any guest-backed memory maps are now
stored in the GPA->IOVA tree and host-only memory maps stay in the
I
On Fri, 21 Feb 2025 10:51:11 +0800
Yuquan Wang wrote:
> >
> > Looks good. I've queued it up on my gitlab staging tree, but
> > Michael if you want to pick this one directly that's fine as well.
> >
> > I should be pushing out my gitlab tree shortly (bit of networking
> > fun to deal with).
> >
On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> On Mon, 17 Feb 2025 19:20:39 +0800
> Yuquan Wang wrote:
>
> > Add serial number parameter in the cxl persistent examples.
> >
> > Signed-off-by: Yuquan Wang
> Looks good. I've queued it up on my gitlab staging tree, but
> Mich
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> In early days vtd_ce_get_rid2pasid_entry() is used to get pasid entry of
is/was
> rid2pasid, then extend to any pasid. So a new name vtd_ce_get_pasid_entry
then it was extended to get any pasid entry?
> is better to match its functions.
to
Hi Ilya,
On 21/2/25 08:34, Ilya Chichkov wrote:
Add PCF8563 a real-time clock with calendar and I2C interface.
This commit adds support for interfacing with it and implements
functionality of setting timer, alarm, reading and writing time.
Datasheet: https://www.micros.com.pl/mediaserver/UZPCF8
Hi Paolo,
> It is a common convention in QEMU to return a positive value in case of
> success, and a negated errno value in case of error. Unfortunately,
> using errno portably in Rust is a bit complicated; on Unix the errno
> values are supported natively by io::Error, but on Windows they are no
On 14/2/25 05:16, Gavin Shan wrote:
acpi_ghes_memory_errors() is the only caller, no need to expose
the function. Besides, the last 'return' in this function isn't
necessary and remove it.
No functional changes intended.
Signed-off-by: Gavin Shan
---
hw/acpi/ghes.c | 6 ++
inclu
Ok, this one definitely caught my eye. :)
On 2/17/25 00:09, Richard Henderson wrote:
+tcg_gen_add_i32(t0, a, b);
+tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, a);
Compare against b instead? If there's an immediate (which could even be
zero) it is there.
+tcg_gen_add_i32
While running the new GPU tests it was noted that the proprietary
nVidia driver barfed when run under the sanitiser:
2025-02-20 11:13:08,226: [11:13:07.782] Output 'headless' attempts
EOTF mode SDR and colorimetry mode default.
2025-02-20 11:13:08,227: [11:13:07.784] Output 'headless' using
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop that iterated over each element
so that when a fl
Add support for reporting Hostwide state counters for nested KVM pseries
guests running with 'cap-nested-papr' on Qemu-TCG acting as
L0-hypervisor. The Hostwide state counters are statistics about state that
L0-hypervisor maintains for the L2-guests and represent the state of all
L2-guests, not jus
This version of the patch addresses the comments from the following review:
https://lore.kernel.org/all/2df9ae98-afb8-4647-be80-12540a1c4...@ventanamicro.com/
Previous version:
- v1:
https://lore.kernel.org/all/20250129144435.82451-1-paolo.sav...@embecosm.com/
The new version:
- fixes the "br
The following organisations appear on the US sanctions list:
Yadro: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=41125
ISPRAS: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=50890
As a result maintainers interacting with such entities would face
legal risk in a number of jur
On 21/2/25 16:19, Peter Maydell wrote:
On Fri, 21 Feb 2025 at 14:41, Philippe Mathieu-Daudé wrote:
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision operation, and
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_decode.c | 3 ---
target/i386/hvf/x86_emu.c| 4
2 files changed, 7 deletions(-)
diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c
index 31285952ad..ffece4773b 100644
--- a/target/i386/hvf/x86_decode.c
+++ b/target/i38
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface to probe_access and
probe_access_flags.
The ne
This patch originates from the last comment of the following review:
https://lore.kernel.org/all/2df9ae98-afb8-4647-be80-12540a1c4...@ventanamicro.com/
We call probe_pages to probe the memory before doing a memory operations or
probe_access_flags to do the same while also obtaining probe flags an
On Fri, 21 Feb 2025 at 14:02, Wei Liu wrote:
>
> Hi,
>
> Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
> Hypervisor (MSHV for short). The driver is being upstreamed. The first
> supported VMM is Cloud Hypervisor. QEMU will be the second supported
> VMM.
>
> The plan is
Complete the conversion from the ClassInitImpl trait to class_init() methods.
This will provide more freedom to split the qemu_api crate in separate parts.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 6 +-
rust/hw/timer/hpet/src/hpet.rs | 4 +-
rust/qemu-api/src/qde
The only function, right now, is to ensure that anything with a
SysBusDeviceClass class is a SysBusDevice.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 5 -
rust/hw/timer/hpet/src/hpet.rs | 4 +++-
rust/qemu-api/src/sysbus.rs | 8 +---
3 files changed, 12 in
This series is logically split in two parts. The first one is more
strictly tied to the objective of splitting qemu_api into multiple crates,
as it breaks the QOM bindings free of the constraints imposed by Rust
orphan rules. The second one instead completes another task that was on
my todo list,
Check that the right bounds are provided to the qom_isa! macro
whenever the class is defined to implement a certain class.
This removes the need to add IsA<> bounds together with the
*Impl trait bounds.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/qdev.rs | 2 +-
rust/qemu-api/src/qom.rs
Outside the qemu_api crate, orphan rules make the usage of ClassInitImpl
unwieldy. Now that it is optional, do not use it.
For PL011Class, this makes it easier to provide a PL011Impl trait similar
to the ones in the qemu_api crate. The device id consts are moved there.
Signed-off-by: Paolo Bonz
Send and Sync are now implemented on the opaque wrappers. Remove them
from the bindings module, unless the structs are pure data containers
and/or have no C functions defined on them.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 8 ++--
1 file changed, 2 insertions(+), 6
On 2/21/25 5:37 AM, Andrew Jones wrote:
On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote:
Using env->sie is clearer than using env->mie.
Maybe? Just as sstatus is a subset of mstatus, sip and sie can be
subsets of mip and mie. However, the AIA can change sip/sie so th
Am Thu, 20 Feb 2025 10:29:00 +0100
schrieb Philippe Mathieu-Daudé :
> Defines FIFO_DEPTH and use it, fixing coding style.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Luc Michel
> ---
> hw/char/mcf_uart.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> There are many call sites referencing context entry by calling
> vtd_as_to_context_entry() which will traverse the DMAR table.
didn't you mean vtd_dev_to_context_entry? instead
>
> In most cases we can use cached context entry in vtd_as->co
On Fri, 21 Feb 2025 07:38:23 +0100
Mauro Carvalho Chehab wrote:
> Em Mon, 3 Feb 2025 16:22:36 +0100
> Igor Mammedov escreveu:
>
> > On Mon, 3 Feb 2025 11:09:34 +
> > Jonathan Cameron wrote:
> >
> > > On Fri, 31 Jan 2025 18:42:41 +0100
> > > Mauro Carvalho Chehab wrote:
> > >
> > >
We allocate extra metadata SKBs in case of zerocopy send. This metadata memory
is accounted for in the OPTMEM limit. If there is any error with sending
zerocopy data or if zerocopy was skipped, these metadata SKBs are queued in the
socket error queue. This error queue is freed when userspace reads
On 20/2/25 09:48, Philippe Mathieu-Daudé wrote:
On 17/2/25 13:50, Peter Maydell wrote:
The work I needed to do to make various softfloat emulation behaviours
runtime-selectable for Arm FEAT_AFP has left the fpu code with very
few remaning target ifdefs. So this series turns the last remaning
one
On Fri, Feb 21, 2025 at 08:07:25AM +, CLEMENT MATHIEU--DRIF wrote:
> From: Clement Mathieu--Drif
>
> This patch set belongs to a list of series that add SVM support for VT-d.
>
> Here we focus on implementing ATS support in the IOMMU and adding a
> PCI-level API to be used by virtual devices
On Fri, 21 Feb 2025 15:27:36 +1000
Gavin Shan wrote:
> On 2/20/25 3:55 AM, Igor Mammedov wrote:
> > On Fri, 14 Feb 2025 14:16:35 +1000
> > Gavin Shan wrote:
> >
> >> The error -1 is returned if the previously reported CPER error
> >> hasn't been claimed. The virtual machine is terminated due
Ping? Patches 1-5 need review here.
thanks
-- PMM
On Tue, 4 Feb 2025 at 12:50, Peter Maydell wrote:
>
> This patchset is a respin of Alex's patches, with some extra fixes
> for bugs I discovered along the way in our existing code (and
> a bit of refactoring to make the fixes straightforward). It
On 2/21/2025 4:09 PM, David Hildenbrand wrote:
> On 21.02.25 03:25, Chenyi Qiang wrote:
>>
>>
>> On 2/21/2025 3:39 AM, David Hildenbrand wrote:
>>> On 20.02.25 17:13, Jean-Philippe Brucker wrote:
For Arm CCA we'd like the guest_memfd discard notifier to call the
IOMMU
notifiers an
From: Nicholas Piggin
Nothing should be doing this, but it doesn't get caught by
pci_register_bar(). Add an assertion to prevent misuse.
Signed-off-by: Nicholas Piggin
Message-Id: <20250117172842.406338-3-npig...@gmail.com>
Reviewed-by: Phil Dennis-Jordan
Signed-off-by: Nicholas Piggin
Review
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