Add PCF8563 a real-time clock with calendar and I2C interface.
This commit adds support for interfacing with it and implements
functionality of setting timer, alarm, reading and writing time.
Datasheet: https://www.micros.com.pl/mediaserver/UZPCF8563ts5_0001.pdf
Signed-off-by: Ilya Chichkov
---
From: Clement Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index eee625a9c6..4d240cad1c 100644
--- a/inclu
From: Clement Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clement Mathieu--Drif
ats_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 1 +
2 files
On 21.02.25 00:24, Michael S. Tsirkin wrote:
On Tue, Jan 28, 2025 at 07:57:03PM +0100, David Hildenbrand wrote:
This is based-on [1], which adds MSI-X support to virtio-balloon-pci,
but can be applied independently.
Turns out it is fairly easy to get virtio-mem-pci running on s390x. We
only hav
On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote:
> Using env->sie is clearer than using env->mie.
Maybe? Just as sstatus is a subset of mstatus, sip and sie can be
subsets of mip and mie. However, the AIA can change sip/sie so they
no longer alias mip/mie, which is why we h
On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> Explictly reset env->mstatus and env->sie.
mie was already getting set to zero, so that should have just been renamed
in the last patch, but I still think we should drop the last patch.
> Add a comment about env->mip
> bei
From: Clement Mathieu--Drif
PSS field of the ecap register stores the supported PASID size minus 1.
Thus, this commit adds support for 20bits PASIDs.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2 inserti
On Thu, Feb 20, 2025 at 01:13:11PM -0300, Daniel Henrique Barboza wrote:
> riscv_cpu_reset_hold() does a lot of TCG-related initializations that
> aren't relevant for KVM, but nevertheless are impacting the reset state
> of KVM vcpus.
>
> When running a KVM guest, kvm_riscv_reset_vcpu() is called
From: Clement Mathieu--Drif
The region returned by this operation will be used as the input region
for ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/hw/pci/pci.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 4002
On 21.02.25 09:26, David Hildenbrand wrote:
On 21.02.25 00:24, Michael S. Tsirkin wrote:
On Tue, Jan 28, 2025 at 07:57:03PM +0100, David Hildenbrand wrote:
This is based-on [1], which adds MSI-X support to virtio-balloon-pci,
but can be applied independently.
Turns out it is fairly easy to get
Hello Fabiano,
On Thu, 20 Feb 2025 at 19:06, Fabiano Rosas wrote:
> This is more or less the handshake idea. Or at least it could be
> included in that work.
>
> I have parked the handshake idea for now because I'm not seeing an
> immediate need for it and there are more pressing issues to be dea
On Fri, Feb 21, 2025 at 09:45:35AM +0100, Andrew Jones wrote:
> On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> > Explictly reset env->mstatus and env->sie.
>
> mie was already getting set to zero, so that should have just been renamed
> in the last patch, but I still th
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
Instead of having a function to check if ACPI is enabled
(acpi_ghes_present), change its logic to be more generic,
returing a pointed to AcpiGhesState.
Such change allows cleanup the ghes GED state code, avoiding
to read it multiple times, and simplifying the code.
Signed-off-by: Mauro Carvalho C
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported, by
using:
$ ghes_inject.py arm
which produces those warnings on Linux:
[ 705.0
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 5 -
include/hw/acpi/ghes.h | 3 +++
2 files
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
On 21/2/25 09:36, Wei Liu wrote:
The prefix x68 is wrong. Change it to x86.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86.c | 4 ++--
target/i386/hvf/x86.h | 8
target/i386/hvf/x86_descr.c | 8
target/i386/hvf/x86_desc
On 21/02/2025 15.06, Peter Maydell wrote:
On my local machine, for a debug build, sbsaref_alpine takes
nearly 900s:
$ (cd build/x86 && ./pyvenv/bin/meson test --setup thorough --suite
func-thorough func-aarch64-aarch64_sbsaref_alpine
)
1/1 qemu:func-thorough+func-aarch64-thorough+thorough /
f
Add a new ags flag to change the way HEST offsets are calculated.
Currently, offsets needed to store ACPI HEST offsets and read ack
are calculated based on a previous knowledge from the logic
which creates the HEST table.
Such logic is not generic, not allowing to easily add more HEST
entries nor
Now that the ghes preparation patches were merged, let's add support
for error injection.
On this series, the first 6 patches chang to the math used to calculate offsets
at HEST
table and hardware_error firmware file, together with its migration code.
Migration tested
with both latest QEMU relea
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 22 --
include/hw/acpi/ghes.h | 7 ++-
2 files chang
No functional change.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_emu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index d0a8e221ea..f1244640e6 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hv
Use the newly defined emul_ops. This allows the module to be reused
by other accelerator in the future.
No functional change intended.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_decode.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/i386/hvf
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision operation, and the
Linux-user NWFPE emulation nominally supports it, but these are
minor.) x86 and m68k disagree about
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error block st
The current code is actually dependent on having just one error
structure with a single source, as any change there would cause
migration issues.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, and how many errors can be
reported at th
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO
(currentl
--- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100
+++ b/DSDT.dsl2025-01-28 09:39:01.684836954 +0100
@@ -9,9 +9,9 @@
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x1516 (5398)
+ * Length 0x1542 (5442)
* Revision
On 17/2/25 13:50, Peter Maydell wrote:
Currently we hardcode at compile time whether the floatx80 default
Infinity value has the explicit integer bit set or not (x86 sets it;
m68k does not). To be able to compile softfloat once for all targets
we'd like to move this setting to runtime.
Define a
Em Fri, 21 Feb 2025 13:23:06 +0100
Mauro Carvalho Chehab escreveu:
> Em Fri, 21 Feb 2025 10:21:27 +
> Jonathan Cameron escreveu:
>
> > On Fri, 21 Feb 2025 07:38:23 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Em Mon, 3 Feb 2025 16:22:36 +0100
> > > Igor Mammedov escreveu:
> > >
On Fri, Feb 21, 2025 at 11:18:33AM -0300, Daniel Henrique Barboza wrote:
> At this moment ziccrse is a TCG always enabled named feature for
> priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
> the KVM driver update ziccrse as well, turning it on/off depending on
> host setti
On 2/20/25 06:45, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v3 01/28] hw/intc/aspeed: Support setting different
memory and register size
Hello Jamin,
On 2/13/25 04:35, Jamin Lin wrote:
According to the AST2700 datasheet, the INTC(CPU DIE) controller has
16KB
(0x4000) of register space,
On Fri, 21 Feb 2025 at 14:42, Philippe Mathieu-Daudé wrote:
>
> On 17/2/25 13:50, Peter Maydell wrote:
> > Currently we hardcode at compile time whether the floatx80 default
> > Infinity value has the explicit integer bit set or not (x86 sets it;
> > m68k does not). To be able to compile softfloa
On Fri, Feb 14, 2025 at 1:52 PM Clément Chigot wrote:
>
> Hi Alistair,
>
> I've an issue following this patch. When the system is reset (e.g
> using HTIF syscalls), the fifo might not be empty and thus some
> characters are lost.
> I discovered it on a Windows host. But by extending
> "TX_INTERRUP
Thomas Huth writes:
> On 21/02/2025 15.06, Peter Maydell wrote:
>> On my local machine, for a debug build, sbsaref_alpine takes
>> nearly 900s:
>> $ (cd build/x86 && ./pyvenv/bin/meson test --setup thorough --suite
>> func-thorough func-aarch64-aarch64_sbsaref_alpine
>> )
>> 1/1 qemu:func-thoroug
At this moment ziccrse is a TCG always enabled named feature for
priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
the KVM driver turn ziccrse off if the extension isn't available in the
host, and we'll need an ext_ziccrse flag in the CPU state for that.
Create an exclusive
Hi,
In this series we made changes in the commit msg in patch 2 to make it
less ambiguious what the KVM driver will do with ziccrse.
No other changes made. Patches based on alistair/riscv_to_apply.next.
Changes from v2:
- patch 2:
- reworded commit message
- v2 link:
https://lore.kernel.org/
Update headers to retrieve the latest KVM caps for RISC-V.
Signed-off-by: Daniel Henrique Barboza
---
include/standard-headers/linux/ethtool.h | 4 +
include/standard-headers/linux/fuse.h | 76 ++-
.../linux/input-event-codes.h | 1 +
include/standa
Expose ziccrse, zabha and svvptc.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 23ce779359..471fd554b3 100644
--- a/target/riscv
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/memory.rs | 30 --
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs
index b791ca6d87f..26cc8de0cf2
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the
> pasid entry and track PASID usage and future PASID tagged DMA address
> translation support in vIOMMU.
>
> VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged
The softfloat (i.e. TCG) specific handling for the FPCR
and FPSR is abstracted behind five functions:
arm_set_default_fp_behaviours
arm_set_ah_fp_behaviours
vfp_get_fpsr_from_host
vfp_clear_float_status_exc_flags
vfp_set_fpsr_to_host
Currently we rely on the first two calling softfloat functi
On Fri, Feb 21, 2025 at 04:53:26PM +, Peter Maydell wrote:
> On Fri, 21 Feb 2025 at 14:02, Wei Liu wrote:
> >
> > Hi,
> >
> > Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
> > Hypervisor (MSHV for short). The driver is being upstreamed. The first
> > supported VMM
On Fri, 21 Feb 2025 at 18:02, Alex Bennée wrote:
>
> Peter Maydell writes:
>
> > When we added Secure EL2 support, we missed that this needs an update
> > to the access code for the EL3 physical timer registers. These are
> > supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
> >
> >
On 2/11/25 3:20 PM, Paolo Savini wrote:
This commit improves the performance of QEMU when emulating strided vector
loads and stores by substituting the call for the helper function with the
generation of equivalend TCG operations.
s/equivalend/equivalent
Signed-off-by: Paolo Savini
---
On Fri, Feb 21, 2025 at 1:42 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Wed, Feb 19, 2025 at 8:22 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > "The text handler you add looks just like the existing latex handler.
> Does
> >> > LaTeX output lack "little hea
On 2/21/25 09:36, Wei Liu wrote:
This patch series attempts to make the instruction emulator in HVF a common
component for the i386 target. It removes HVF specific code by either using a
set of hooks or moving it to better locations. The new incoming MSHV
accelerator will implement the hooks, and
From: Paolo Bonzini
Without it, recent bindgen will give an error
error: extern block cannot be declared unsafe
if rustc is not new enough to support the "unsafe extern" construct.
Cc: qemu-r...@nongnu.org
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
Message-ID: <20250206111514.
Signed-off-by: Paolo Bonzini
---
meson.build| 7 ---
rust/qemu-api/src/timer.rs | 24 +---
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/meson.build b/meson.build
index 8ed10b6624e..16c76c493f3 100644
--- a/meson.build
+++ b/meson.build
On 21/2/25 17:01, Alex Bennée wrote:
While running the new GPU tests it was noted that the proprietary
nVidia driver barfed when run under the sanitiser:
2025-02-20 11:13:08,226: [11:13:07.782] Output 'headless' attempts
EOTF mode SDR and colorimetry mode default.
2025-02-20 11:13:08,22
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/irq.rs| 15 ++-
rust/qemu-api/src/sysbus.rs | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/rust/qemu-api/src/irq.rs b/rust/qemu-api/src/irq.rs
index d1c9dc96eff..aec2825b2f9 100644
--- a/rust/qemu-api/src/
The following patches are queued for QEMU stable v9.2.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-02-23, and the release is planned for 2025-02-24:
https://wiki.qemu.org/Planning/9.2
This is a short-cycle release to fix issues with the uploaded 9.2.1
t
From: Laurent Vivier
Add VHOST_USER_PROTOCOL_F_SHARED_OBJECT and
VHOST_USER_PROTOCOL_F_DEVICE_STATE protocol feature maps to
the virtio introspection.
Cc: jonah.pal...@oracle.com
Fixes: 160947666276 ("vhost-user: add shared_object msg")
Cc: aest...@redhat.com
Fixes: cda83adc62b6 ("vhost-user: In
From: Michael Roth
The current logic scans qemu.git/subprojects/ from *.wrap files to
determine whether or not to include the associated directories in the
release tarballs. However, the script assumes that it is being run from
the top-level of the source directory, which may not always be the ca
From: Zhenzhong Duan
When iommufd_cdev_ram_block_discard_disable() fails for whatever reason,
errp should be set or else SIGSEV is triggered in vfio_realize() when
error_prepend() is called.
By this chance, use the same error message for both legacy and iommufd
backend.
Fixes: 5ee3dc7af785 ("vf
From: Mikael Szreder
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Cc: qemu-sta...@nongnu.org
Fixes: 0bba7572d40d ("target/sparc: Perform
From: Fabiano Rosas
ASAN detected a leak when running the ahci-test
/ahci/io/dma/lba28/retry:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in __vasprintf_internal
#2 in vasprintf
#3 in g_vasprintf
#4 in g_strdup_vprintf
#5 in g_strdup_printf
From: Fabiano Rosas
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the sta
From: Peter Krempa
Commit 7452162adec25c10 introduced 'qom-path' argument to BLOCK_IO_ERROR
event but when the event is instantiated in 'send_qmp_error_event()' the
arguments for 'device' and 'qom_path' in
qapi_event_send_block_io_error() were reversed :
Generated code for sending event:
void
Inspired by the same-named type in Linux. This type provides the compiler
with a correct view of what goes on with FFI types. In addition, it
separates the glue code from the bindgen-generated code, allowing
traits such as Send, Sync or Zeroable to be specified independently
for C and Rust struct
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/hpet.rs | 2 +-
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/sysbus.rs| 25 ++---
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/memory.rs | 2 +-
rust/qemu-api/src/qdev.rs | 6 +++---
rust/qemu-api/src/qom.rs | 35 ++-
4 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/rust/
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/chardev.rs | 8 ++--
rust/qemu-api/src/qdev.rs | 1 +
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs
index 26cc8de0cf2..
Update the code in net/slirp.c to be compatible with
libslirp 4.9.0, which deprecated slirp_pollfds_fill()
and started using slirp_os_socket type for sockets
(which is a 64-bit integer on win64) for all callbacks
starting with version 6 of the interface.
Signed-off-by: Michael Tokarev
Reviewed-by
Peter Maydell writes:
> When we added Secure EL2 support, we missed that this needs an update
> to the access code for the EL3 physical timer registers. These are
> supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
>
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Peter Maydell
> ---
On Fri, Feb 21, 2025 at 05:36:39PM +0100, Paolo Bonzini wrote:
> On 2/21/25 09:36, Wei Liu wrote:
> > This patch series attempts to make the instruction emulator in HVF a common
> > component for the i386 target. It removes HVF specific code by either using
> > a
> > set of hooks or moving it to b
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Signed-off-by: Konstantin Shkolnyy
---
Changes in V
On 2/21/25 17:14, Alex Bennée wrote:
The following organisations appear on the US sanctions list:
Yadro: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=41125
ISPRAS: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=50890
As a result maintainers interacting with such entities
From: Thomas Huth
The FreeBSD job started to fail since the 14-1 image disappeared
from the cloud. Update the job to v14.2 to fix it.
Message-ID: <20250211120817.35050-1-th...@redhat.com>
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
(cherry picked from commit 66a1b4991c32e370a4e0
From: Peter Maydell
The SMC91C111 includes an MMU Command register which permits
the guest to remove entries from the RX FIFO. The datasheet
does not specify what happens if the guest tries to do this
when the FIFO is already empty; there are no status registers
containing error bits which might
From: Volker Rümelin
Windows only:
The libSDL2 Windows message loop needs the libSDL2 Windows low
level keyboard hook procedure to grab the left and right Windows
keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
Since SDL2 2.30.4 the SDL2 keyboard hook procedure also filters
o
Add a derive macro that makes it easy to peel off all the layers of
specialness (UnsafeCell, MaybeUninit, etc.) and just get a pointer
to the wrapped type; and likewise add them back starting from a
*mut.
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 8 ++--
rust/qemu-api-m
target/arm/vfp_helper.c is almost entirely TCG-specific code,
guarded by #ifdef CONFIG_TCG. The only parts that aren't
TCG-specific are the handling of the FPSCR/FPSR/FPCR registers.
(I noticed this while I was working on the FEAT_AFP code, and
it felt a bit awkward but I left it as-is at the time.
Most of the target/arm/vfp_helper.c file is purely TCG helper code,
guarded by #ifdef CONFIG_TCG. Move this into a new file in
target/arm/tcg/.
This leaves only the code relating to getting and setting the
FPCR/FPSR/FPSCR in the original file. (Some of this also is
TCG-only, but that needs more c
Currently the helper_vfp_get_fpscr() and helper_vfp_set_fpscr()
functions do the actual work of updating the FPSCR, and we have
wrappers vfp_get_fpscr() and vfp_set_fpscr() which we use for calls
from other QEMU C code.
Flip these around so that it is vfp_get_fpscr() and vfp_set_fpscr()
which do t
The vfp_helper.c in the target/arm directory now only has
code for handling FPSCR/FPCR/FPSR in it, and no helper
functions. Rename it to vfp_fpscr.c; this helps keep it
distinct from tcg/vfp_helper.c.
Signed-off-by: Peter Maydell
---
target/arm/{vfp_helper.c => vfp_fpscr.c} | 2 +-
target/arm/me
The DSDT table will also be affected by such change.
Signed-off-by: Mauro Carvalho Chehab
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8
From: Clement Mathieu--Drif
PASID value must be used by devices as a key (or part of a key)
when populating their ATC with the IOTLB entries returned by the IOMMU.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/inte
From: Clement Mathieu--Drif
This will be useful for devices that support ATS
and need to store entries in an ATC (device IOTLB).
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
inde
From: Clement Mathieu--Drif
As the SVM-capable devices will need to cache translations, we provide
an first implementation.
This cache uses a two-level design based on hash tables.
The first level is indexed by a PASID and the second by a virtual addresse.
Signed-off-by: Clement Mathieu--Drif
From: Clement Mathieu--Drif
We add a convenient way to initialize an device-iotlb notifier.
This is meant to be used by ATS-capable devices.
pci_device_iommu_memory_region_pasid is introduces in this commit and
will be used in several other SVM-related functions exposed in
the PCI API.
Signed-o
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests/
On 21.02.25 03:25, Chenyi Qiang wrote:
On 2/21/2025 3:39 AM, David Hildenbrand wrote:
On 20.02.25 17:13, Jean-Philippe Brucker wrote:
For Arm CCA we'd like the guest_memfd discard notifier to call the IOMMU
notifiers and create e.g. VFIO mappings. The default VFIO discard
notifier isn't suffi
From: Clement Mathieu--Drif
This patch set belongs to a list of series that add SVM support for VT-d.
Here we focus on implementing ATS support in the IOMMU and adding a
PCI-level API to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 74 --
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
From: Clement Mathieu--Drif
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added (define
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 17 -
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a360119fbe..d3772
From: Clement Mathieu--Drif
The cached is_master value is necessary to know if a device is
allowed to issue ATS requests or not.
This behavior is implemented in an upcoming patch.
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pci.c| 25 +++--
include/hw/pc
From: Clement Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed-of
From: Clement Mathieu--Drif
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 24
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h | 5 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pci
From: Clement Mathieu--Drif
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5.
This is needed by devices that support ATS.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/i38
From: Clement Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
We decided not to use the existing translation operation for 2 reasons.
First, ATS is d
From: Clement Mathieu--Drif
pasid_enabled checks whether the capability is
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clement Mathieu--Drif
---
hw/pci/pcie.c | 9 +
include/hw/pci/pcie.h | 2 ++
2 fil
On Fri, Feb 21, 2025 at 09:26:23AM -0300, Daniel Henrique Barboza wrote:
> We're missing scounteren and senvcfg CSRs, both already present in the
> KVM UAPI.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --gi
On Fri, Feb 21, 2025 at 09:26:22AM -0300, Daniel Henrique Barboza wrote:
> We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but
> in no particular order and missing some of them (like env->mstatus).
>
> Create a helper to do that, unclogging reset_vcpu(), and initialize
> env->
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