On 03/02/2025 10.26, Cédric Le Goater wrote:
The test sequence boots from kernel a sam460ex machine with a
virtio-net device to check PCI.
The buildroot is built with config :
BR2_powerpc=y
BR2_powerpc_440fp=y
and the kernel with the '44x/canyonlands' deconfig and virtio support.
Cc: BA
On 11/2/25 13:13, Daniel P. Berrangé wrote:
On Tue, Feb 11, 2025 at 01:08:17PM +0100, Thomas Huth wrote:
The FreeBSD job started to fail since the 14-1 image disappeared
from the cloud. Update the job to v14.2 to fix it.
Signed-off-by: Thomas Huth
---
.gitlab-ci.d/cirrus.yml | 2 +-
1 file
On 04/02/25 11:15AM, Jonathan Cameron wrote:
On Mon, 3 Feb 2025 17:14:45 +0530
Sweta Kumari wrote:
Signed-off-by: Sweta Kumari
Reviewed-by: Alok Rathore
Reviewed-by: Krishna Kanth Reddy
Hi Sweta,
Thanks for the patch. Great to see someone working on these
features. As in previous threa
On Tue, Feb 11, 2025 at 01:36:35PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/2/25 13:13, Daniel P. Berrangé wrote:
> > On Tue, Feb 11, 2025 at 01:08:17PM +0100, Thomas Huth wrote:
> > > The FreeBSD job started to fail since the 14-1 image disappeared
> > > from the cloud. Update the job to v14.2
The vulkan test currently fails if the egl-headless device is not
available. Let's add a proper check to skip the test in this case.
Fixes: 3d30f882ce ("tests/functional: extend test_aarch64_virt with vulkan
test")
Reported-by: Cornelia Huck
Acked-by: Alex Bennée
Tested-by: Cornelia Huck
Messa
From: Daniel P. Berrangé
Rather than a giant sed command with a hardcoded list of env var name,
we can now use the new(ish) cirrus-vars command that libvirt has added
to the 'cirrus-run' container.
Signed-off-by: Daniel P. Berrangé
Message-ID: <20241204194807.1472261-3-berra...@redhat.com>
Sign
On Sat, 1 Feb 2025 at 16:40, Peter Maydell wrote:
>
> When FPCR.AH is set, various behaviours of AArch64 floating point
> operations which are controlled by softfloat config settings change:
> * tininess and ftz detection before/after rounding
> * NaN propagation order
> * result of 0 * Inf + N
On 2/11/25 12:37, Thomas Huth wrote:
On 03/02/2025 10.26, Cédric Le Goater wrote:
The test sequence boots from kernel a sam460ex machine with a
virtio-net device to check PCI.
The buildroot is built with config :
BR2_powerpc=y
BR2_powerpc_440fp=y
and the kernel with the '44x/canyonlands
On 2/6/25 14:14, Cédric Le Goater wrote:
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Hello,
Under certain circumstances, a MMIO region of a device fails to map
because the region is outside the supported IOVA ranges of the VM. In
this case, PCI peer
On 11.02.2025 16:00, Cédric Le Goater wrote:
On 2/11/25 15:37, Maciej S. Szmigiero wrote:
On 10.02.2025 18:24, Cédric Le Goater wrote:
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This property allows configuring whether to start the config load only
after all ite
On Mon, Jan 27, 2025 at 07:29:21PM +0100, Andrea Bolognani wrote:
> Changes from [v1]:
>
> * adopt a completely different, more general approach.
>
> [v1] https://mail.gnu.org/archive/html/qemu-devel/2024-12/msg00459.html
>
> Andrea Bolognani (3):
> binfmt: Shuffle things around
> binfmt: Nor
On 11/2/25 14:06, Peter Maydell wrote:
In do_cvttq() we set env->error_code with what is supposed to be a
set of FPCR exception bit values. However, if the set of float
exception flags we get back from softfloat for the conversion
includes a flag which is not one of the three we expect here
(inv
On Mon, Feb 03, 2025 at 01:43:46PM +0100, Thomas Huth wrote:
All other vhost-user tests here use modern virtio, too, so let's
adjust the vhost-user-net test accordingly.
Signed-off-by: Thomas Huth
---
tests/qtest/vhost-user-test.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewe
On 2/11/25 05:06, Peter Maydell wrote:
In do_cvttq() we set env->error_code with what is supposed to be a
set of FPCR exception bit values. However, if the set of float
exception flags we get back from softfloat for the conversion
includes a flag which is not one of the three we expect here
(inv
On Tue, Feb 11, 2025 at 11:25:05AM +0100, Victor Toso wrote:
> Hi,
>
> On Thu, Jan 16, 2025 at 09:59:52PM +, Daniel P. Berrangé wrote:
> > Pause here if you've read enough for now.
> >
> >
> >
> > As a way to validate these thoughts, I spent a day to mock up a demo
> > of a QA
On Tue, 11 Feb 2025, Thomas Huth wrote:
On 03/02/2025 10.26, Cédric Le Goater wrote:
The test sequence boots from kernel a sam460ex machine with a
virtio-net device to check PCI.
The buildroot is built with config :
BR2_powerpc=y
BR2_powerpc_440fp=y
and the kernel with the '44x/canyonla
qemu/ tags/pull-vfio-20250211
for you to fetch changes up to be7d8579eb5758c0edf81eb068017a56471a77e0:
vfio: Remove superfluous error report in vfio_listener_region_add()
(2025-02-11 14:15:19 +0100)
vfio queue:
* Coverity
From: Tomita Moeko
Device may only expose a specific portion of PCI config space through a
region in a BAR, such behavior is seen in igd GGC and BDSM mirrors in
BAR0. To handle these, config_offset is introduced to allow mirroring
arbitrary region in PCI config space.
Signed-off-by: Tomita Moeko
Depending on the configuration of the host and VM, a passthrough
device may generate recurring DMA mapping errors at runtime. In such
cases, reporting the issue once is sufficient.
We have already the warn/error_report_once() routines taking a format
and arguments. Using the same design pattern, a
For pseries machines, commit 567b5b309abe ("vfio/pci: Relax DMA map
errors for MMIO regions") introduced 2 error reports to notify the
user of MMIO mapping errors. Consolidate both code paths under one.
Cc: Harsh Prateek Bora
Cc: Shivaprasad G Bhat
Reviewed-by: Harsh Prateek Bora
Reviewed-by: A
This is to be consistent with other reported errors related to vIOMMU
devices.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Williamson
Link: https://lore.kernel.org/qemu-devel/20250206131438.1505542-3-...@redhat.com
Signed-off-by: Cédric Le Goater
---
hw/vfio/pci.c | 2 +-
1 file chan
This helper will be useful in the listener handlers to extract the
VFIO device from a memory region using memory_region_owner(). At the
moment, we only care for PCI passthrough devices. If the need arises,
we will add more.
Reviewed-by: Alex Williamson
Link: https://lore.kernel.org/qemu-devel/202
When the IOMMU address space width is smaller than the physical
address width, a MMIO region of a device can fail to map because the
region is outside the supported IOVA ranges of the VM. In this case,
PCI peer-to-peer transactions on BARs are not supported. This can
occur with the 39-bit IOMMU add
Currently, the mapping handlers of the IOMMU backends, VFIO IOMMU Type
1 aka. legacy and IOMMUFD, return an errno and also report an error.
This can lead to excessive log messages at runtime for recurring DMA
mapping errors. Since these errors are already reported by the callers
in the vfio_contain
The risk is mainly theoretical since the applied bit mask will keep
the 'ggms' shift value below 3. Nevertheless, let's use a 64 bit
integer type and resolve the coverity issue.
Resolves: Coverity CID 1585908
Fixes: 1e1eac5f3dcd ("vfio/igd: canonicalize memory size calculations")
Reviewed-by: Alex
From: Tomita Moeko
Declare generic vfio_generic_{window_address,window_data,mirror}_quirk
in newly created pci_quirks.h so that they can be used elsewhere, like
igd.c.
Signed-off-by: Tomita Moeko
Reviewed-by: Alex Williamson
Link: https://lore.kernel.org/r/20250104154219.7209-2-tomitamo...@gma
From: Zhenzhong Duan
When iommufd_cdev_ram_block_discard_disable() fails for whatever reason,
errp should be set or else SIGSEV is triggered in vfio_realize() when
error_prepend() is called.
By this chance, use the same error message for both legacy and iommufd
backend.
Fixes: 5ee3dc7af785 ("vf
Rephrase a bit the ending comment about how errors are handled
depending on the phase in which vfio_listener_region_add() is called.
Reviewed-by: Alex Williamson
Link: https://lore.kernel.org/qemu-devel/20250206131438.1505542-4-...@redhat.com
Signed-off-by: Cédric Le Goater
---
hw/vfio/common.c
From: Tomita Moeko
With the introduction of config_offset field, VFIOConfigMirrorQuirk can
now be used for those mirrored register in igd bar0. This eliminates
the need for the macro intoduced in 1a2623b5c9e7 ("vfio/igd: add macro
for declaring mirrored registers").
Signed-off-by: Tomita Moeko
When FPCR.AH is 1, the behaviour of some instructions changes:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2, BFMLALB, BFMLALT
* SVE BFCVT, BFCVTNT, BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
* SME BFCVT, BFCVTN, BFMLAL, BFMLSL (these are all in SME2 which
QEMU does not yet implement)
* FRECPE, FRECPS, FRECPX, F
Implement the FPCR.AH == 1 semantics for vector FMIN/FMAX, by
creating new _ah_ versions of the gvec helpers which invoke the
scalar fmin_ah and fmax_ah helpers on each element.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
t
Currently in softfloat we canonicalize input denormals and so the
code that implements floating point operations does not need to care
whether the input value was originally normal or denormal. However,
both x86 and Arm FEAT_AFP require that an exception flag is set if:
* an input is denormal
*
We are going to need to generate different code in some cases when
FPCR.AH is 1. For example:
* Floating point neg and abs must not flip the sign bit of NaNs
* some insns (FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, and various
BFCVT and BFM bfloat16 ops) need to use a different float_status
On Wed, Feb 5, 2025 at 3:58 PM Jonah Palmer wrote:
>
> An issue arises from aliased memory mappings in the guest, where
> different GPAs map to the same HVA. For example:
>
> - GPA1->HVA1
> - GPA2->HVA1
>
> When these mappings exist in the IOVA->HVA tree, a lookup by an HVA
> backed by guest mem
Handle FPCR.NEP in the operations handled by do_cvtf_scalar().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
get_float_exception_flags() returns exception flags,
which are distinct from the FPCR bits used as error code.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20250211130626.3940412-1-peter.mayd...@linaro.org>
---
target/alpha/fpu_helper.c | 15 +++
1 file changed, 7 insertions(
From: Richard Henderson
Replace with fp_status[FPST_A64_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2
* SVE BFCVT, BFCVTNT
so that they get the required behaviour changes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 27 +--
target/arm/tcg/tran
do_fp3_scalar_idx() is used only for the FMUL and FMULX scalar by
element instructions; these both need to merge the result with the Rn
register when FPCR.NEP is set.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 ins
In do_cvttq() we set env->error_code with what is supposed to be a
set of FPCR exception bit values. However, if the set of float
exception flags we get back from softfloat for the conversion
includes a flag which is not one of the three we expect here
(invalid_cvti, invalid, inexact) then we will
When FPCR.AH = 1, some of the cumulative exception flags in the FPSR
behave slightly differently for A64 operations:
* IDC is set when a denormal input is used without flushing
* IXC (Inexact) is set when an output denormal is flushed to zero
Update vfp_get_fpsr_from_host() to do this.
Note tha
For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use
FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get
the required behaviour changes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.h | 13
target/arm/tcg/trans
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.
In this commit we
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c | 25 +
target/arm/tc
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we
can enable FEAT_AFP for '-cpu max', and document that we support it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 ins
Implement the FPCR.AH semantics for the SVE FMAXV and FMINV
vector-reduction-to-scalar max/min operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 +++
target/arm/tcg/sve_helper.c| 43 +-
tar
Handle FPCR.NEP for the 1-input scalar operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran
The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/sve_helper.c| 18 ++
ffaf7f0376f8040ce9068d71ae9ae8722505c42e:
Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of
https://gitlab.com/stsquad/qemu into staging (2025-02-10 13:26:17 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-202
From: Richard Henderson
Select on index instead of pointer.
No functional change.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/mve_helper.c | 40 +
From: Richard Henderson
Replace with fp_status[FPST_AH_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 2
When FPCR.AH == 1, floating point FMIN and FMAX have some odd special
cases:
* comparing two zeroes (even of different sign) or comparing a NaN
with anything always returns the second argument (possibly
squashed to zero)
* denormal outputs are not squashed to zero regardless of FZ or FZ16
FPCR.AH == 1 mandates that taking the absolute value of a NaN should
not change its sign bit. This means we can no longer use
gen_vfp_abs*() everywhere but must instead generate slightly more
complex code when FPCR.AH is set.
Implement these semantics for scalar FABS and FABD. This change also
a
Implement the increased precision variation of FRECPE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRecipEstimate() and
RecipEstimate() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/vfp_helper.c | 54 +++
Handle FPCR.NEP merging for scalar FABS and FNEG; this requires
an extra parameter to do_fp1_scalar_int(), since FMOV scalar
does not have the merging behaviour.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 27 ---
1 fi
FPCR.AH == 1 mandates that negation of a NaN value should not flip
its sign bit. This means we can no longer use gen_vfp_neg*()
everywhere but must instead generate slightly more complex code when
FPCR.AH is set.
Make this change for the scalar FNEG and for those places in
translate-a64.c which w
Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH == 1.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/t
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFMLALB, BFMLALT
* SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
so that they get the required behaviour changes.
We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour
rather than a bool is_fp16; existing callsites now select
FPST_FPCR_F
Remove all instances of _fd_ from the migration generic code. These
functions have grown over time and the _fd_ part is now just
confusing.
migration_fd_error() -> migration_error() makes it a little vague, so
change it to migration_set_error_state().
Signed-off-by: Fabiano Rosas
---
migration/
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitive if written
out longhand, we condense th
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN
in FMLSL by element and vector, using the usual trick of
negating by XOR when AH=0 and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and do
From: Richard Henderson
Replace with fp_status[FPST_A32_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
It's possible that the migration is cancelled during
migration_switchover_start(). In that case, don't set the migration
state FAILED in migration_completion().
Fixes: 3dde8fdbad ("migration: Merge precopy/postcopy on switchover start")
Signed-off-by: Fabiano Rosas
---
migration/migration.c | 4
From: Richard Henderson
Replace with fp_status[FPST_STD_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
Currently we implement BFCVT scalar via do_fp1_scalar(). This works
even though BFCVT is a narrowing operation from 32 to 16 bits,
because we can use write_fp_sreg() for float16. However, FPCR.NEP
support requires that we use write_fp_hreg_merging() for float16
outputs, so we can't continue to bor
The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field,
so we can select the correct behaviour.
Because the operand is known to be negative, negating the operand
is the same as taking the absolute value. Defer this to
Implement the FPCR.AH semantics for the SVE FMAX and FMIN
operations that take two vector operands.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c |
Make SVE FABS honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 inse
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in the vector versions of FRECPS and FRSQRTS, by implementing
new vector wrappers that call the _ah_ scalar helpers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this in the same way we did for
the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field
passed to the helper and using that to decide whether to negate the
values.
The construction o
From: Richard Henderson
Sink common code from the callers into do_fmlal
and do_fmlal_idx. Reorder the arguments to minimize
the re-sorting from the caller's arguments.
Signed-off-by: Richard Henderson
Message-id: 20250129013857.135256-35-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
From: Richard Henderson
Replace with fp_status[FPST_STD].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c|
On 2/11/25 16:57, Maciej S. Szmigiero wrote:
On 11.02.2025 16:00, Cédric Le Goater wrote:
On 2/11/25 15:37, Maciej S. Szmigiero wrote:
On 10.02.2025 18:24, Cédric Le Goater wrote:
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This property allows configuring wheth
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/tra
For the x86 and the Arm FEAT_AFP semantics, we need to be able to
tell the target code that the FPU operation has used an input
denormal. Implement this; when it happens we set the new
float_flag_denormal_input_used.
Note that we only set this when an input denormal is actually used by
the operat
Make the SVE FABD insn honour the FPCR.AH "don't negate the sign
of a NaN" semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 7 +++
target/arm/tcg/sve_helper.c| 22 ++
target/arm/tcg/translate-sve.c | 2 +-
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need
Handle FPCR.NEP for the 3-input scalar operations which use
do_fmla_scalar_idx() and do_fmadd(), by making them call the
appropriate write_fp_*reg_merging() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 12 ++--
1 file change
The Armv8.7 FEAT_AFP feature defines three new control bits in
the FPCR:
* FPCR.AH: "alternate floating point mode"; this changes floating
point behaviour in a variety of ways, including:
- the sign of a default NaN is 1, not 0
- if FPCR.FZ is also 1, denormals detected after rounding
Make SVE FNEG honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 inse
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
The construction of neg_imag and neg_real were done to make it easy
From: Richard Henderson
The negation step in FCMLA by index mustn't negate a NaN when
FPCR.AH is set. Use the same approach as vector FCMLA of
passing in FPCR.AH and using it to select whether to negate
by XOR or by the muladd negate_product flag.
Signed-off-by: Richard Henderson
Message-id: 20
Implement the increased precision variation of FRSQRTE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRSqrtEstimate() and
RecipSqrtEstimate() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/vfp_helper.c | 7
From: Richard Henderson
The negation step in SVE FCMLA mustn't negate a NaN when FPCR.AH is
set. Use the same approach as we did for A64 FCMLA of passing in
FPCR.AH and using it to select whether to negate by XOR or by the
muladd negate_product flag.
Signed-off-by: Richard Henderson
Message-id
Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects
flushing of single and double precision denormal inputs to zero for
AArch64 floating point instructions. (For half-precision, the
existing FPCR.FZ16 control remains the only one.)
FPCR.FIZ differs from FPCR.FZ in that if we flush
From: Richard Henderson
Move ARMFPStatusFlavour to cpu.h with which to index
this array. For now, place the array in an anonymous
union with the existing structures. Adjust the order
of the existing structures to match the enum.
Simplify fpstatus_ptr() using the new array.
Signed-off-by: Rich
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need
When FPCR.AH is set, various behaviours of AArch64 floating point
operations which are controlled by softfloat config settings change:
* tininess and ftz detection before/after rounding
* NaN propagation order
* result of 0 * Inf + NaN
* default NaN value
When the guest changes the value of th
Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_fcvtxn[] array for
the FCVTXN (vector) in
From: Richard Henderson
Pass ARMFPStatusFlavour index instead of fp_status[FOO].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vfp_helper.c | 10 +-
1
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
The float_muladd_negate_product flag produces the same result
as negating either of the multiplication operands, assuming
neither of the operands are NaNs. But s
For FEAT_AFP, we want to emit different code when FPCR.NEP is set, so
that instead of zeroing the high elements of a vector register when
we write the output of a scalar operation to it, we instead merge in
those elements from one of the source registers. Since this affects
the generated code, we
From: Richard Henderson
Replace with fp_status[FPST_AH].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 6 +++---
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS
(indexed). We do this by creating 6 new helpers, which allow us to
do the negation either by XOR (for AH=0) or by muladd flags
(for AH=1).
Signed-off-by: Peter Maydell
[PMM: Mostly from RTH's patch; error in index order into fn
From: Richard Henderson
Replace with fp_status[FPST_A64].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c|
Fabiano Rosas writes:
> Update the migrate_cancel command documentation with a few words about
> postcopy and the expected state of the machine after migration.
>
> Signed-off-by: Fabiano Rosas
> ---
> qapi/migration.json | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the
SVE FMLS (vector) insns, by providing new helpers for the AH=1 case
which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions
that do the work.
The float*_muladd functions have a flags argument that can
perform option
From: Richard Henderson
The negation step in FCMLA mustn't negate a NaN when FPCR.AH
is set. Handle this by passing FPCR.AH to the helper via the
SIMD data field, and use this to select whether to do the
negation via XOR or via the muladd negate_product flag.
Signed-off-by: Richard Henderson
Me
From: Richard Henderson
Replace with fp_status[FPST_A32]. As this was the last of the
old structures, we can remove the anonymous union and struct.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-15-richard.hender...@linaro.org
[PMM: twea
1 - 100 of 278 matches
Mail list logo
