Hi; this pullreq contains only my FEAT_AFP/FEAT_RPRES patches (plus a fix for a target/alpha latent bug that would otherwise be revealed by the fpu changes), because 68 patches is already longer than I prefer to send in at one time...
thanks -- PMM The following changes since commit ffaf7f0376f8040ce9068d71ae9ae8722505c42e: Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu into staging (2025-02-10 13:26:17 -0500) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250211 for you to fetch changes up to ca4c34e07d1388df8e396520b5e7d60883cd3690: target/arm: Sink fp_status and fpcr access into do_fmlal* (2025-02-11 16:22:08 +0000) ---------------------------------------------------------------- target-arm queue: * target/alpha: Don't corrupt error_code with unknown softfloat flags * target/arm: Implement FEAT_AFP and FEAT_RPRES ---------------------------------------------------------------- Peter Maydell (49): target/alpha: Don't corrupt error_code with unknown softfloat flags fpu: Add float_class_denormal fpu: Implement float_flag_input_denormal_used fpu: allow flushing of output denormals to be after rounding target/arm: Define FPCR AH, FIZ, NEP bits target/arm: Implement FPCR.FIZ handling target/arm: Adjust FP behaviour for FPCR.AH = 1 target/arm: Adjust exception flag handling for AH = 1 target/arm: Add FPCR.AH to tbflags target/arm: Set up float_status to use for FPCR.AH=1 behaviour target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS target/arm: Use FPST_FPCR_AH for BFCVT* insns target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns target/arm: Add FPCR.NEP to TBFLAGS target/arm: Define and use new write_fp_*reg_merging() functions target/arm: Handle FPCR.NEP for 3-input scalar operations target/arm: Handle FPCR.NEP for BFCVT scalar target/arm: Handle FPCR.NEP for 1-input scalar operations target/arm: Handle FPCR.NEP in do_cvtf_scalar() target/arm: Handle FPCR.NEP for scalar FABS and FNEG target/arm: Handle FPCR.NEP for FCVTXN (scalar) target/arm: Handle FPCR.NEP for NEP for FMUL, FMULX scalar by element target/arm: Implement FPCR.AH semantics for scalar FMIN/FMAX target/arm: Implement FPCR.AH semantics for vector FMIN/FMAX target/arm: Implement FPCR.AH semantics for FMAXV and FMINV target/arm: Implement FPCR.AH semantics for FMINP and FMAXP target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX immediate target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX vector target/arm: Implement FPCR.AH handling of negation of NaN target/arm: Implement FPCR.AH handling for scalar FABS and FABD target/arm: Handle FPCR.AH in vector FABD target/arm: Handle FPCR.AH in SVE FNEG target/arm: Handle FPCR.AH in SVE FABS target/arm: Handle FPCR.AH in SVE FABD target/arm: Handle FPCR.AH in negation steps in SVE FCADD target/arm: Handle FPCR.AH in negation steps in FCADD target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insns target/arm: Handle FPCR.AH in negation step in FMLS (indexed) target/arm: Handle FPCR.AH in negation in FMLS (vector) target/arm: Handle FPCR.AH in negation step in SVE FMLS (vector) target/arm: Handle FPCR.AH in SVE FTSSEL target/arm: Handle FPCR.AH in SVE FTMAD target/arm: Enable FEAT_AFP for '-cpu max' target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper target/arm: Implement increased precision FRECPE target/arm: Implement increased precision FRSQRTE target/arm: Enable FEAT_RPRES for -cpu max Richard Henderson (19): target/arm: Handle FPCR.AH in vector FCMLA target/arm: Handle FPCR.AH in FCMLA by index target/arm: Handle FPCR.AH in SVE FCMLA target/arm: Handle FPCR.AH in FMLSL (by element and vector) target/arm: Handle FPCR.AH in SVE FMLSL (indexed) target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors) target/arm: Introduce CPUARMState.vfp.fp_status[] target/arm: Remove standard_fp_status_f16 target/arm: Remove standard_fp_status target/arm: Remove ah_fp_status_f16 target/arm: Remove ah_fp_status target/arm: Remove fp_status_f16_a64 target/arm: Remove fp_status_f16_a32 target/arm: Remove fp_status_a64 target/arm: Remove fp_status_a32 target/arm: Simplify fp_status indexing in mve_helper.c target/arm: Simplify DO_VFP_cmp in vfp_helper.c target/arm: Read fz16 from env->vfp.fpcr target/arm: Sink fp_status and fpcr access into do_fmlal* docs/system/arm/emulation.rst | 2 + include/fpu/softfloat-helpers.h | 11 + include/fpu/softfloat-types.h | 25 ++ target/arm/cpu-features.h | 10 + target/arm/cpu.h | 97 +++-- target/arm/helper.h | 26 ++ target/arm/internals.h | 6 + target/arm/tcg/helper-a64.h | 13 + target/arm/tcg/helper-sve.h | 120 ++++++ target/arm/tcg/translate-a64.h | 13 + target/arm/tcg/translate.h | 54 +-- target/arm/tcg/vec_internal.h | 35 ++ target/mips/fpu_helper.h | 6 + fpu/softfloat.c | 66 +++- target/alpha/cpu.c | 7 + target/alpha/fpu_helper.c | 2 + target/arm/cpu.c | 46 +-- target/arm/helper.c | 2 +- target/arm/tcg/cpu64.c | 2 + target/arm/tcg/helper-a64.c | 151 ++++---- target/arm/tcg/hflags.c | 13 + target/arm/tcg/mve_helper.c | 44 +-- target/arm/tcg/sme_helper.c | 4 +- target/arm/tcg/sve_helper.c | 367 ++++++++++++++----- target/arm/tcg/translate-a64.c | 782 ++++++++++++++++++++++++++++++++-------- target/arm/tcg/translate-sve.c | 193 +++++++--- target/arm/tcg/vec_helper.c | 387 ++++++++++++++------ target/arm/vfp_helper.c | 374 +++++++++++++++---- target/hppa/fpu_helper.c | 11 + target/i386/tcg/fpu_helper.c | 8 + target/mips/msa.c | 9 + target/ppc/cpu_init.c | 3 + target/rx/cpu.c | 8 + target/sh4/cpu.c | 8 + target/tricore/helper.c | 1 + tests/fp/fp-bench.c | 1 + fpu/softfloat-parts.c.inc | 127 +++++-- 37 files changed, 2325 insertions(+), 709 deletions(-)
