(cover-letter update I forgot on v2:)
This series now contains the two approches we've been discussing to
avoid the TLS termination error on the multifd_recv threads.
The source machine now ends the TLS session with gnutls_bye() and the
destination will consider a premature termination an error.
The correct way of calling qcrypto_tls_session_handshake() requires
calling qcrypto_tls_session_get_handshake_status() right after it so
there's no reason to have a separate method.
Refactor qcrypto_tls_session_handshake() to inform the status in its
own return value and alter the callers accordin
We're currently changing the way the source multifd migration handles
the shutdown of the multifd channels when TLS is in use to perform a
clean termination by calling gnutls_bye().
Older src QEMUs will always close the channel without terminating the
TLS session. New dst QEMUs treat an unclean te
We want to pass flags into qio_channel_tls_readv() but
qio_channel_readv_full_all_eof() doesn't take a flags argument.
No functional change.
Signed-off-by: Fabiano Rosas
---
hw/remote/mpqemu-link.c | 2 +-
include/io/channel.h| 2 ++
io/channel.c| 9 ++---
3 files changed, 9
Add a read flag that can inform a channel that it's ok to receive an
EOF at any moment. Channels that have some form of strict EOF
tracking, such as TLS session termination, may choose to ignore EOF
errors with the use of this flag.
This is being added for compatibility with older migration stream
Add a task dispatcher for gnutls_bye similar to the
qio_channel_tls_handshake_task(). The gnutls_bye() call might be
interrupted and so it needs to be rescheduled.
The migration code will make use of this to help the migration
destination identify a premature EOF. Once the session termination is
i
The multifd recv side has been getting a TLS error of
GNUTLS_E_PREMATURE_TERMINATION at the end of migration when the send
side closes the sockets without ending the TLS session. This has been
masked by the code not checking the migration error after loadvm.
Start ending the TLS session at multifd
QEMU's TLS session code provides no way to call gnutls_bye() to
terminate a TLS session. Callers of qcrypto_tls_session_read() can
choose to ignore a GNUTLS_E_PREMATURE_TERMINATION error by setting the
gracefulTermination argument.
The QIOChannelTLS ignores the premature termination error whenever
We're currently only checking the QEMUFile error after
qemu_loadvm_state(). This was causing a TLS termination error from
multifd recv threads to be ignored.
Start checking the migration error as well to avoid missing further
errors.
Regarding compatibility concerning the TLS termination error th
On 2/5/2025 4:52 PM, Steven Sistare wrote:
On 2/5/2025 4:28 PM, Peter Xu wrote:
On Wed, Feb 05, 2025 at 12:54:01PM -0800, Steve Sistare wrote:
qmp_migrate guarantees that cpr_channel is not null for
MIG_MODE_CPR_TRANSFER when cpr_state_save is called:
qmp_migrate()
if (s->paramet
This is now handled by the configs/targets/*.mak fragment.
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/alpha/cpu-param.h | 2 --
target/arm/cpu-param.h| 2 --
target/avr/cpu-param.h| 1 -
Require a 64-bit host binary to spawn a 64-bit guest.
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/meson.build b/meson.build
index e50a103f8a
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors are caught like so:
In file included from .../src/include/exec/cpu-defs.h:26,
from ../src/target/hppa/cpu.h:24,
from ../src/linu
Prasad Pandit writes:
> From: Prasad Pandit
>
> Migration capabilities are set in multiple '.start_hook'
> functions for various tests. Instead, consolidate setting
> capabilities in 'set_migration_capabilities()' function
> which is called from various 'test_*_common()' functions.
> While simpl
From: Helge Deller
The Diva GSP ("Guardian Service Processor") PCI boards are Remote
Management cards for PA-RISC machines. They come with built-in 16550A
UARTs for serial consoles and modem functionalities, as well as a
mailbox-like memory area for hardware auto-reboot functionality.
Latest ge
From: Helge Deller
Until now we used a standard serial-pci device to emulate a HP serial
console. This worked nicely with 32-bit Linux and 32-bit HP-UX, but
64-bit HP-UX crashes with it and expects either a Diva GSP card, or a real
64-bit capable PCI graphic card (which we don't have yet).
In or
On 7 February 2025 15:37:40 GMT, Sean Christopherson wrote:
>On Fri, Feb 07, 2025, David Woodhouse wrote:
>> From: David Woodhouse
>>
>> At the time kvm_xen_init() is called, hyperv_enabled() doesn't yet work, so
>> the correct MSR index to use for the hypercall page isn't known.
>>
>> Rather t
From: Helge Deller
Update to lastest SeaBIOS-hppa which sets up the
LMMIO range for the internal artist graphic card.
Signed-off-by: Helge Deller
---
roms/seabios-hppa | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/roms/seabios-hppa b/roms/seabios-hppa
index 1c516b4813..33
From: Helge Deller
Do not create the artist graphic card if the user disabled it
with "-global artist.disable=true" on the command line.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa
From: Helge Deller
Each Astro on 64-bit machines supports up to four LMMIO regions.
Those regions are used by graphic cards and other PCI devices which
need to map huge memory areas. The LMMIO regions are configured and
set up by SeaBIOS-hppa and then used as-is by the operating systems
(Linux, H
Require a 64-bit host binary to spawn a 64-bit guest.
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 1af8aeb194..911955cfa
Require a 64-bit host binary to spawn a 64-bit guest.
For HVF this is trivially true because macOS 11 dropped
support for 32-bit applications entirely.
For NVMM, NetBSD only enables nvmm on x86_64:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/nvmm/Makefile?rev=1.1.6.2;content-type=text%2Fpl
For system mode, we can rarely support the amount of RAM that
the guest requires. TCG emulation is restricted to round-robin
mode, which solves many of the atomicity issues, but not those
associated with virtio. In any case, round-robin does nothing
to help the speed of emulation.
For user mode,
Configuration of 64-bit host on 32-bit guest will shortly
be denied. Use a 32-bit guest instead.
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/crossbuilds.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d
From: Helge Deller
The following changes since commit 6fccaa2fba391815308a746d68f7fa197bc93586:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2025-02-02 11:09:10 -0500)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git
tag
v1: 20250128004254.33442-1-richard.hender...@linaro.org
v2: 20250203031821.741477-1-richard.hender...@linaro.org
v3: 20250204215359.1238808-1-richard.hender...@linaro.org
For v4, tidy NVMM/WHPX per Thomas' review.
Drop two more stubs patches which were intended to be dropped with v3.
r~
Richar
We deprecated i686 system mode support for qemu 8.0. However, to
make real cleanups to TCG we need to deprecate all 32-bit hosts.
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
docs/about/deprecated.rst | 7 +++
From: Helge Deller
Allow users to disable the artist graphic card on the command line
with the option "-global artist.disable=true".
This change allows to use other graphic cards when using Linux, e.g.
by adding "-device ati-vga".
Signed-off-by: Helge Deller
---
hw/display/artist.c | 9 ++-
On Fri, Feb 7, 2025, 6:57 AM Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > This replaces use of the constants from the QapiSpecialFeatures
> > enum, with constants from the auto-generate QapiFeatures enum
> > in qapi-features.h
> >
> > The 'deprecated' and 'unstable' features still
Richard Henderson writes:
> On 2/7/25 07:45, Peter Maydell wrote:
>> This is where things go wrong -- icount_start_warp_timer()
>> notices that all CPU threads are currently idle, and
>> decides it needs to warp the timer forwards to the
>> next deadline, which is at the end of time -- INT64_MAX.
AMD EPYC 5th generation processors have introduced a feature that allows
the hypervisor to control the SEV_FEATURES that are set for, or by, a
guest [1]. ALLOWED_SEV_FEATURES can be used by the hypervisor to enforce
that SEV-ES and SEV-SNP guests cannot enable features that the
hypervisor does not
From: Kishon Vijay Abraham I
Add CPU feature detection for "Allowed SEV Features" to allow the
Hypervisor to enforce that SEV-ES and SEV-SNP guest VMs cannot
enable features (via SEV_FEATURES) that the Hypervisor does not
support or wish to be enabled.
Signed-off-by: Kishon Vijay Abraham I
Sign
AMD EPYC 5th generation processors have introduced a feature that allows
the hypervisor to control the SEV_FEATURES that are set for, or by, a
guest [1]. ALLOWED_SEV_FEATURES can be used by the hypervisor to enforce
that SEV-ES and SEV-SNP guests cannot enable features that the
hypervisor does not
The Allowed SEV Features feature allows the host kernel to control
which SEV features it does not want the guest to enable [1].
This has to be explicitly opted-in by the user because it has the
ability to break existing VMs if it were set automatically.
Currently, both the PmcVirtualization and S
On Wed, Jan 22, 2025 at 12:43 AM Joao Martins wrote:
>
> On 07/01/2025 06:55, Zhangfei Gao wrote:
> > Hi, Joao
> >
> > On Fri, Jun 23, 2023 at 5:51 AM Joao Martins
> > wrote:
> >>
> >> Hey,
> >>
> >> This series introduces support for vIOMMU with VFIO device migration,
> >> particurlarly related
On 2/7/25 03:02, Cornelia Huck wrote:
-t = cpu->isar.id_aa64zfr0;
+t = GET_IDREG(idregs, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_S
On 2/7/25 03:02, Cornelia Huck wrote:
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
new file mode 100644
index ..de09ebae91a5
--- /dev/null
+++ b/target/arm/cpu-sysregs.h
...
+static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
You can't place the data into
On 2/7/25 03:02, Cornelia Huck wrote:
+/* read a 32b sysreg value and store it in the idregs */
+static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs
sysreg)
+{
+int index = get_sysreg_idx(sysreg);
+uint64_t *reg;
+int ret;
+
+if (index < 0) {
+retur
This reverts commit dae0ec159f9 ("accel: build tcg modular").
The attempt was only enabled for x86, only modularized a small
portion of tcg, and in more than 3 years there have been no
follow-ups to improve the situation.
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Ma
On Fri, 7 Feb 2025 at 17:48, Peter Xu wrote:
>
> On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote:
> > (I wonder if we ought to suggest quiescing outstanding
> > DMA in the enter phase? But it's probably easier to fix
> > the iommus like this series does than try to get every
> > dma-
Peter Xu writes:
> On Fri, Feb 07, 2025 at 11:27:53AM -0300, Fabiano Rosas wrote:
>> The multifd recv side has been getting a TLS error of
>> GNUTLS_E_PREMATURE_TERMINATION at the end of migration when the send
>> side closes the sockets without ending the TLS session. This has been
>> masked by
Peter Xu writes:
> On Fri, Feb 07, 2025 at 11:27:58AM -0300, Fabiano Rosas wrote:
>> We're currently changing the way the source multifd migration handles
>> the shutdown of the multifd channels when TLS is in use to perform a
>> clean termination by calling gnutls_bye().
>>
>> Older src QEMUs w
On 2/7/25 03:02, Cornelia Huck wrote:
+/* read a 32b sysreg value and store it in the idregs */
+static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs
sysreg)
+{
+int index = get_sysreg_idx(sysreg);
+uint64_t *reg;
+int ret;
+
+if (index < 0) {
+retur
On 2/7/25 03:02, Cornelia Huck wrote:
And switch to using the generated definitions.
Generated against Linux 6.14-rc1.
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysreg-properties.c | 716 -
target/arm/cpu-sysregs.h | 116 +
target/arm/cpu-sysr
On Fri, Feb 07, 2025 at 11:27:51AM -0300, Fabiano Rosas wrote:
> QEMU's TLS session code provides no way to call gnutls_bye() to
> terminate a TLS session. Callers of qcrypto_tls_session_read() can
> choose to ignore a GNUTLS_E_PREMATURE_TERMINATION error by setting the
> gracefulTermination argume
On 2/6/25 15:21, Eric Auger wrote:
To ease the debug of reset sequence, let's add a trace point
in vfio_reset_handler()
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/vfio/common.c | 1 +
hw/vfio/trace-events | 1 +
2 files changed, 2 insertions(+)
d
On 2/7/25 07:45, Peter Maydell wrote:
This is where things go wrong -- icount_start_warp_timer()
notices that all CPU threads are currently idle, and
decides it needs to warp the timer forwards to the
next deadline, which is at the end of time -- INT64_MAX.
But once timer_mod_ns() returns, the g
On Fri, Feb 07, 2025 at 05:06:20PM +, Peter Maydell wrote:
> On Fri, 7 Feb 2025 at 16:54, Peter Xu wrote:
> >
> > On Thu, Feb 06, 2025 at 03:21:51PM +0100, Eric Auger wrote:
> > > This is a follow-up of Peter's attempt to fix the fact that
> > > vIOMMUs are likely to be reset before the device
On 2/7/25 17:54, Peter Xu wrote:
On Thu, Feb 06, 2025 at 03:21:51PM +0100, Eric Auger wrote:
This is a follow-up of Peter's attempt to fix the fact that
vIOMMUs are likely to be reset before the device they protect:
[PATCH 0/4] intel_iommu: Reset vIOMMU after all the rest of devices
https://lor
On Fri, Feb 7, 2025, 5:30 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Fri, Jan 31, 2025 at 8:18 AM Markus Armbruster
> wrote:
> >
> >> Cc: John Snow for Python typing expertise.
> >>
> >> Daniel P. Berrangé writes:
> >>
> >> > This replaces use of the constants from the QapiSpecia
On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote:
> (I wonder if we ought to suggest quiescing outstanding
> DMA in the enter phase? But it's probably easier to fix
> the iommus like this series does than try to get every
> dma-capable pci device to do something different.)
I wonder i
Peter Xu writes:
> On Fri, Feb 07, 2025 at 11:27:51AM -0300, Fabiano Rosas wrote:
>> QEMU's TLS session code provides no way to call gnutls_bye() to
>> terminate a TLS session. Callers of qcrypto_tls_session_read() can
>> choose to ignore a GNUTLS_E_PREMATURE_TERMINATION error by setting the
>> g
On Fri, Feb 07, 2025 at 11:27:53AM -0300, Fabiano Rosas wrote:
> The multifd recv side has been getting a TLS error of
> GNUTLS_E_PREMATURE_TERMINATION at the end of migration when the send
> side closes the sockets without ending the TLS session. This has been
> masked by the code not checking the
On Fri, Feb 07, 2025 at 11:27:54AM -0300, Fabiano Rosas wrote:
> We're currently only checking the QEMUFile error after
> qemu_loadvm_state(). Check the migration error as well to avoid
> missing errors that might be set by the multifd recv thread.
>
> This doesn't break compat between 9.2 and 10.
On 2/5/25 18:07, Peter Xu wrote:
On Wed, Feb 05, 2025 at 05:27:13PM +0100, William Roche wrote:
[...]
The HMP command "info ramblock" is implemented with the ram_block_format()
function which returns a message buffer built with a string for each
ramblock (protected by the RCU_READ_LOCK_GUARD). O
On Fri, Feb 07, 2025 at 11:27:58AM -0300, Fabiano Rosas wrote:
> We're currently changing the way the source multifd migration handles
> the shutdown of the multifd channels when TLS is in use to perform a
> clean termination by calling gnutls_bye().
>
> Older src QEMUs will always close the chann
On 2/7/25 07:30, Alex Bennée wrote:
This allows people to run the test locally:
make docker-test-rust@fedora-rust-nightly
Signed-off-by: Alex Bennée
---
v2
- update MAINTAINERS
---
MAINTAINERS | 1 +
tests/docker/Makefile.include | 3 +++
tests/docker/test-rust
On 2/6/25 20:13, Corvin Köhne wrote:
> From: Corvin Köhne
>
> We're currently missing some GPU IDs already supported by the i915
> kernel driver. Additionally, we've treated IvyBridge as gen 6 in the
> past. According to i915 it's gen 7 [1]. It shouldn't cause any issues
> yet because we treat
On Fri, Feb 07, 2025 at 02:55:57PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Feb 07, 2025 at 11:27:51AM -0300, Fabiano Rosas wrote:
> >> QEMU's TLS session code provides no way to call gnutls_bye() to
> >> terminate a TLS session. Callers of qcrypto_tls_session_read() can
> >>
On 7.02.2025 15:36, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: Peter Xu
The newly introduced device state buffer can be used for either storing
VFIO's read() raw data, but already also possible to store generic device
states. After noticing that device states may not easily pr
On 7.02.2025 15:27, Fabiano Rosas wrote:
v2:
Added the premature_ok logic;
Added compat property for QEMU <9.1;
Refactored the existing handshake code;
CI run:
https://gitlab.com/farosas/qemu/-/pipelines/1660800456
v1:
https://lore.kernel.org/r/20250206175824.22664-1-faro...@suse.de
Hi,
We'v
Replace function prefix name loongarch_xxx with virt_xxx in file
virt-acpi-build.c
Signed-off-by: Bibo Mao
---
hw/loongarch/virt-acpi-build.c | 6 +++---
hw/loongarch/virt.c| 2 +-
include/hw/loongarch/virt.h| 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/h
Similiar with virt-acpi-build.c, file virt-fdt-build.c is added here.
And move functions relative with fdt table building to the file.
It is only code movement and there is no function change.
Signed-off-by: Bibo Mao
---
hw/loongarch/meson.build | 4 +-
hw/loongarch/virt-fdt-build.c | 53
This is code cleanup with loongArch virt machine type. One separate file
is added for fdt table building, also rename file acpi-build with
virt-acpi-build.
It is only cod movement and function rename. There is no any function
change.
Bibo Mao (3):
hw/loongarch/virt: Rename filename acpi-build w
File acpi-build.c is relative with virt machine type, rename it with
virt-acpi-build.c
Signed-off-by: Bibo Mao
---
hw/loongarch/meson.build | 2 +-
hw/loongarch/{acpi-build.c => virt-acpi-build.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename hw/loongarch/{a
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO
(currentl
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin the entirety of
guest memory into the host iommu.
Pinning for the direct mapping case is handled via
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
With this series, QEMU can indicate to the guest that an IOMMU is not
strictly required for a zPCI device. This would subseque
Specifying this bit in the guest CLP response indicates that the guest
can optionally choose to skip translation and instead use
identity-mapped operations.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c| 5 -
include/hw/s390x/s390-pci-clp.h | 1 +
2 files changed, 5 inse
This series was spun off from:
"[PATCH 0/3] virtio-net: Convert feature properties to OnOffAuto"
(https://patchew.org/QEMU/20240714-auto-v3-0-e27401aab...@daynix.com/)
Some features are not always available with vhost. Legacy features are
not available with vp_vdpa in particular. virtio devices us
Do not consume a value if interpreting one failed so that we can
reinterpret the value with a different type.
Signed-off-by: Akihiko Odaki
---
qapi/qobject-input-visitor.c | 103 +--
1 file changed, 69 insertions(+), 34 deletions(-)
diff --git a/qapi/qobj
DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO()
as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference
is that DEFINE_PROP_ON_OFF_AUTO_BIT64() exposes OnOffAuto instead of
bool.
Signed-off-by: Akihiko Odaki
---
include/hw/qdev-properties.h | 18
Some features are not always available with vhost. Legacy features are
not available with vp_vdpa in particular. virtio devices used to disable
them when not available even if the corresponding properties were
explicitly set to "on".
QEMU already has OnOffAuto type, which includes the "auto" value
bool has representations of "on" and "off" different from
OnOffAuto/OnOffSplit:
- The command line syntax accepts on/yes/true/y and off/no/false/n for
bool but only on and off for OnOffAuto.
- JSON uses true/false for bool but "on" and "off" for
OnOffAuto/OnOffSplit.
This inconsistency causes
On Wed, Jan 29, 2025 at 11:59:04AM +0100, Paolo Bonzini wrote:
> Date: Wed, 29 Jan 2025 11:59:04 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH 04/10] rust: add bindings for gpio_{in|out}
> initialization
>
>
>
> On Sat, Jan 25, 2025 at 1:32 PM Zhao Liu wrote:
> > +fn init_gpio_in FnCa
Reviewed-by: Max Chou
On 2025/1/26 3:20 PM, Anton Blanchard wrote:
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 ++---
On Fri, 2025-02-07 at 08:47 +0100, Corvin Köhne wrote:
> On Thu, 2025-02-06 at 14:26 -0700, Alex Williamson wrote:
> > On Thu, 6 Feb 2025 13:13:39 +0100
> > Corvin Köhne wrote:
> >
> > > From: Corvin Köhne
> > >
> > > We've recently imported the PCI ID list of knwon Intel GPU devices from
> >
Am 6. Februar 2025 17:29:16 UTC schrieb Peter Maydell
:
>On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> docs/system/arm/imx8mp-evk.rst | 1 +
>> include/hw/arm/fsl-imx8mp.h| 11 +++
>> include/hw/timer/imx_gpt.h | 1 +
>> hw
Hi Anton,
You might need to extend this patch or provide a new patch to handle
the different EEWs source operands checking for the vrgatherei16.vv
instruction (when SEW is not 16).
Thanks,
Max
On 2025/1/26 3:20 PM, Anton Blanchard wrote:
Signed-off-by: Anton Blanchard
---
target/riscv/insn
Hi Anton,
I think that the commit message could be improved for better clarity.
The vext_check_ss function affects more RVV instructions than the
vadd.vx instruction alone.
(PS:perhaps using the category (OPIVX/OPFVF/etc.) to describe the
affected RVV instructions would be more helpful.)
Addit
Hi Anton,
The vext_check_slide function affects the
vslide[up|down].v[x|i]/vfslide1[up|down].vf/vslide1[up|down].vx
instructions than the vslide1down.vx instruction alone.
Therefore, it would be more appropriate to update the commit message to
provide a clearer information.
(PS:perhaps, using
On Thu, Feb 06, 2025 at 06:32:58PM +0100, Philippe Mathieu-Daudé wrote:
> We only support 32-bit TriCore architecture.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/tricore/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheer
On Fri, 7 Feb 2025 at 04:14, Peter Xu wrote:
> Would you mind reorder the two test patches, to avoid removing the lines
> added by previous patch?
* Both ways they are the same in the end, no? Anyway, will do.
Thank you.
---
- Prasad
Hi Anton,
This patch violates some coding style rules of QEMU.
You can verify the coding style by running the checkpatch.pl script in
the QEMU repository.
(ref:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#use-the-qemu-coding-style)
The patch 12 also has the same issue.
Than
Reviewed-by: Max Chou
On 2025/1/26 3:20 PM, Anton Blanchard wrote:
Signed-off-by: Anton Blanchard
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_
On 11/21/2024 6:06 PM, Mi, Dapeng wrote:
> On 11/8/2024 7:44 AM, dongli.zh...@oracle.com wrote:
>> Hi Zhao,
>>
>>
>> On 11/6/24 11:52 PM, Zhao Liu wrote:
>>> (+Dapang & Zide)
>>>
>>> Hi Dongli,
>>>
>>> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
Date: Mon, 4 Nov 2024 01:40
Il ven 7 feb 2025, 09:24 Zhao Liu ha scritto:
> > Please add "let _: () = F::ASSERT_IS_SOME;", which is added by the
> > qdev_init_clock_in() patch.
> >
>
> Okay.
>
> I would add `assert!(F::is_some());` at the beginning of init_gpio_in().
>
Use the "let" so that it's caught at compile time.
Th
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
target/arm/cpu64.c| 28
target/arm/helper
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 4 ++--
target/arm/helper.c | 4 ++--
target/arm/i
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 14
target/arm/help
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h | 3 +++
target/arm/cpu64.c | 25 +
target/arm/kvm.c | 30 ++
3 files changed, 58 insertions(+)
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index de09
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 72 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/helper.c | 8 ++---
target/arm/kvm.c | 12 +++
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu.c | 14 --
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 8 +++---
target/arm/helper.c |
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16
target/arm/cpu.c | 13 +
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 4 ++--
target/arm/helpe
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 3 +--
target/arm/tcg/cpu64.c| 4 ++--
6 f
From: Eric Auger
The known ID regs are described in a new initialization function
dubbed initialize_cpu_sysreg_properties(). That code will be
automatically generated from linux arch/arm64/tools/sysreg. For the
time being let's just describe a single id reg, CTR_EL0. In this
description we only c
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
target/arm/helper.c | 12 ++---
target/arm/kvm.c
From: Eric Auger
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory do generate 2 qemu files:
- target/arm/cpu-sysreg-p
On Thu, Feb 06, 2025 at 03:21:51PM +0100, Eric Auger wrote:
> This is a follow-up of Peter's attempt to fix the fact that
> vIOMMUs are likely to be reset before the device they protect:
>
> [PATCH 0/4] intel_iommu: Reset vIOMMU after all the rest of devices
> https://lore.kernel.org/all/202401170
1 - 100 of 261 matches
Mail list logo
