SNVS contains an RTC which allows Linux to deal correctly with time. This is
particularly useful when handling persistent storage which will be done in the
next patch.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
>
> All previous raspi machines can be created using the
> generic machine. Deprecate the old names to maintain
> a single one. Update the tests.
>
> Signed-off-by: Philippe Mathieu-Daudé
> diff --git a/docs/about/deprecated.rst b/docs/a
On a real device, the boot ROM contains the very first instructions the CPU
executes. Also, U-Boot calls into the ROM to determine the boot device. While
we're not actually implementing this here, let's create the infrastructure and
add a dummy ROM with all zeros. This allows for implementing a ROM
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx8mp.h | 1 +
hw/arm/fsl-imx8mp.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index 4dbe30f524..03f057c7db 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++
While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference
manual.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
---
include/hw/usb/hcd-dwc3.h | 2 +-
hw/usb/hcd-dwc3.c | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/hw/
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
serial. All other devices of the A53 memory map are represented as
TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
for running Linux without it crashing due to invalid memory accesses.
Signe
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 8
hw/arm/fsl-imx8mp.c| 26 ++
3 files changed, 35 insertions(+)
diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst
On the real device, the PCIe root bus is only connected to a PCIe bridge and
does not allow for direct attachment of devices. Doing so in QEMU results in no
PCI devices being detected by Linux. Instead, PCI devices should plug into the
secondary PCIe bus spawned by the internal PCIe bridge.
Unfort
Hi Jan,
On 4/2/25 10:11, Jan Beulich wrote:
On 04.02.2025 09:19, Juergen Gross wrote:
On 03.02.25 23:43, Stefano Stabellini wrote:
+Xen maintainers
On Mon, 3 Feb 2025, Richard Henderson wrote:
On 2/3/25 04:54, Paolo Bonzini wrote:
On 2/3/25 04:18, Richard Henderson wrote:
v1: 202501280042
On 4/2/25 10:57, Daniel P. Berrangé wrote:
On Tue, Feb 04, 2025 at 10:51:04AM +0100, Philippe Mathieu-Daudé wrote:
On 4/2/25 10:22, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
All previous raspi machines can be created using the
generic machine. Deprecate
On Tue, Feb 04, 2025 at 11:48:10AM +0100, Philippe Mathieu-Daudé wrote:
> On 4/2/25 10:57, Daniel P. Berrangé wrote:
> > On Tue, Feb 04, 2025 at 10:51:04AM +0100, Philippe Mathieu-Daudé wrote:
> > > On 4/2/25 10:22, Peter Maydell wrote:
> > > > On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé
On Mon, 3 Feb 2025 11:29:49 +0530
Arpit Kumar wrote:
Add some description of what is being added here.
Key issue in here is that clearing the CEL doesn't make
sense. It is a description of what the device supports, there
is no state to clear in it. To add this command you need
to pick a differ
On Thu, 16 Jan 2025 at 14:05, David Woodhouse wrote:
>
> From: David Woodhouse
>
> The vmclock device addresses the problem of live migration with
> precision clocks. The tolerances of a hardware counter (e.g. TSC) are
> typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that
> c
Peter Xu writes:
> On Mon, Feb 03, 2025 at 10:41:32PM +0100, Maciej S. Szmigiero wrote:
>> On 3.02.2025 21:20, Peter Xu wrote:
>> > On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
>> > > On 3.02.2025 19:20, Peter Xu wrote:
>> > > > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Ma
On Mon, Feb 3, 2025 at 2:58 AM Alistair Francis wrote:
>
> On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
> >
> > CTR entries are accessed using ctrsource, ctrtarget and ctrdata
> > registers using smcsrind/sscsrind extension. This commits extends
> > the csrind extension to support CTR reg
On Tue, 4 Feb 2025 at 13:40, Philippe Mathieu-Daudé wrote:
>
> On 4/2/25 12:13, Peter Maydell wrote:
> > On Tue, 4 Feb 2025 at 09:57, Daniel P. Berrangé wrote:
> >> IMHO we can have distinct machines for each model, but
> >> *NOT* have further machines for each RAM size within a
> >> model.
> >
>
On Mon, 13 Jan 2025 at 17:38, Philippe Mathieu-Daudé wrote:
>
> From: Akihiko Odaki
>
> Commit 03fcbd9dc508 ("qdev: Check for the availability of a hotplug
> controller before adding a device") says:
>
> > The qdev_unplug() function contains a g_assert(hotplug_ctrl)
> > statement, so QEMU crash
On Thu, 30 Jan 2025 at 11:26, Philippe Mathieu-Daudé wrote:
>
> (series fully reviewed)
>
> Hi,
>
> This series contains the non-controversial and already
> reviewed patches (rebased) from this previous series:
> "Remove one use of qemu_get_cpu() in A7/A15 MPCore priv"
> https://lore.kernel.org/qe
On Thu, 30 Jan 2025 at 18:26, Philippe Mathieu-Daudé wrote:
>
> We already have a definition to distinct GIC internal
> IRQs versus external ones, use it. No logical changes.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/xilinx_zynq.c | 34 --
> 1 file
Hi Nathan,
On 11/22/24 7:53 PM, Nathan Chen wrote:
> > >> Also as a heads up, I've added support for auto-inserting PCIe
> switch
> > >> between the PXB and GPUs in libvirt to attach multiple devices to a
> > SMMU
> > >> node per libvirt's documentation - "If you intend to plug multiple
> > >
On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
wrote:
> On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> wrote:
>> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
>> wrote:
>> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
>> > -mask = FIELD_EX32(cr0, TYPE2_COMPARE_0
On 1/29/25 15:43, Steve Sistare wrote:
Refactor vector use into a helper vfio_vector_init.
Add vfio_notifier_init and vfio_notifier_cleanup for named notifiers,
and pass additional arguments to vfio_remove_kvm_msi_virq.
All for use by CPR in a subsequent patch. No functional change.
Signed-off
On 3.02.2025 23:59, Peter Xu wrote:
On Mon, Feb 03, 2025 at 11:18:11PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 22:27, Peter Xu wrote:
On Thu, Jan 30, 2025 at 11:08:34AM +0100, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via mul
On 4.02.2025 00:02, Peter Xu wrote:
On Mon, Feb 03, 2025 at 10:41:43PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 21:36, Peter Xu wrote:
On Mon, Feb 03, 2025 at 09:15:52PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 20:58, Peter Xu wrote:
On Mon, Feb 03, 2025 at 02:57:36PM +0100, Macie
On 4/2/25 14:52, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 13:40, Philippe Mathieu-Daudé wrote:
On 4/2/25 12:13, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 09:57, Daniel P. Berrangé wrote:
IMHO we can have distinct machines for each model, but
*NOT* have further machines for each RAM size
On Mon, Feb 03, 2025 at 03:20:50PM -0500, Peter Xu wrote:
> On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
> > On 3.02.2025 19:20, Peter Xu wrote:
> > > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
> > > > From: "Maciej S. Szmigiero"
> > > >
> > > > M
On Tue, 4 Feb 2025 at 15:08, Philippe Mathieu-Daudé wrote:
>
> Hi Paolo,
>
> On 3/2/25 12:41, Paolo Bonzini wrote:
> > Currently, the instance_post_init calls are performed from the leaf
> > class and all the way up to Object. This is incorrect because the
> > leaf class cannot observe property v
On 2/4/25 16:08, Philippe Mathieu-Daudé wrote:
Hi Paolo,
On 3/2/25 12:41, Paolo Bonzini wrote:
Currently, the instance_post_init calls are performed from the leaf
class and all the way up to Object. This is incorrect because the
leaf class cannot observe property values applied by the supercla
On 4.02.2025 16:00, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
On 3.02.2025 23:56, Peter Xu wrote:
On Mon, Feb 03, 2025 at 10:41:32PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 21:20, Peter Xu wrote:
On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2
On Tue, Feb 04, 2025 at 03:39:00PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 23:56, Peter Xu wrote:
> > On Mon, Feb 03, 2025 at 10:41:32PM +0100, Maciej S. Szmigiero wrote:
> > > On 3.02.2025 21:20, Peter Xu wrote:
> > > > On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
>
> Raspberry Pi 'B' models have an ethernet chipset (the LAN9512).
> Since we don't yet model it, add a /* TODO */ comment.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/raspi.c | 14 ++
> 1 file changed, 14 inser
On 2/4/2025 10:02 AM, Philippe Mathieu-Daudé wrote:
On 4/2/25 14:29, Paolo Bonzini wrote:
On 2/4/25 09:28, Cédric Le Goater wrote:
The CPR feature was added in QEMU 9.0 and it lacks a maintainer.
Propose the main contributor to become one.
Why can't changes go through the migration tree? The
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
>
> Add the 'max_ramsize' field to the soc_property[] array,
> corresponding to the maximum DRAM size a SoC can map.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/raspi.c | 21 +
> 1 file changed, 17 insert
On Tue, Feb 04, 2025 at 03:57:37PM +0100, Maciej S. Szmigiero wrote:
> The vfio_migration_cleanup() used to just close a migration FD, while
> RAM might end up calling qemu_ram_msync(), which sounds like something
> that should be called under BQL.
>
> But I am not sure whether that lack of BQL ar
On Mon, Feb 03, 2025 at 01:20:01PM -0500, Peter Xu wrote:
> On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
> > From: "Maciej S. Szmigiero"
> >
> > Multifd send channels are terminated by calling
> > qio_channel_shutdown(QIO_CHANNEL_SHUTDOWN_BOTH) in
> > multifd_send_terminat
Hi Paolo,
On 3/2/25 12:41, Paolo Bonzini wrote:
Currently, the instance_post_init calls are performed from the leaf
class and all the way up to Object. This is incorrect because the
leaf class cannot observe property values applied by the superclasses;
for example, a compat property will be set
q
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
> needs to fit both. This commit changes the name of the GCR module.
> Future commits will add the support for NPCM8XX GCRs.
>
> Signed-off-by: Hao Wu
> ---
> hw/misc/meson.buil
Am 31.01.2025 um 14:41 hat Fabiano Rosas geschrieben:
> Kevin Wolf writes:
>
> > Add an option in BlockExportOptions to allow creating an export on an
> > inactive node without activating the node. This mode needs to be
> > explicitly supported by the export type (so that it doesn't perform any
>
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
> this commit moves the NPCM7XX GCR to NPCM GCR for these
> properties.
>
> Signed-off-by: Hao Wu
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> Signed-off-by: Hao Wu
> ---
> hw/misc/npcm_gcr.c | 131 -
> include/hw/misc/npcm_gcr.h | 6 +-
> 2 files changed, 134 insertions(+), 3 deletions(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
+ John (for vfio-user)
On 1/29/25 15:43, Steve Sistare wrote:
Return the memory region that the translated address is found in, for
use in a subsequent patch. No functional change.
Keeping a reference on this memory region could be risky. What for ?
Signed-off-by: Steve Sistare
---
hw/vf
On 1/29/25 15:43, Steve Sistare wrote:
Refactor and define iommufd_cdev_make_hwpt, to be called by CPR in a
a later patch. No functional change.
Signed-off-by: Steve Sistare
---
hw/vfio/iommufd.c | 69 +--
1 file changed, 41 insertions(+),
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
> PHY. This implementation contains all the default registers and
> the soft reset feature that are required to load the Linux kernel
> driver. Further features have not been implemen
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
>
> Expand the current type2model array to include the processor id.
>
> Since the BCM2838 is indistinctly used as BCM2711 (within the
> Linux community), add it as alias in RaspiProcessorId.
Can you explain this in more detail? Presumabl
On Tue, Feb 04, 2025 at 11:02:28AM -0500, Peter Xu wrote:
> On Tue, Feb 04, 2025 at 03:08:02PM +, Daniel P. Berrangé wrote:
> > On Mon, Feb 03, 2025 at 01:20:01PM -0500, Peter Xu wrote:
> > > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
> > > > From: "Maciej S. Szmigiero
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
> Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This should go at the end of the series, once you've added
the new machine types it documents.
> Signed-off-by: Ha
On Tue, Feb 04, 2025 at 05:02:23PM +0100, Maciej S. Szmigiero wrote:
> On 4.02.2025 16:15, Daniel P. Berrangé wrote:
> > On Thu, Jan 30, 2025 at 11:08:28AM +0100, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > Currently, hitting EOF on receive without sender terminating
On 2/4/2025 9:39 AM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
Refactor vector use into a helper vfio_vector_init.
Add vfio_notifier_init and vfio_notifier_cleanup for named notifiers,
and pass additional arguments to vfio_remove_kvm_msi_virq.
All for use by CPR in a subseq
On 2/4/2025 9:56 AM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
Do not reset a vfio-pci device during CPR, and do not complain if the
kernel's PCI config space changes for non-emulated bits between the
vmstate save and load, which can happen due to ongoing interrupt activity.
On Thu, 26 Dec 2024 at 08:29, Hao Wu wrote:
>
> Signed-off-by: Hao Wu
> ---
> hw/arm/meson.build | 2 +-
> hw/arm/npcm8xx_boards.c | 256 +++
> include/hw/arm/npcm8xx.h | 20 +++
> 3 files changed, 277 insertions(+), 1 deletion(-)
> create mode 1006
On 2/4/2025 9:14 AM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
Do not reset a vfio-pci device during CPR.
Signed-off-by: Steve Sistare
---
hw/pci/pci.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 2afa423..16b4f71
On 2/4/2025 9:10 AM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
If there are multiple containers and unmap-all fails for some container, we
need to remap vaddr for the other containers for which unmap-all succeeded.
Recover by walking all address ranges of all containers to r
On Tue, Feb 04, 2025 at 01:40:34PM +, Peter Maydell wrote:
> On Wed, 29 Jan 2025 at 16:11, Fabiano Rosas wrote:
> >
> > From: Steve Sistare
> >
> > Add the cpr-transfer migration mode, which allows the user to transfer
> > a guest to a new QEMU instance on the same host with minimal guest pau
Am 30.01.2025 um 20:50 hat Eric Blake geschrieben:
> On Thu, Jan 30, 2025 at 06:12:34PM +0100, Kevin Wolf wrote:
> > Block devices have an individual active state, a single global flag
> > can't cover this correctly. This becomes more important as we allow
> > users to manually manage which nodes a
On Tue, Feb 04, 2025 at 03:08:02PM +, Daniel P. Berrangé wrote:
> On Mon, Feb 03, 2025 at 01:20:01PM -0500, Peter Xu wrote:
> > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > Multifd send channels are terminated by calling
>
On Thu, 26 Dec 2024 at 08:29, Hao Wu wrote:
>
> Signed-off-by: Hao Wu
> ---
> configs/devices/aarch64-softmmu/default.mak | 1 +
> hw/arm/Kconfig | 11 +
> hw/arm/meson.build | 1 +
> hw/arm/npcm8xx.c| 810 +++
On Tue, Feb 04, 2025 at 04:12:15PM +, Daniel P. Berrangé wrote:
> On Tue, Feb 04, 2025 at 11:02:28AM -0500, Peter Xu wrote:
> > On Tue, Feb 04, 2025 at 03:08:02PM +, Daniel P. Berrangé wrote:
> > > On Mon, Feb 03, 2025 at 01:20:01PM -0500, Peter Xu wrote:
> > > > On Thu, Jan 30, 2025 at 11:
Am 03.02.2025 um 20:49 hat Eric Blake geschrieben:
> On Fri, Jan 31, 2025 at 10:50:51AM +0100, Kevin Wolf wrote:
> > This tests different types of operations on inactive block nodes
> > (including graph changes, block jobs and NBD exports) to make sure that
> > users manually activating and inactiv
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> The bootrom is a minimal bootrom used to load an NPCM8XX image.
> The source code is located in the same repo as the NPCM7XX one:
> github.com/google/vbootrom/tree/master/npcm8xx.
>
> Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 26 Dec 2024 at 08:28, Hao Wu wrote:
>
> This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
> it supports loading the UBoot from the SPI device and not more.
>
> We updated the npcm7xx bootrom to be compiled from this version.
>
> Signed-off-by: Hao Wu
> ---
Reviewed-by: Pet
On 2/4/2025 11:26 AM, Peter Xu wrote:
On Tue, Feb 04, 2025 at 01:40:34PM +, Peter Maydell wrote:
On Wed, 29 Jan 2025 at 16:11, Fabiano Rosas wrote:
From: Steve Sistare
Add the cpr-transfer migration mode, which allows the user to transfer
a guest to a new QEMU instance on the same host
On 03.02.25 23:43, Stefano Stabellini wrote:
+Xen maintainers
On Mon, 3 Feb 2025, Richard Henderson wrote:
On 2/3/25 04:54, Paolo Bonzini wrote:
On 2/3/25 04:18, Richard Henderson wrote:
v1: 20250128004254.33442-1-richard.hender...@linaro.org
For v2, immediately disable 64-on-32 TCG.
I *su
Hi Cedric,
> From: Cédric Le Goater
> Sent: Tuesday, February 4, 2025 3:35 PM
> To: Jamin Lin ; Andrew Jeffery
> ; Peter Maydell ;
> Steven Lee ; Troy Lee ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v1 01/18]
On 1/23/25 7:31 PM, Peter Xu wrote:
On Thu, Jan 23, 2025 at 04:19:40PM +0300, Daniil Tatianin wrote:
Currently, passing mem-lock=on to QEMU causes memory usage to grow by
huge amounts:
no memlock:
$ ./qemu-system-x86_64 -overcommit mem-lock=off
$ ps -p $(pidof ./qemu-system-x86_64)
Hi Cedric,
> From: Cédric Le Goater
> Sent: Friday, January 31, 2025 3:34 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v1 00/18]
The ref405ep machine is the only PPC 405 machine. Drop all support by
removing the SoC and associated devices as-well as the machine.
Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-3-...@redhat.com
Signed-off-by: Cédric Le Goater
---
MAINTAINERS |6 -
doc
Since we are about to remove all support for PPC 405, start by
removing the tests referring to the ref405ep machine.
Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-2-...@redhat.com
Signed-off-by: Cédric Le Goater
---
tests/qtest/m48t59-test.c| 5 -
tests/functional/
Hello,
The PPC 405 CPU and ref405ep machine was deprecated in QEMU 9.1
because there are no known users, firmware images are not available,
OpenWRT dropped support in 2019, U-Boot in 2017, and Linux in 2024.
Continue the phase-out process and remove tests, plus boards. The 405
CPU implementation
The ref405ep machine is scheduled for removal in QEMU 10.0. Keep the
405 CPU implementation for a while because it is theoretically
possible to model the power management (OCC) co-processor found on the
IBM POWER [8-11] processors.
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst |
When reading or writing the timer registers, sometimes we need to
apply one of the timer offsets. Specifically, this happens for
direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It
also applies for direct reads a
On 2/3/25 11:50 AM, Anthony Krowiak wrote:
On 1/7/25 1:43 PM, Rorie Reyes wrote:
Creates an object indicating that an AP configuration change event
has been received and stores it in a queue. These objects will later
be used to store event information for an AP configuration change
when the
On Mon, 3 Feb 2025 11:29:50 +0530
Arpit Kumar wrote:
> Signed-off-by: Arpit Kumar
> Reviewed-by: Alok Rathore
> Reviewed-by: Krishna Kanth Reddy
Likewise, the CEL isn't a dynamic thing. Asking to populate
it makes little sense so the log capability should always
say this is not supported.
On Tue, 4 Feb 2025 14:16:19 +0900
Itaru Kitayama wrote:
> Jonathan,
>
> > On Feb 4, 2025, at 2:30, Jonathan Cameron
> > wrote:
> >
> > Add a single complex case for aarch64 virt machine.
> > Given existing much more comprehensive tests for x86 cover the
> > common functionality, a single test
Hi Andrew,
> -Original Message-
> From: Andrew Jeffery
> Sent: Thursday, January 30, 2025 12:20 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Steven Lee
> ; Troy Lee ; Joel Stanley
> ; open list:ASPEED BMCs ; open
> list:All patches CC here
> Cc: Troy Lee ; Yunlin Tang
>
> S
When a machine is first booted, all virtio balloon stats are initialized
to their default value -1 (18446744073709551615 when represented as
unsigned).
They remain that way while the firmware is loading, and early phase of
guest OS boot, until the virtio-balloon driver is activated. Thereafter
the
Hi Andrew,
> From: Andrew Jeffery
> Sent: Thursday, January 30, 2025 11:55 AM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Steven Lee
> ; Troy Lee ; Joel Stanley
> ; open list:ASPEED BMCs ; open
> list:All patches CC here
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v1 06/18]
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one
and a Designware one. There is no device model for the latter, so only add the
ENET one.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 8
hw/arm/
On 4/2/25 10:22, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
All previous raspi machines can be created using the
generic machine. Deprecate the old names to maintain
a single one. Update the tests.
Signed-off-by: Philippe Mathieu-Daudé
diff --git a/doc
On Tue, Feb 04, 2025 at 10:51:04AM +0100, Philippe Mathieu-Daudé wrote:
> On 4/2/25 10:22, Peter Maydell wrote:
> > On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé
> > wrote:
> > >
> > > All previous raspi machines can be created using the
> > > generic machine. Deprecate the old names to ma
On Tue, 4 Feb 2025, Philippe Mathieu-Daudé wrote:
On 4/2/25 10:22, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé
wrote:
All previous raspi machines can be created using the
generic machine. Deprecate the old names to maintain
a single one. Update the tests.
Signed-
On 2/4/25 09:28, Cédric Le Goater wrote:
The CPR feature was added in QEMU 9.0 and it lacks a maintainer.
Propose the main contributor to become one.
Why can't changes go through the migration tree? The only addition
seems to be hw/vfio/cpr*.
Paolo
Cc: Steve Sistare
Signed-off-by: Cédric
On Tue, 28 Jan 2025 12:52:39 -0800
Richard Henderson wrote:
> On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
> > We are trying to understand what means "a qdev is realized".
> > One explanation was "the device is guest visible"; however
> > many devices are realized before being mapped, thus are
On 4/2/25 12:13, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 09:57, Daniel P. Berrangé wrote:
On Tue, Feb 04, 2025 at 10:51:04AM +0100, Philippe Mathieu-Daudé wrote:
On 4/2/25 10:22, Peter Maydell wrote:
On Tue, 4 Feb 2025 at 00:23, Philippe Mathieu-Daudé wrote:
All previous raspi machines
Hi Cedric, CPR is a mode of live migration, integrated so closely that
it makes more sense for the migration maintainers to maintain it, and
consult me if/when necessary. "migration" appears in 4 of the 5 paths
you list below.
- Steve
On 2/4/2025 3:28 AM, Cédric Le Goater wrote:
The CPR featur
On Wed, 29 Jan 2025 at 16:11, Fabiano Rosas wrote:
>
> From: Steve Sistare
>
> Add the cpr-transfer migration mode, which allows the user to transfer
> a guest to a new QEMU instance on the same host with minimal guest pause
> time, by preserving guest RAM in place, albeit with new virtual addres
On 2/4/25 14:31, Steven Sistare wrote:
Hi Cedric, CPR is a mode of live migration, integrated so closely that
it makes more sense for the migration maintainers to maintain it, and
consult me if/when necessary. "migration" appears in 4 of the 5 paths
you list below.
CPR is growing with the rece
On Mon, Feb 03, 2025 at 02:43:05PM -0800, Stefano Stabellini wrote:
> +Xen maintainers
>
>
> On Mon, 3 Feb 2025, Richard Henderson wrote:
> > On 2/3/25 04:54, Paolo Bonzini wrote:
> > > On 2/3/25 04:18, Richard Henderson wrote:
> > > > v1: 20250128004254.33442-1-richard.hender...@linaro.org
> > >
Am 3. Februar 2025 05:42:55 UTC schrieb Dmitriy Sharikhin
:
>At Sun, 02/02/2025 at 18:09 +0100, Philippe Mathieu-Daudé writes:
>> No clue about compatibility. If you unfortunately need to add it,
>> then please address my comments in the next version.
>TCA6416 is _way_ more complex device than
On 04.02.2025 09:19, Juergen Gross wrote:
> On 03.02.25 23:43, Stefano Stabellini wrote:
>> +Xen maintainers
>>
>>
>> On Mon, 3 Feb 2025, Richard Henderson wrote:
>>> On 2/3/25 04:54, Paolo Bonzini wrote:
On 2/3/25 04:18, Richard Henderson wrote:
> v1: 20250128004254.33442-1-richard.hender
Hi,
On 1/31/25 12:27 PM, Eugenio Perez Martin wrote:
On Fri, Jan 31, 2025 at 6:04 AM Sahil Siddiq wrote:
On 1/24/25 1:04 PM, Eugenio Perez Martin wrote:
On Fri, Jan 24, 2025 at 6:47 AM Sahil Siddiq wrote:
On 1/21/25 10:07 PM, Eugenio Perez Martin wrote:
On Sun, Jan 19, 2025 at 7:37 AM Sahi
When we added Secure EL2 support, we missed that this needs an update
to the access code for the EL3 physical timer registers. These are
supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 3 +++
1 file
From: Alex Bennée
Signed-off-by: Alex Bennée
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 99e0a68b6c5..c00a6e410cd 100644
--- a/hw/arm/virt.c
+++ b
When we are calculating timer deadlines, the correct definition of
whether or not to apply an offset to the physical count is described
in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different
from when the offset should be applied for a direct read of the
counter sysreg.
We got this r
From: Alex Bennée
When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:
- define the timers and their access functions
From: Alex Bennée
As we are about to add more physical and virtual timers lets make it
clear what each timer does.
Signed-off-by: Alex Bennée
[PMM: Add timer register name prefix to each comment]
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/gtimer.h | 10 +-
From: Alex Bennée
Signed-off-by: Alex Bennée
Reviewed-by: Peter Maydell
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
---
hw/arm/sbsa-ref.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 6183111f2de..d69e7aaa95e 100644
--- a/hw/arm/
The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 2 --
1 file changed,
This patchset is a respin of Alex's patches, with some extra fixes
for bugs I discovered along the way in our existing code (and
a bit of refactoring to make the fixes straightforward). It is:
Based-on: 20250130182309.717346-1-peter.mayd...@linaro.org
("target/arm: Clean up some corner cases of sy
Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer. This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at EL2 and HCR_EL2.E2H is
Ping for code review, please?
thanks
-- PMM
On Mon, 27 Jan 2025 at 12:31, Peter Maydell wrote:
>
> The '-old-param' command line option is specific to Arm targets; it
> is very briefly documented as "old param mode". What this option
> actually does is change the behaviour when directly booting
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