Re: [PATCH 1/2] target/s390x: Fix MVC not always invalidating translation blocks

On Tue, 2025-01-28 at 10:56 +0100, David Hildenbrand wrote: > On 28.01.25 01:12, Ilya Leoshkevich wrote: > > Node.js crashes in qemu-system-s390x with random SIGSEGVs / > > SIGILLs. > > > > The v8 JIT used by Node.js can garbage collect and overwrite unused > > code. Overwriting is performed by >

[PATCH 05/11] hw/sd/omap_mmc: Use similar API for "wire up omap_clk" to other OMAP devices

The approach we've settled on for handling the omap_clk wiring for OMAP devices converted to QDev is to have a function omap_foo_set_clk() whose implementation just sets the field directly in the device's state struct. (See the "TODO" comment near the top of omap.h.) Make omap_mmc do the same. Sig

Re: [PATCH 01/22] target/arm: Rename FPST_FPCR_A32 to FPST_A32

On Mon, 27 Jan 2025 at 23:26, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate.h | 6 ++-- > target/arm/tcg/translate-vfp.c | 54 +- > 2 files changed, 30 insertions(+), 30 deletions(-) > > diff --git a/target/arm

Re: [PATCH v2 10/15] target/ppc: Restrict ppc_tcg_hv_emu() to TCG

On 1/27/25 15:56, Philippe Mathieu-Daudé wrote: Make is_prefix_insn_excp() prototype but have it guarded by a tcg_enabled() check. Inline part of it in powerpc_excp_books(). Extract POWERPC_EXCP_HV_EMU handling code to ppc_tcg_hv_emu(), also exposing its prototype in "internal.h". Signed-off

Re: [PATCH 0/9] hw/sysbus/platform-bus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE

On Tue, 28 Jan 2025 at 10:42, Gerd Hoffmann wrote: > > On Sat, Jan 25, 2025 at 07:13:34PM +0100, Philippe Mathieu-Daudé wrote: > > Some SysBus devices can optionally be dynamically plugged onto > > the sysbus-platform-bus (then virtual guests are aware of > > mmio mapping and IRQs via device tree

Re: [PATCH 02/11] acpi/ghes: add a firmware file with HEST address

Em Thu, 23 Jan 2025 18:01:35 +0100 Igor Mammedov escreveu: > On Thu, 23 Jan 2025 10:02:17 + > Jonathan Cameron wrote: > > > On Wed, 22 Jan 2025 16:46:19 +0100 > > Mauro Carvalho Chehab wrote: > > > > > Store HEST table address at GPA, placing its content at > > > hest_addr_le variable.

Rust in QEMU update, January 2025

It's been roughly two months since my previous posting of a roadmap for Rust in QEMU, so it's time for an update. While the project is still at an experimental phase, the amount of functionality available from safe Rust is enough that it could be considered for new devices. As before, this mostl

Re: [PATCH v2 09/15] target/ppc: Restrict exception helpers to TCG

On 28/1/25 10:59, Harsh Prateek Bora wrote: On 1/27/25 15:56, Philippe Mathieu-Daudé wrote: Move exception helpers to tcg-excp_helper.c so they are only built when TCG is selected. Signed-off-by: Philippe Mathieu-Daudé ---   target/ppc/excp_helper.c | 34

[Stable-9.1.3 17/58] 9pfs: fix 'Tgetattr' after unlink

With a valid file ID (FID) of an open file, it should be possible to send a 'Tgettattr' 9p request and successfully receive a 'Rgetattr' response, even if the file has been removed in the meantime. Currently this would fail with ENOENT. I.e. this fixes the following misbehaviour with a 9p Linux cl

[Stable-8.2.9 23/45] 9pfs: fix regression regarding CVE-2023-2861

The released fix for this CVE: f6b0de53fb8 ("9pfs: prevent opening special files (CVE-2023-2861)") caused a regression with security_model=passthrough. When handling a 'Tmknod' request there was a side effect that 'Tmknod' request could fail as 9p server was trying to adjust permissions: #6

[Stable-8.2.9 42/45] tests: acpi: whitelist expected blobs

Signed-off-by: Igor Mammedov Message-Id: <20250115125342.3883374-2-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin (cherry picked from commit 1ad32644fe4c9fb25086be15a66dde1d55d3410f) Signed-off-by: Michael Tokarev (Mjt: drop x86/ subdir and tables not rel

[Stable-9.1.3 29/58] roms: re-add edk2-basetools target

Needed to build ipxe nic roms. Reported-by: Liu Jaloo Fixes: 22e11539e167 ("edk2: replace build scripts") Signed-off-by: Gerd Hoffmann Message-ID: <20241212084408.1390728-1-kra...@redhat.com> (cherry picked from commit 0f5715e4b5706b31b3550d8e6b88871e029c7823) Signed-off-by: Michael Tokarev di

[Stable-8.2.9 12/45] 9pfs: remove obsolete comment in v9fs_getattr()

The comment claims that we'd only support basic Tgetattr fields. This is no longer true, so remove this comment. Fixes: e06a765efbe3 ("hw/9pfs: Add st_gen support in getattr reply") Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: (cherry picked from commit 3bc4db44430f5

[Stable-9.1.3 39/58] docs: Correct release of TCG trace-events removal

TCG trace-events were deprecated before the v6.2 release, and removed for v7.0. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Michael Tokarev Signed-off-by: Michael Tokarev (cherry picked from commit b4859e8f33a7d9c793a60395f792c10190cb4f78) Signed-off-by: Michael

[Stable-9.1.3 31/58] hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs

In the GICv3 ITS model, we have a common coding pattern which has a local C struct like "DTEntry dte", which is a C representation of an in-guest-memory data structure, and we call a function such as get_dte() to read guest memory and fill in the C struct. These functions to read in the struct som

[Stable-8.2.9 05/45] virtio-net: Fix size check in dhclient workaround

work_around_broken_dhclient() accesses IP and UDP headers to detect relevant packets and to calculate checksums, but it didn't check if the packet has size sufficient to accommodate them, causing out-of-bound access hazards. Fix this by correcting the size requirement. Fixes: 1d41b0c1ec66 ("Work a

[Stable-8.2.9 16/45] hw/nvme: fix msix_uninit with exclusive bar

Commit fa905f65c554 introduced a machine compatibility parameter to enable an exclusive bar for msix. It failed to account for this when cleaning up. Make sure that if an exclusive bar is enabled, we use the proper cleanup routine. Cc: qemu-sta...@nongnu.org Fixes: fa905f65c554 ("hw/nvme: add mach

[Stable-9.1.3 08/58] plugins: add missing export for qemu_plugin_num_vcpus

Fixes: 4a448b148ca ("plugins: add qemu_plugin_num_vcpus function") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier Message-Id: <20241112212622.3590693-2-pierrick.bouv...@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20241121165806.476008-

[Stable-9.1.3 06/58] qdev: Fix set_pci_devfn() to visit option only once

pci_devfn properties accept either a string or an integer as input. To implement this, set_pci_devfn() first tries to visit the option as a string, and if that fails, it visits it as an integer instead. While the QemuOpts visitor happens to accept this, it is invalid according to the visitor interf

[Stable-8.2.9 36/45] target/i386/cpu: Fix notes for CPU models

Fixes: 644e3c5d812 ("missing vmx features for Skylake-Server and Cascadelake-Server") Signed-off-by: Han Han Reviewed-by: Chenyi Qiang Reviewed-by: Michael Tokarev Signed-off-by: Michael Tokarev (cherry picked from commit 93dcc9390e5ad0696ae7e9b7b3a5b08c2d1b6de6) Signed-off-by: Michael Tokarev

Re: [PATCH v2 06/13] hw/sd/sd: Remove legacy sd_set_cb() in favor of GPIOs

Am 28. Januar 2025 10:34:23 UTC schrieb Peter Maydell : >On Mon, 27 Jan 2025 at 23:11, Bernhard Beschow wrote: >> >> >> >> Am 27. Januar 2025 13:24:46 UTC schrieb Peter Maydell >> : >> >On Sat, 11 Jan 2025 at 18:37, Bernhard Beschow wrote: >> >> >> >> Commit ce5dd27534b0 "hw/sd: Remove omap2

[PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

From: Helge Deller The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know why it was decided then why Linux should not use space register hashing. 32-bit HP-UX versions seem

[PATCH 3/4] target/hppa: 64-bit CPUs start with space register hashing enabled

From: Helge Deller Turn on space register hashing for 64-bit CPUs when reset. Signed-off-by: Helge Deller --- target/hppa/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4..c86f9190d2 100644 --- a/target/hppa/cpu.c +++ b/targe

[PATCH 2/4] target/hppa: Add instruction decoding for mfdiag and mtdiag

From: Helge Deller Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag instructions which modify the diagnose registers. diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in commit 3bdf20819e68 based on some analysis of ODE code, but now they conflict with the generic

[PATCH 1/4] target/hppa: Add CPU diagnose registers

From: Helge Deller Add the diagnose registers (%dr) to the CPUArchState. Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. Signed-off-by: Helge Deller --- target/hppa/cpu.h | 1 + target/hppa/mac

[PATCH v2] target/hppa: Implement CPU diagnose registers for 64-bit HP-UX

This series of 4 patches incorporates the changes as suggested by Richard regarding PATCH #3 from my previous series. Please review. Helge

Re: [PATCH 0/5] tests/functional: Update Aspeed OpenBMC images

Hi Cédric, On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote: > Hello, > > This series updates the OpenBMC firmware images to the latest version > for existing tests and also adds 2 new tests for Aspeed machines > which > were not tested before : witherspoon and bletchley. > > Thanks, >

Re: [PATCH 4/5] target/riscv/csr.c: fix deadcode in aia_smode32()

On Wed, Jan 22, 2025 at 4:53 AM Daniel Henrique Barboza wrote: > > Coverity reported a DEADCODE ticket in this function, as follows: > > CID 1590358: Control flow issues (DEADCODE) > Execution cannot reach this statement: "return ret;". > > 380 return ret; > >

Re: [PATCH 5/5] target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt()

On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza wrote: > > Coverity reported a BAD_SHIFT issue in the following code: > > > 2097 > CID 1590355: Integer handling issues (BAD_SHIFT) > In expression "hdeleg >> cause", right shifting by more than 63 >bits has u

Re: [PATCH 1/2] target/riscv: Fix the hpmevent mask

On Thu, Jan 16, 2025 at 10:51 AM Atish Patra wrote: > > As per the latest privilege specification v1.13[1], the sscofpmf > only reserves first 8 bits of hpmeventX. Update the corresponding > masks accordingly. > > [1]https://github.com/riscv/riscv-isa-manual/issues/1578 > > Signed-off-by: Atish Pa

Re: [PATCH 2/2] target/riscv: Mask out upper sscofpmf bits during validation

On Thu, Jan 16, 2025 at 10:51 AM Atish Patra wrote: > > As per the ISA definition, the upper 8 bits in hpmevent are defined > by Sscofpmf for privilege mode filtering and overflow bits while the > lower 56 bits are desginated for platform specific hpmevent values. > For the reset case, mhpmevent v

Re: [PATCH 3/5] target/riscv/csr.c: fix deadcode in rmw_xiregi()

On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza wrote: > > Coverity found a DEADCODE issue in rmw_xiregi() claiming that we can't > reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label: > > > 2652 done: > CID 1590357: Control flow issues (DEADCODE) > E

Re: CXL emulation on aarch64

> On Jan 22, 2025, at 23:07, Jonathan Cameron > wrote: > > On Fri, 17 Jan 2025 09:43:11 + > Jonathan Cameron via wrote: > >> On Fri, 17 Jan 2025 10:13:41 +0900 >> Itaru Kitayama wrote: >> On Jan 16, 2025, at 19:58, Jonathan Cameron wrote: On Thu, 16 Jan 2025 15:

Re: [PATCH v6 10/10] docs/system: virtio-gpu: Document host/guest requirements

On Sun, Jan 26, 2025 at 12:14 PM Dmitry Osipenko < dmitry.osipe...@collabora.com> wrote: > From: Alex Bennée > > This attempts to tidy up the VirtIO GPU documentation to make the list > of requirements clearer. There are still a lot of moving parts and the > distros have some catching up to do be

Re: [PATCH v2 3/4] target/riscv: add RVA23U64 profile

On Wed, Jan 15, 2025 at 5:02 AM Daniel Henrique Barboza wrote: > > Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since > all RVA22U64 mandatory extensions are also present in RVA23U64. What's > left then is to list the mandatory extensions that are RVA23 only. > > A new "rva23u64

[PATCH v2 21/34] target/arm: Use float*_maybe_ah_chs in sve_fcadd_*

The construction of neg_imag and neg_real were done to make it easy to apply both in parallel with two simple logical operations. This changed with FPCR.AH, which is more complex than that. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 51 +++

[PATCH v2 20/34] target/arm: Use float*_maybe_ah_chs in sve_fcadd_*

The construction of neg_imag and neg_real were done to make it easy to apply both in parallel with two simple logical operations. This changed with FPCR.AH, which is more complex than that. Note that there was a naming issue with neg_imag and neg_real. They were named backward, with neg_imag bein

[PATCH v2 06/34] target/arm: Introduce CPUARMState.vfp.fp_status[]

Move ARMFPStatusFlavour to cpu.h with which to index this array. For now, place the array in an anonymous union with the existing structures. Adjust the order of the existing structures to match the enum. Simplify fpstatus_ptr() using the new array. Signed-off-by: Richard Henderson --- target

[PATCH v2 01/34] target/arm: Rename FPST_FPCR_A32 to FPST_A32

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++-- target/arm/tcg/translate-vfp.c | 54 +- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 59e780df2e..6ce2471

[PATCH v2 29/34] Revert "target/arm: Handle FPCR.AH in FMLSL"

This reverts commit c5eb0b62e603c1d391ee2199108f0eb34aadc8f5. --- target/arm/tcg/translate-a64.c | 4 ++-- target/arm/tcg/vec_helper.c| 28 2 files changed, 6 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a6

[PATCH v2 34/34] target/arm: Sink fp_status and fpcr access into do_fmlal*

Sink common code from the callers into do_fmlal and do_fmlal_idx. Reorder the arguments to minimize the re-sorting from the caller's arguments. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 28 1 file changed, 16 insertions(+), 12 deletions(-)

[PATCH v2 13/34] target/arm: Remove fp_status_a64

Replace with fp_status[FPST_A64]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 10 +- target/arm/vfp_helper.c | 16 5 files changed, 15

[PATCH v2 31/34] target/arm: Handle FPCR.AH in sve2_fmlal_zzxw_s

Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 9b14885ef2..c716bd774a 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tc

[PATCH v2 17/34] target/arm: Move float*_ah_chs to vec_internal.h

Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 20 target/arm/tcg/helper-a64.c | 15 +-- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 094f5c169c..a67393

[PATCH v2 33/34] target/arm: Read fz16 from env->vfp.fpcr

Read the bit from the source, rather than from the proxy via get_flush_inputs_to_zero. This makes it clear that it does not matter which of the float_status structures is used. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6

[PATCH v2 30/34] target/arm: Handle FPCR.AH in gvec_fmlal_a64

Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 71 - 1 file changed, 46 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index b3ed6533bb..9b14885ef2 100644 --- a/target/arm/tcg/vec_helpe

[PATCH v2 32/34] target/arm: Handle FPCR.AH in sve2_fmlal_zzzw_s

Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index c716bd774a..bae98a34b8 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tc

[PATCH v2 22/34] target/arm: Use flags for AH negation in do_fmla_zpzzz_*

The float*_muladd functions have a flags argument that can perform optional negation of various operand. We don't use that for "normal" arm fmla, because the muladd flags are not applied when an input is a NaN. But since FEAT_AFP does not negate NaNs, this behaviour is exactly what we need. Sinc

[PATCH v2 15/34] target/arm: Simplify fp_status indexing in mve_helper.c

Select on index instead of pointer. No functional change. Signed-off-by: Richard Henderson --- target/arm/tcg/mve_helper.c | 40 + 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 3

[PATCH v2 04/34] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 ++--- target/arm/tcg/translate-a64.c | 44 +++ target/arm/tcg/translate-sve.c | 66 +- 3 files changed, 59 insertions(+), 59 deletions(-) diff --git a/target/arm/tcg/tran

[PATCH v2 00/34] target/arm: FEAT_AFP followups for FEAT_SME2

Hi Peter, I know you've sent a PR with some of this, but I don't have a complete tree against which to rebase. So this is still Based-on: 20250124162836.2332150-1-peter.mayd...@linaro.org ("[PATCH 00/76] target/arm: Implement FEAT_AFP and FEAT_RPRES") Up to patch 22 is unchanged; after patch 22

[PATCH v2 23/34] target/arm: Use flags for AH negation in sve_ftmad_*

Because the operand is known to be negative, negating the operand is the same as taking the absolute value. Defer this to the muladd operation via flags, so that it happens after NaN detection, which is correct for FPCR.AH. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 27 +

Re: [PATCH v3 1/2] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs

On Wed, Jan 22, 2025 at 3:07 AM Daniel Henrique Barboza wrote: > > The mcontrol select bit (19) is always zero, meaning our triggers will > always match virtual addresses. In this condition, if the user does not > specify a size for the trigger, the access size defaults to XLEN. > > At this moment

[PATCH v2 27/34] target/arm: Handle FPCR.AH in sve_fcmla_zpzzz_*

Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c| 69 +- target/arm/tcg/translate-sve.c | 2 +- 2 files changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index c12b2600bd..c206ca6

[PATCH v2 14/34] target/arm: Remove fp_status_a32

Replace with fp_status[FPST_A32]. As this was the last of the old structures, we can remove the anonymous union and struct. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 7 +-- target/arm/cpu.c| 2 +- target/arm/vfp_helper.c | 18 +- 3 files change

[PATCH v2 24/34] target/arm: Use flags for AH negation in float*_ah_mulsub_f

The float_muladd_negate_product flag produces the same result as negating either of the multiplication operands, assuming neither of the operands are NaNs. But since FEAT_AFP does not negate NaNs, this behaviour is exactly what we need. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_he

[PATCH v2 28/34] target/arm: Split gvec_fmla_idx_* for fmls and ah_fmls

Split negation cases out of gvec_fmla, creating 6 new helpers. We no longer pass 'neg' as a bit in simd_data. Handle FPCR.AH=0 via xor and FPCR.AH=1 via muladd flags. Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/tcg/translate-a64.c | 17 +++

[PATCH v2 25/34] target/arm: Handle FPCR.AH in gvec_fcmla[hsd]

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/vec_helper.c| 66 -- 2 files changed, 40 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 715760a17b..3

[PATCH v2 19/34] target/arm: Use float*_maybe_ah_chs in sve_ftssel_*

Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 3f38e07829..a2ff3b7f11 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sv

[PATCH v2 08/34] target/arm: Remove standard_fp_status

Replace with fp_status[FPST_STD]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 8 target/arm/tcg/mve_helper.c | 28 ++-- target/arm/tcg/vec_helper.c | 4 ++-- target/arm/vfp_helper.c | 4 ++-- 5 fil

[PATCH v2 26/34] target/arm: Handle FPCR.AH in gvec_fcmla[hs]_idx

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/vec_helper.c| 44 -- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3748f7d145..9

[PATCH v2 11/34] target/arm: Remove fp_status_f16_a64

Replace with fp_status[FPST_A64_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 8 target/arm/vfp_helper.c | 16 5 files changed,

[PATCH v2 07/34] target/arm: Remove standard_fp_status_f16

Replace with fp_status[FPST_STD_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 4 ++-- target/arm/tcg/mve_helper.c | 24 target/arm/vfp_helper.c | 8 4 files changed, 18 insertions(+), 19 deleti

Re: [PATCH 1/4] target/hppa: Add CPU diagnose registers

On 1/28/25 14:45, del...@kernel.org wrote: From: Helge Deller Add the diagnose registers (%dr) to the CPUArchState. Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. Signed-off-by: Helge Deller ---

[PATCH v2 12/34] target/arm: Remove fp_status_f16_a32

Replace with fp_status[FPST_A32_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/vec_helper.c | 4 ++-- target/arm/vfp_helper.c | 14 +++--- 4 files changed, 10 insertions(+), 11 deletions(-) diff --g

Re: [PATCH 1/5] target/riscv/csr.c: fix deadcode in rmw_xireg()

On Wed, Jan 22, 2025 at 4:52 AM Daniel Henrique Barboza wrote: > > Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't > reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label: > > done: > if (ret) { > return (env->virt_enabled && virt) ? >RISCV

Re: [PATCH 0/5] target/riscv: Coverity fixes

On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza wrote: > > Hi, > > This series contains Coverity fixes for issues found in the latest > RISC-V pull made yesterday. > > Coverity CIDs being resolved: 1590355, 1590356, 1590357, 1590358 and > 1590359. > > Patches based on master. > > > Daniel

Re: [PATCH v2 1/4] target/riscv: add ssu64xl

On Wed, Jan 15, 2025 at 5:04 AM Daniel Henrique Barboza wrote: > > ssu64xl is defined in RVA22 as: > > "sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must > be supported)." > > This is always true in TCG and it's mandatory for RVA23, so claim > support for it. > > Signed-off-b

Re: [PATCH 2/5] target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg()

On Wed, Jan 22, 2025 at 4:50 AM Daniel Henrique Barboza wrote: > > Coverity found a second DEADCODE issue in rmw_xireg() claiming that we can't > reach 'RISCV_EXCP_NONE' at the 'done' label: > > > 2706 done: > > 2707 if (ret) { > > 2708 return (env->virt_enabled && virt)

Re: [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off

On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev wrote: > > A behavior of misa.v must be similar as misa.f. > So when this bit's field is turned off, mstatus.vs must be turned off > too. It follows from the privileged manual of RISC-V, paragraph 3.1.1. > "Machine ISA (misa) Register". > > Signed-

Re: [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off

On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev wrote: > > A behavior of misa.v must be similar as misa.f. > So when this bit's field is turned off, mstatus.vs must be turned off > too. It follows from the privileged manual of RISC-V, paragraph 3.1.1. > "Machine ISA (misa) Register". > > Signed-

Re: [PATCH] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0

On Fri, Jan 24, 2025 at 8:16 PM Max Chou wrote: > > According to the Vector Reduction Operations section in the RISC-V "V" > Vector Extension spec, > "If vl=0, no operation is performed and the destination register is not > updated." > > The vd should be updated when vl is larger than 0. > > Signe

Re: [PATCH] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set

On Fri, Jan 24, 2025 at 7:06 PM Max Chou wrote: > > In prop_vlen_set function, there is an incorrect comparison between > vlen(bit) and vlenb(byte). > This will cause unexpected error when user applies the `vlen=1024` cpu > option with a vendor predefined cpu type that the default vlen is > 1024(v

[PATCH v2 18/34] target/arm: Introduce float*_maybe_ah_chs

Add versions of float*_ah_chs which takes fpcr_ah. These will help simplify some usages. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index a67

[PATCH v2 02/34] target/arm: Rename FPST_FPCR_A64 to FPST_A64

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 +-- target/arm/tcg/translate-a64.c | 78 +-- target/arm/tcg/translate-sme.c | 4 +- target/arm/tcg/translate-sve.c | 98 +- 4 files changed, 94 insertions(+), 94 dele

[PATCH v2 05/34] target/arm: Rename FPST_FPCR_AH* to FPST_AH*

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 14 +++--- target/arm/tcg/translate-a64.c | 8 target/arm/tcg/translate-sve.c | 8 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/transla

[PATCH v2 16/34] target/arm: Simplify DO_VFP_cmp in vfp_helper.c

Pass ARMFPStatusFlavour index instead of fp_status[FOO]. Signed-off-by: Richard Henderson --- target/arm/vfp_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index a2775a2e8d..4e242275e7 100644 --- a/target/

[PATCH v2 03/34] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++--- target/arm/tcg/translate-vfp.c | 24 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2edb707b85..adf6eb8b91 1006

Re: [PATCH 2/4] target/hppa: Add instruction decoding for mfdiag and mtdiag

On 1/28/25 14:45, del...@kernel.org wrote: From: Helge Deller Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag instructions which modify the diagnose registers. diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in commit 3bdf20819e68 based on some analysis of ODE

Re: [PATCH v3 2/2] target/riscv: throw debug exception before page fault

On Wed, Jan 22, 2025 at 3:08 AM Daniel Henrique Barboza wrote: > > In the RISC-V privileged ISA section 3.1.15 table 15, it is determined > that a debug exception that is triggered from a load/store has a higher > priority than a possible fault that this access might trigger. > > This is not the c

Re: [PATCH v3 0/2] target/riscv: throw debug exception before page fault

On Wed, Jan 22, 2025 at 3:07 AM Daniel Henrique Barboza wrote: > > Hi, > > In this new version, in patch 2, we're using the address 'size' val from > riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN. > > No other changes made. Patches based on master. > > Changes from v2: > - patch 2

Re: [PATCH 3/4] target/hppa: 64-bit CPUs start with space register hashing enabled

On 1/28/25 14:45, del...@kernel.org wrote: From: Helge Deller Turn on space register hashing for 64-bit CPUs when reset. Signed-off-by: Helge Deller --- target/hppa/cpu.c | 5 + 1 file changed, 5 insertions(+) Reviewed-by: Richard Henderson r~

[PATCH v2 10/34] target/arm: Remove ah_fp_status

Replace with fp_status[FPST_AH]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 3 +-- target/arm/cpu.c| 6 +++--- target/arm/vfp_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f7d5d5430..5e3d

Re: [PATCH v2] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking

On Wed, Jan 15, 2025 at 1:52 PM Huang Borong wrote: > > Remove the redundant masking of "hart_idx", as the same operation is > performed later during address calculation. > > This change impacts the "hart_idx" value in the final qemu_log_mask() > call. The original "hart_idx" parameter should be u

Re: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

On 1/28/25 14:45, del...@kernel.org wrote: +if (ctx->is_pa20 && (a->dr == 2)) { +/* Exit TB to recalculate gva_offset_mask on %dr2 */ +ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; +} Where does this update happen? I think you've missed that step. r~

Re: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

On 1/28/25 14:45, del...@kernel.org wrote: @@ -4635,6 +4640,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); +ctx

[PATCH v2 09/34] target/arm: Remove ah_fp_status_f16

Replace with fp_status[FPST_AH_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 3 +-- target/arm/cpu.c| 2 +- target/arm/vfp_helper.c | 10 +- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18afff850

Re: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

On 1/28/25 17:52, Richard Henderson wrote: On 1/28/25 14:45, del...@kernel.org wrote: +    if (ctx->is_pa20 && (a->dr == 2)) { +    /* Exit TB to recalculate gva_offset_mask on %dr2 */ +    ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; +    } Where does this update happen?  I think you've

Re: [PATCH v2 2/4] target/riscv: use RVB in RVA22U64

On Wed, Jan 15, 2025 at 5:04 AM Daniel Henrique Barboza wrote: > > From the time we added RVA22U64 until now the spec didn't declare 'RVB' > as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec > [1] added the following in the 'RVA22U64 Mandatory Extensions' section: > > "B Bit-ma

Re: [PATCH 07/21] hw/arm/fsl-imx8mp: Add SNVS

On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote: > > SNVS contains an RTC which allows Linux to deal correctly with time. This is > particularly useful when handling persistent storage which will be done in the > next patch. > > Signed-off-by: Bernhard Beschow > --- > docs/system/arm/imx8mp

[RFC PATCH 1/9] accel/tcg: Simplify use of &first_cpu in rr_cpu_thread_fn()

Let vCPUs wait for themselves being ready first, then other ones. This allows the first thread to starts without the global vcpu queue (thus &first_cpu) being populated. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops-rr.c | 15 --- 1 file changed, 8 insertions(+),

Re: [PATCH 3/7] tests/qtest/migration: Initialize MigrationTestEnv::arch early

Philippe Mathieu-Daudé writes: > Some tests expect MigrationTestEnv::arch to be set. Initialize > it early enough to avoid SIGSEGV, for example like the following > g_str_equal() call in migration/precopy-tests.c: > >954 void migration_test_add_precopy(MigrationTestEnv *env) >955 { >.

Re: [PATCH 7/7] tests/qtest/migration: Allow using accelerators different of TCG / KVM

Philippe Mathieu-Daudé writes: > There is no particular reason to restrict all the framework > to TCG or KVM, since we can check on a per-test basis which > accelerator is available (via MigrationTestEnv::has_$ACCEL). The reason is: CONFIG_KVM=n CONFIG_TCG=n The check is about "there is no acc

Re: [PATCH 5/7] tests/qtest/migration: Add MigrationTestEnv::has_hvf field

Philippe Mathieu-Daudé writes: > Allow tests to tune their parameters when running on HVF. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas

Re: [PATCH 4/7] tests/qtest/migration: Pass accelerator arguments as machine option

Philippe Mathieu-Daudé writes: > The '-accel' CLI option is handler as sugar property as > '-machine,accel='. Replace the migration tests command > line, only using the best accelerator available (first > hardware, then software). > > Signed-off-by: Philippe Mathieu-Daudé > --- > tests/qtest/mi

[PATCH] hw/arm/virt: Support larger highmem MMIO regions

The MMIO region size required to support virtualized environments with large PCI BAR regions can exceed the hardcoded limit configured in QEMU. For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO (currentl

[PATCH 2/5] disas/hppa: implement mfdiag/mtdiag disassembly

From: Helge Deller The various PA-RISC CPUs implement different CPU-specific diag instructions (mfdiag, mtdiag, mfcpu, mtcpu, ...) to access CPU-internal diagnose/configuration registers, e.g. for cache control, managing space register hashing, control front panel LEDs and read status of the hard

Re: [PATCH] target/arm: Drop unused AARCh64DecodeTable typedefs

On 1/28/25 05:50, Peter Maydell wrote: We removed the old table-based decoder in favour of decodetree, but we left a couple of typedefs that are now unused; delete them. Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 11 --- 1 file changed, 11 deletions(-) Oops.

RE: [PATCH] hw/arm/virt: Support larger highmem MMIO regions

> -Original Message- > From: Matthew R. Ochs > Sent: Tuesday, January 28, 2025 4:03 PM > To: qemu-devel@nongnu.org; Shameerali Kolothum Thodi > ; nath...@nvidia.com > Cc: ddut...@redhat.com; eric.au...@redhat.com; nicol...@nvidia.com; > ank...@nvidia.com > Subject: [PATCH] hw/arm/virt:

Re: [PATCH] hw/arm/virt: Support larger highmem MMIO regions

Hi Matthew, Shameer, On 1/28/25 6:36 PM, Shameerali Kolothum Thodi wrote: > >> -Original Message- >> From: Matthew R. Ochs >> Sent: Tuesday, January 28, 2025 4:03 PM >> To: qemu-devel@nongnu.org; Shameerali Kolothum Thodi >> ; nath...@nvidia.com >> Cc: ddut...@redhat.com; eric.au...@redh

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