On 1/24/25 08:28, Peter Maydell wrote:
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
Hi Paolo,
On Fri, Jan 17, 2025 at 08:39:55PM +0100, Paolo Bonzini wrote:
> Date: Fri, 17 Jan 2025 20:39:55 +0100
> From: Paolo Bonzini
> Subject: [PATCH 02/10] rust: qom: add reference counting functionality
> X-Mailer: git-send-email 2.47.1
>
> Add a smart pointer that allows to add and remove
From: Yanfeng Liu
This enables generic timer feature for Cortex-R5 so that to support guests
like NuttX RTOS.
Signed-off-by: Yanfeng Liu
---
target/arm/tcg/cpu32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2ad218
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Simplify cpu-target.c by extracting mixed vmstate code
into the cpu_vmstate_register() / cpu_vmstate_unregister()
helpers, implemented in cpu-user.c and cpu-system.c.
Signed-off-by: Philippe Mathieu-Daudé
---
XXX: tlb_flush() temporary declared ma
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Now that cpu_exec_realizefn() and cpu_exec_unrealizefn()
methods don't use any target specific definition anymore,
we can move them to cpu-common.c to be able to build them
once.
Signed-off-by: Philippe Mathieu-Daudé
---
Eventually they'll be absor
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Rather than using the obscure system_bus_info.instance_size,
directly use sizeof(BusState).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/sysbus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Nice.
Reviewed-by: Richard Hende
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/sysbus.c
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically
plugged on the TYPE_PLATFORM_BUS_DEVICE.
Rather than sometimes noting that with comment around
the 'user_creatable = true' line in each DeviceRealize
handler, introduce an abstract TYPE_DYNAMIC
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
cpu_memory_rw_debug() system implementation is defined in
system/physmem.c. Move the user one to accel/tcg/user-exec.c
to simplify cpu-target.c maintenance.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/user-exec.c | 92 ++
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Fix style on code we are going to modify.
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 6d8b7825746..a2999e7c3c0 100644
---
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7
("Use a dedicated function to request exit from execution
loop"), tlb_flush() and tb_flush() are related to TCG
accelerator.
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 33 +++
On 1/24/25 13:10, Michael Clark wrote:
+static x86_opc_prefix x86_table_make_prefix(const x86_opc_data *d,
+const x86_opr_data *o, const x86_ord_data *p)
+{
+x86_opc_prefix tp;
+memset(&tp, 0, sizeof(tp));
+
+/* extract prefix and synthesize width prefixes */
+switch (x86_enc_
On 1/21/25 07:26, Akihiko Odaki wrote:
...
>>> I feel the dependency information for virglrenderer and Mesa are more
>>> suited for the Mesa documentation as they are not specific to QEMU and
>>> potentially useful also for e.g., libkrun and crosvm.
>>
>> I think while everything is in so much flux
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Slighly simplify cpu-target.c again by extracting cpu_exec_initfn()
to cpu-{system,user}.c, adding an empty stub for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
Good enough for now...
---
cpu-target.c | 9 -
hw/core
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Do not explain why _X86_IOMMU devices are user_creatable,
have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to explicit
they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/amd_iommu.c | 2 -
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Because the RAM FB device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/ramfb-standalone.c | 3 +--
1 file changed, 1 insertion(+), 2
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Do not explain why VFIO_PLATFORM devices are user_creatable,
have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to explicit
they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE.
to make it explicit that they can be
Reviewed-by: Richard Henderso
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Because the network eTSEC device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/fsl_etsec/etsec.c | 4 +---
1 file changed, 1 insertion(+)
On 1/25/25 10:13, Philippe Mathieu-Daudé wrote:
Because the TPM TIS sysbus device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_tis_sysbus.c | 3 +--
1 file changed, 1 insertion(+),
On Sun, Jan 26, 2025 at 3:56 PM Jason Wang wrote:
>
> On Sat, Jan 25, 2025 at 12:42 AM Peter Xu wrote:
> >
> > Hello, Jason, Eric,
> >
> > On Fri, Jan 24, 2025 at 11:30:56AM +0800, Jason Wang wrote:
> > > It might be because neither virtio bus nor virtio-net provides a
> > > shutdown method.
> >
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
TCGCPUOps structure makes more sense in the accelerator context
rather than hardware emulation. Move it under the accel/tcg/ scope.
Mechanical change doing:
$ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \
$(git grep -l hw/core
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
The heavily imported "system/cpus.h" header includes "accel-ops.h"
to get AccelOpsClass type declaration. Reduce headers pressure by
forward declaring it in "qemu/typedefs.h", where we already
declare the AccelCPUState type.
Reduce "system/cpus.h"
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Rather than maintaining a mix of system / user code for CPU
class properties, move system properties to cpu-system.c
and user ones to the new cpu-user.c unit.
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 58 ---
On 25.01.25 10:13, Philippe Mathieu-Daudé wrote:
Some SysBus devices can optionally be dynamically plugged onto
the sysbus-platform-bus (then virtual guests are aware of
mmio mapping and IRQs via device tree / ACPI rules).
This series makes these devices explicit by having them implement
the D
On 1/24/25 08:28, Peter Maydell wrote:
Handle FPCR.NEP merging for scalar FABS and FNEG; this requires
an extra parameter to do_fp1_scalar_int(), since FMOV scalar
does not have the merging behaviour.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 27
On 1/24/25 08:28, Peter Maydell wrote:
Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_
On 1/24/25 08:28, Peter Maydell wrote:
Handle FPCR.NEP in the operations handled by do_cvtf_scalar().
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH == 1 semantics for vector FMIN/FMAX, by
creating new_ah_ versions of the gvec helpers which invoke the
scalar fmin_ah and fmax_ah helpers on each element.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 +
On 1/25/25 08:58, Philippe Mathieu-Daudé wrote:
Add a class_post_init() handler to be called by parents
*after* child class_init() handler is called. This is
necessary to have parent class check children properly
set some values or mandatory handlers.
Philippe Mathieu-Daudé (2):
qom: Declare
On 1/25/25 09:01, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Cc:qemu-ri...@nongnu.org
---
target/riscv/internals.h | 4 +++-
target/riscv/cpu.c | 8 +++-
2 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/24/25 08:28, Peter Maydell wrote:
Handle FPCR.NEP for the 1-input scalar operations.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/25/25 09:01, Philippe Mathieu-Daudé wrote:
diff --git a/cpu-target.c b/cpu-target.c
index 98e9e7cc4a1..778f622b07a 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -230,6 +230,14 @@ void cpu_class_init_props(DeviceClass *dc)
device_class_set_props(dc, cpu_common_props);
}
+void cpu
On 1/24/25 08:28, Peter Maydell wrote:
do_fp3_scalar_idx() is used only for the FMUL and FMULX scalar by
element instructions; these both need to merge the result with the Rn
register when FPCR.NEP is set.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file chan
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the_ah_ helper for the reduction step when
FPCR.AH == 1.
Signed-off-by: Peter Maydell
---
target/a
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c | 25 +
ta
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH semantics for the SVE FMAXV and FMINV
vector-reduction-to-scalar max/min operations.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 +++
target/arm/tcg/sve_helper.c| 43 +
On 1/24/25 08:28, Peter Maydell wrote:
Split the handling of vector FABD so that it calls a different set
of helpers when FPCR.AH is 1, which implement the "no negation of
the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4
target/arm/tcg/t
On 1/24/25 08:28, Peter Maydell wrote:
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
Signed-off-by: Peter Mayde
On 1/24/25 08:28, Peter Maydell wrote:
Make the SVE FABD insn honour the FPCR.AH "don't negate the sign
of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 7 +++
target/arm/tcg/sve_helper.c| 22 ++
target/arm/tcg/translate-sve.
On 1/24/25 08:28, Peter Maydell wrote:
+if (neg_real && !(fpcr_ah && float16_is_any_nan(e1))) {
+e1 ^= neg_real;
+}
+if (neg_imag && !(fpcr_ah && float16_is_any_nan(e3))) {
+e3 ^= neg_imag;
+}
Drop the neg_real/neg_
On 1/24/25 08:28, Peter Maydell wrote:
Make SVE FNEG honour the FPCR.AH "don't negate the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files chan
On 1/24/25 08:28, Peter Maydell wrote:
Make SVE FABS honour the FPCR.AH "don't negate the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files chan
On 1/24/25 08:28, Peter Maydell wrote:
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitiv
On 1/24/25 08:28, Peter Maydell wrote:
Honour the FPCR.AH "don't negate the sign of a NaN" semantics in
FMLSL. We pass in the value of FPCR.AH in the SIMD data field, and
use this to determine whether we should suppress the negation for
NaN inputs.
Signed-off-by: Peter Maydell
---
target/arm/t
On 1/24/25 08:28, Peter Maydell wrote:
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in the vector versions of FRECPS and FRSQRTS, by implementing
new vector wrappers that call the_ah_ scalar helpers.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14
On 1/24/25 08:28, Peter Maydell wrote:
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS
(indexed), by passing through FPCR.AH in the SIMD data word, for the
helper to use to determine whether to negate.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 2 +-
On 1/24/25 08:28, Peter Maydell wrote:
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the
SVE FMLS (vector) insns, by providing new helpers for the AH=1 case
which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions
that do the work.
Signed-off-by: Peter Maydell
---
On 1/24/25 08:28, Peter Maydell wrote:
The x86 DE bit in the FPU and MXCSR status is supposed to be set
when an input denormal is consumed. We didn't previously report
this from softfloat, so the x86 code either simply didn't set
the DE bit or else incorrectly wired it up to denormal_flushed,
dep
On 1/24/25 08:28, Peter Maydell wrote:
The softfloat get_float_exception_flags() function returns 'int', but
in various places in target/i386 we incorrectly store the returned
value into a uint8_t. This currently has no ill effects because i386
doesn't care about any of the float_flag enum value
On 1/24/25 08:28, Peter Maydell wrote:
Add some fma test cases that check for correct handling of FTZ and
for the flag that indicates that the input denormal was consumed.
Signed-off-by: Peter Maydell
---
tests/tcg/x86_64/fma.c | 12
1 file changed, 12 insertions(+)
diff --git
On 1/24/25 08:28, Peter Maydell wrote:
Implement the increased precision variation of FRSQRTE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRSqrtEstimate() and
RecipSqrtEstimate() functions.
Signed-off-by: Peter Maydell
---
target/arm/vfp_hel
On 1/24/25 08:27, Peter Maydell wrote:
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 2d37d7c9f21..a7509b314b0 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -671,6 +671,8 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const
Translatio
On 2025/01/27 3:06, Dmitry Osipenko wrote:
On 1/21/25 07:26, Akihiko Odaki wrote:
...
I feel the dependency information for virglrenderer and Mesa are more
suited for the Mesa documentation as they are not specific to QEMU and
potentially useful also for e.g., libkrun and crosvm.
I think while
On 1/24/25 08:27, Peter Maydell wrote:
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -673,6 +673,8 @@ typedef enum ARMFPStatusFlavour {
FPST_FPCR_A32,
FPST_FPCR_A64,
FPST_FPCR_F16,
+FPST_FPCR_F16_A32,
+FPST_FPCR_F16_A64,
FPST_STD,
FPST_
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the RAM FB device can be optionally plugged on
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Rather than using the obscure system_bus_info.instance_s
> +impl Owned {
> +/// Convert a raw C pointer into an owned reference to the QOM
> +/// object it points to. The object's reference count will be
> +/// decreased when the `Owned` is dropped.
> +///
> +/// # Panics
> +///
> +/// Panics if `ptr` is NULL.
> +///
> +
On 23/1/25 22:56, Philippe Mathieu-Daudé wrote:
Make is_prefix_insn_excp() prototype but have it guarded by
a tcg_enabled() check. Inline part of it in powerpc_excp_books().
Extract POWERPC_EXCP_HV_EMU handling code to ppc_tcg_hv_emu(),
also exposing its prototype in "internal.h".
Signed-off-by
On Mon, Jan 20, 2025 at 10:09 AM Ani Sinha wrote:
>
> A new qtest is written that exercizes the fw-cfg DMA based read and write ops
> to write values into vmcoreinfo fw-cfg file and read them back and verify that
> they are the same.
>
> Signed-off-by: Ani Sinha
Final ping on this patch.
> ---
On Mon, Jan 20, 2025 at 10:09 AM Ani Sinha wrote:
>
> At present, the libqos/fw_cfg.c library does not support the modern DMA
> interface which is required to write to the fw_cfg files. It only uses the IO
> interface. Implement read and write methods based on DMA. This will enable
> developers to
Reviewed-by: Clément Mathieu--Drif
Thanks phil
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Do not explain why _X86_IOMMU devices are u
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the TPM TIS sysbus device can be optionally plug
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> When multiple QOM types are registered in the same file,
On 24/01/2025 14.58, Alex Bennée wrote:
Thomas Huth writes:
We don't have any functional tests for this machine yet, thus let's
add a test with a MicroPython binary that is available online
We do have a basic system test:
test-armv6m-undef: test-armv6m-undef.S
$(CC) -mcpu=cort
Reviewed-by: Clément Mathieu--Drif
On 25/01/2025 19:13, Philippe Mathieu-Daudé wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Because the network eTSEC device can be optionally plugg
On 2025/01/27 5:11, Dmitry Osipenko wrote:
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by
Philippe Mathieu-Daudé writes:
> Add a class_post_init() handler to be called by parents
> *after* child class_init() handler is called. This is
> necessary to have parent class check children properly
> set some values or mandatory handlers.
>
> Signed-off-by: Philippe Mathieu-Daudé
Plausible,
On 26/1/25 13:31, Richard Henderson wrote:
On 1/25/25 09:01, Philippe Mathieu-Daudé wrote:
diff --git a/cpu-target.c b/cpu-target.c
index 98e9e7cc4a1..778f622b07a 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -230,6 +230,14 @@ void cpu_class_init_props(DeviceClass *dc)
device_class_set_p
On 1/24/25 08:28, Peter Maydell wrote:
The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve_helper.c|
On 1/24/25 08:28, Peter Maydell wrote:
The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve_helper.c| 2
On 1/24/25 08:28, Peter Maydell wrote:
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we
can enable FEAT_AFP for '-cpu max', and document that we support it.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files cha
On 1/24/25 08:28, Peter Maydell wrote:
Implement the increased precision variation of FRECPE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRecipEstimate() and
RecipEstimate() functions.
Signed-off-by: Peter Maydell
---
target/arm/vfp_helper.c
On 1/24/25 08:28, Peter Maydell wrote:
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4
target/arm/tcg/translate-a64.c | 7 ++-
On 1/24/25 08:28, Peter Maydell wrote:
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
Reviewed-by: Richard Henderson
On 1/24/25 08:28, Peter Maydell wrote:
The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we
flush outputs to zero when we detect underflow, which is after
rounding. Set the detect_ftz flag accordingly.
This allows us to enable the test in fma.c which checks this
behaviour.
Signed-o
On 1/23/25 15:43, Philippe Mathieu-Daudé wrote:
Use the tcg_enabled() check so the compiler can elide
the call when TCG isn't available, allowing to remove
the tb_flush() stub.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/stubs/tcg-stub.c | 4
gdbstub/system.c | 5 -
2 file
On 1/23/25 15:43, Philippe Mathieu-Daudé wrote:
Keep common MMAP-related declarations in a single place.
Note, this disable ThreadSafetyAnalysis on Linux for:
- mmap_fork_start()
- mmap_fork_end().
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h| 12 +---
include/us
On 1/23/25 15:43, Philippe Mathieu-Daudé wrote:
cpu_common_initfn() is our target agnostic initializer,
while cpu_exec_initfn() is the target specific one.
The %as and %num_ases fields are not target specific,
so initialize them in the common helper.
Signed-off-by: Philippe Mathieu-Daudé
---
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
While cpu-exec.c is build for each target,tcg_flags helpers
aren't target specific. Move them to cpu-exec-common.c to
build them once.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec-common.c | 33 +
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
Missed in commit b86f59c7155 ("accel: replace struct CpusAccel
with AccelOpsClass") which removed the single CpusAccel use.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-cpus.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/acce
On 1/25/25 08:05, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Cc:qemu-ri...@nongnu.org
---
target/riscv/internals.h | 4 +++-
target/riscv/cpu.c | 8 +++-
2 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
Hi Richard,
On Fri, Oct 13, 2023 at 11:29 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/sparc/insns.decode | 4 ++
> target/sparc/translate.c | 105 +++---
> 2 files changed, 46 insertions(+), 63 deletions(-)
>
> diff --git a/
On 1/24/25 08:28, Peter Maydell wrote:
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 05036089dd7..406d76e1129 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -399,6 +399,42 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status
*f
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/
On 1/24/25 08:28, Peter Maydell wrote:
Implement the FPCR.AH semantics for the SVE FMAX and FMIN
operations that take two vector operands.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/transla
On 1/24/25 08:28, Peter Maydell wrote:
FPCR.AH == 1 mandates that negation of a NaN value should not flip
its sign bit. This means we can no longer use gen_vfp_neg*()
everywhere but must instead generate slightly more complex code when
FPCR.AH is set.
Make this change for the scalar FNEG and fo
On 1/24/25 08:28, Peter Maydell wrote:
FPCR.AH == 1 mandates that taking the absolute value of a NaN should
not change its sign bit. This means we can no longer use
gen_vfp_abs*() everywhere but must instead generate slightly more
complex code when FPCR.AH is set.
Implement these semantics for
On 1/26/25 01:38, Artyom Tarasenko wrote:
Hi Richard,
On Fri, Oct 13, 2023 at 11:29 PM Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 4 ++
target/sparc/translate.c | 105 +++---
2 files changed, 46 insertions(
From: Pierre-Eric Pelloux-Prayer
If EGL is used, we can rely on dmabuf to import textures without
doing copies.
To get this working on X11, we use the existing SDL hint:
SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX).
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirki
Print out error messages when virgl fence creation fails to aid debugging
of the fence-related bugs.
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirkin
Tested-by: Alex Bennée
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 13 -
1 file changed, 12 insertion
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
using a new virtio-gpu-gl device option "drm_native_context=on".
Unlike Virgl and Venus contexts that operate on application API level,
DRM native contexts work on a kernel UAPI level. This lower level results
in a lightweig
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
Extend virtio-gpu documentation with a link to the Mesa VirGL
documentation.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/system/devices/virtio-gpu.rst
b/docs/system/
Change virtio-gpu Venus link, pointing it at the Mesa Venus
documentation instead of the protocol. The Mesa doc provides more
information and also has a link to the protocol.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 2 +-
1 file changed
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
Contarary to Virgl and Venus contexts that mediates high level GFX APIs,
DRM native context [1] mediates lower level kernel driver UAPI, which
reflects in a less CPU overhead and less/simpler code needed to support it.
DRM contex
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by: Alex Bennée
Cc: Sergio Lopez Pascual
Sign
1 - 100 of 105 matches
Mail list logo
