The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we
flush outputs to zero when we detect underflow, which is after
rounding. Set the detect_ftz flag accordingly.
This allows us to enable the test in fma.c which checks this
behaviour.
Signed-off-by: Peter Maydell
---
target/i386/tc
In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
raise the Invalid exception regardless of target architecture. (This
was a change affecting hppa, i386, sh4 and tricore.) However, this
was incorrect for i386, wh
FPCR.AH == 1 mandates that negation of a NaN value should not flip
its sign bit. This means we can no longer use gen_vfp_neg*()
everywhere but must instead generate slightly more complex code when
FPCR.AH is set.
Make this change for the scalar FNEG and for those places in
translate-a64.c which w
Implement the FPCR.AH semantics for the SVE FMAXV and FMINV
vector-reduction-to-scalar max/min operations.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 +++
target/arm/tcg/sve_helper.c| 43 +-
target/arm/tcg/translate-sve.c | 16
Implement the increased precision variation of FRECPE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRecipEstimate() and
RecipEstimate() functions.
Signed-off-by: Peter Maydell
---
target/arm/vfp_helper.c | 54 +++
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the
SVE FMLS (vector) insns, by providing new helpers for the AH=1 case
which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions
that do the work.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 21 +
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in the vector versions of FRECPS and FRSQRTS, by implementing
new vector wrappers that call the _ah_ scalar helpers.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c |
The helpers vfp_cmps, vfp_cmpes, vfp_cmpd, vfp_cmped are used only from
the A32 decoder; the A64 decoder uses separate vfp_cmps_a64 etc helpers
(because for A64 we update the main NZCV flags and for A32 we update
the FPSCR NZCV flags). So we can make these helpers use the fp_status_a32
field instea
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS
(indexed), by passing through FPCR.AH in the SIMD data word, for the
helper to use to determine whether to negate.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate-sve.c | 2 +-
Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
that detect tininess before rounding, but is usually not the right
place when the architecture detects tininess after rounding. For
example, for x86 the SDM states
In the A32 decoder, use FPST_FPCR_A32 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_FPCR_A32/g'
target/arm/tcg/translat
Handle FPCR.NEP in the operations handled by do_cvtf_scalar().
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 64994d3212f..6c20293961a
Move the mips64el replay tests from tests/avocado/replay_kernel.py to
the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to the file where we already use the same asset already.
Signed-off-by: Thom
Move the mips big endian replay tests from tests/avocado/replay_kernel.py
to the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to the file where we already use the same asset already.
Signed-off-b
Move the mipsel replay tests from tests/avocado/replay_kernel.py to
the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to the file where we already use the same asset already.
Signed-off-by: Thomas
Copy the ReplayKernelBase class from the avocado tests. We are going
to need it to convert the related replay tests in the following patches.
Signed-off-by: Thomas Huth
---
tests/functional/replay_kernel.py | 84 +++
1 file changed, 84 insertions(+)
create mode 10064
Some tests have a very long runtime and might run into timeout
issues e.g. when QEMU has been compiled with --enable-debug.
Add a decorator for marking them more easily and document the
corresponding environment variable that is used to enable the
tests.
Signed-off-by: Thomas Huth
---
docs/devel
tests/avocado/replay_kernel.py is a rather big file with a lot of
Avocado-based tests in it. But in the long run, we rather want to
get away from Avocado, so we eventually have to convert these tests
to the functional framework. For this, we have to separate the tests
by target architecture, since
This patch was missed :-) which could free HPETState.flags from a
BqlCell.
> > -/* Push number of timers into capability returned via HPET_ID */
> > -s->capability &= ~HPET_ID_NUM_TIM_MASK;
> > -s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
> > -hpet_cfg.hpet[s->hp
This patch addresses a potential data race involving the global variable
goflag in the rcutorture test.
Fixes: 8fda74a52b ("rcu: add rcutorture")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2750
Signed-off-by: Vitalii Mordan
---
v2: Access goflag using qatomic_read and qatomic_set as
On Thu, 23 Jan 2025 12:23:43 +0100
Igor Mammedov wrote:
> On Thu, 23 Jan 2025 10:52:15 +
> Alex Bennée wrote:
>
> > Igor Mammedov writes:
> >
> > > QEMU will crash with following debug enabled
> > > # define DEBUG_TLB_GATE 1
> > > # define DEBUG_TLB_LOG_GATE 1
> > > due to [1] intro
On Fri, 18 Oct 2024 12:12:52 -0400
Gregory Price wrote:
> From: Svetly Todorov
>
> Using a shared-memory bytemap, validates that DC adds, releases,
> and reclamations happen on extents belonging to the appropriate
> host.
>
I'll carry this on my staging tree for now gitlab.com/jic23/qemu (late
On Fri, 2025-01-24 at 09:49 +0100, Cédric Le Goater wrote:
> On 1/14/25 20:55, Eric Farman wrote:
> > On Tue, 2025-01-14 at 13:51 -0500, Rorie Reyes wrote:
> > > On 1/8/25 2:29 AM, Cédric Le Goater wrote:
> > > > Hello Rorie,
> > > >
> > > > On 1/7/25 19:43, Rorie Reyes wrote:
> > > > > This patch
On Fri, Jan 24, 2025 at 11:00:33AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> >The cursor data virtio-gpu is receiving from the guest has
> >had the alpha channel pre-multiplied into the RGB components.
>
> The kernel driver simply passes through whatever it gets from userspace.
>
> Not sur
On Thu, 23 Jan 2025 10:39:02 +0530
Vinayak Holikatti wrote:
Hi Vinayak,
Thanks for your patch! Good to add support for this.
Various comments inline, but all fairly minor things.
thanks,
Jonathan
> CXL spec 3.1 section 8.2.9.9.5.3 describes media operations commands.
> CXL devices
Booting an s390x VM in record/replay mode hangs due to a deadlock
between rr_cpu_thread_fn() and s390_machine_reset(). The former needs
the record/replay mutex held by the latter, and the latter waits until
the former completes its run_on_cpu() request.
Fix by temporarily dropping the record/repla
The code of gen_Jcc is very similar to gen_LOOP* and gen_JCXZ, but this
is hidden by gen_jcc.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Link: https://lore.kernel.org/r/20241215090613.89588-2-pbonz...@redhat.com
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 8
In a repeated string operation, CX/ECX will be decremented until it
is 0 but never underflow. Use this observation to avoid a deposit or
zero-extend operation if the address size of the operation is smaller
than MO_TL.
As in the previous patch, the patch is structured to include some
preparatory
Now that everything has been cleaned up, look at DF and prefixes
in a single function, and call that one from gen_repz and gen_repz_nz.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 34 ++---
Place struct_name before field_name, similar to offset_of.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device_class.rs | 2 +-
rust/qemu-api/src/vmstate.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/rust/hw/char/pl011/src/device_class.rs
b/rust/
From: Zhao Liu
A safe REALIZE accepts immutable reference.
Since current PL011's realize() only calls a char binding function (
qemu_chr_fe_set_handlers), it is possible to convert mutable reference
(&mut self) to immutable reference (&self), which only needs to convert
the pointers passed to C
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/lib.rs | 4
1 file changed, 4 deletions(-)
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index f30f9850ad4..d10f0805aac 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/p
Hi,
>The cursor data virtio-gpu is receiving from the guest has
>had the alpha channel pre-multiplied into the RGB components.
The kernel driver simply passes through whatever it gets from userspace.
Not sure what userspace passes to the kernel, I suspect it is whatever
typical GPUs ca
From: Helge Deller
Fixes those warnings:
Unsupported host ancillary data: 0/8
Signed-off-by: Helge Deller
Reviewed-by: Laurent Vivier
---
linux-user/syscall.c | 10 ++
linux-user/syscall_defs.h | 6 ++
2 files changed, 16 insertions(+)
diff --git a/linux-user/syscall.c b/l
Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST,
and will be used to create TDX VMs (TDs) by
qemu -machine ...,confidential-guest-support=tdx0 \
-object tdx-guest,id=tdx0
It has one QAPI member 'attributes' defined, which allows user to set
TD's attributes directly.
Pull in recent TDX updates, which are not backwards compatible.
It's just to make this series runnable. It will be updated by script
scripts/update-linux-headers.sh
once TDX support is upstreamed in linux kernel
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 70 ++
On 10/01/2025 14.17, Alex Bennée wrote:
From: Pierrick Bouvier
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Hi,
FWIW, I just saw this test_aarch64_rme_virt test failing once. Looking at
the conso
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise refuse to boot.
Add sept-ve-disable property for tdx-guest object, for user to c
Implement TDX specific ConfidentialGuestSupportClass::kvm_init()
callback, tdx_kvm_init().
Mark guest state is proctected for TDX VM. More TDX specific
initialization will be added later.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- remove Acked-by from Gerd since the patch changed due to us
We should be using the F16-specific float_status for conversions from
half-precision, because halfprec inputs never set Input Denormal.
Without FEAT_AHP, using the wrong fpst here had no effect, because
the only difference between the F16_A64 and A64 fpst is its handling
of flush-to-zero on input
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we
can enable FEAT_AFP for '-cpu max', and document that we support it.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/sy
On Fri, Jan 24, 2025 at 04:56:50PM +1100, Alexey Kardashevskiy wrote:
> > Now, I assume Peter's real question is, if we can copy the vBIOS to a
> > private region and no need to create a specific guest_memfd-backed
> > memory region for it?
Yes.
>
> I guess we can copy it but we have pc.bios and
[Cc'ed Thibaut as author of 3e866365e1eb ("vhost user: add rarp sending
after live migration for legacy guest")]
On Wed, 22 Jan 2025 17:51:07 +0100
Stefano Garzarella wrote:
> On Wed, Jan 22, 2025 at 05:41:15PM +0100, Laurent Vivier wrote:
> >On 22/01/2025 17:20, Stefano Garzarella wrote:
> >>
We are going to need to generate different code in some cases when
FPCR.AH is 1. For example:
* Floating point neg and abs must not flip the sign bit of NaNs
* some insns (FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, and various
BFCVT and BFM bfloat16 ops) need to use a different float_status
Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_fcvtxn[] array for
the FCVTXN (vector) in
On Fri, 24 Jan 2025 at 16:28, Peter Maydell wrote:
>
> This patchset implements emulation of the Arm FEAT_AFP and FEAT_RPRES
> extensions, which are floating-point related. It's based on the
> small i386 bugfix series I sent out a while back:
>
> Based-on: 20250116112536.4117889-1-peter.mayd...@li
In the A32 decoder, use FPST_FPCR_F16_A32 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_FPCR_F16_A32/g'
target/a
Make the SVE FABD insn honour the FPCR.AH "don't negate the sign
of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 7 +++
target/arm/tcg/sve_helper.c| 22 ++
target/arm/tcg/translate-sve.c | 2 +-
3 files changed, 30 insertions(+
Implement the increased precision variation of FRSQRTE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRSqrtEstimate() and
RecipSqrtEstimate() functions.
Signed-off-by: Peter Maydell
---
target/arm/vfp_helper.c | 77 ++
The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve_helper.c| 18 +++---
target/arm/tcg/tra
Hi Thomas,
On 1/24/25 05:29, Thomas Huth wrote:
On 10/01/2025 14.17, Alex Bennée wrote:
From: Pierrick Bouvier
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Hi,
FWIW, I just saw this test_aarch
Make SVE FABS honour the FPCR.AH "don't negate the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 insertions(+), 1 deletion(-)
diff -
Make SVE FNEG honour the FPCR.AH "don't negate the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 insertions(+), 1 deletion(-)
diff -
Handle FPCR.NEP merging for scalar FABS and FNEG; this requires
an extra parameter to do_fp1_scalar_int(), since FMOV scalar
does not have the merging behaviour.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 27 ---
1 file changed, 20 insertions(+), 7
The softfloat get_float_exception_flags() function returns 'int', but
in various places in target/i386 we incorrectly store the returned
value into a uint8_t. This currently has no ill effects because i386
doesn't care about any of the float_flag enum values above 0x40.
However, we want to start u
Right now, we only allow for writing to memory regions that allow direct
access using memcpy etc; all other writes are simply ignored. This
implies that debugging guests will not work as expected when writing
to MMIO device regions.
Let's extend cpu_memory_rw_debug() to write to more memory region
Honour the FPCR.AH "don't negate the sign of a NaN" semantics in
FMLSL. We pass in the value of FPCR.AH in the SIMD data field, and
use this to determine whether we should suppress the negation for
NaN inputs.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 4 ++--
target/arm/
In the A64 decoder, use FPST_FPCR_A32 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_FPCR_A64/g'
target/arm/tcg/transla
When FPCR.AH is set, various behaviours of AArch64 floating point
operations which are controlled by softfloat config settings change:
* tininess and ftz detection before/after rounding
* NaN propagation order
* result of 0 * Inf + NaN
* default NaN value
When the guest changes the value of th
do_fp3_scalar_idx() is used only for the FMUL and FMULX scalar by
element instructions; these both need to merge the result with the Rn
register when FPCR.NEP is set.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
When FPCR.AH = 1, some of the cumulative exception flags in the FPSR
behave slightly differently for A64 operations:
* IDC is set when a denormal input is used without flushing
* IXC (Inexact) is set when an output denormal is flushed to zero
Update vfp_get_fpsr_from_host() to do this.
Note tha
Implement the FPCR.AH == 1 semantics for vector FMIN/FMAX, by
creating new _ah_ versions of the gvec helpers which invoke the
scalar fmin_ah and fmax_ah helpers on each element.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c |
Implement the FPCR.AH semantics for the SVE FMAX and FMIN
operations that take two vector operands.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 17 +++--
3 files ch
For the x86 and the Arm FEAT_AFP semantics, we need to be able to
tell the target code that the FPU operation has used an input
denormal. Implement this; when it happens we set the new
float_flag_denormal_input_used.
Note that we only set this when an input denormal is actually used by
the operat
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 25 ++
The x86 DE bit in the FPU and MXCSR status is supposed to be set
when an input denormal is consumed. We didn't previously report
this from softfloat, so the x86 code either simply didn't set
the DE bit or else incorrectly wired it up to denormal_flushed,
depending on which register you looked at.
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c | 25 +
target/arm/tcg/vec_helper.c| 10 +
For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the
behaviour of the writeback of the result for most SIMD scalar
operations, so that instead of zeroing the upper part of the result
register it merges the upper elements from one of the input
registers.
Provide new functions write_f
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.
In this commit we
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitive if written
out longhand, we condense th
Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects
flushing of single and double precision denormal inputs to zero for
AArch64 floating point instructions. (For half-precision, the
existing FPCR.FZ16 control remains the only one.)
FPCR.FIZ differs from FPCR.FZ in that if we flush
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use
FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get
the required behaviour changes.
Signed-off-by: Peter Maydell
---
select_fpst() is another function I'm not super happy wit hthe
naming of, because again it shoul
On 23/1/25 02:22, Gustavo Romero wrote:
Add me as the maintainer for the ivshmem-pci.c device, the ivshmem
server, and the ivshmem client tool. Also, adjust remaining parts left
behind after ivshmem PCI device was renamed from ivshmem.c to
ivshmem-pci.c, like header files, Kconfig, docs, and buil
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c |
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/tricore/cpu.h b/targe
On Fri, Jan 24, 2025 at 03:15:25PM +0100, Thomas Huth wrote:
> Some tests have a very long runtime and might run into timeout
> issues e.g. when QEMU has been compiled with --enable-debug.
> Add a decorator for marking them more easily and document the
> corresponding environment variable that is u
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b7367f6d808..2402706c7d9 100644
--- a/include/hw/core/cpu
Let's factor more of the generic "is this directly accessible" check,
independent of the "write" condition out.
Note that the "!mr->rom_device" check in the write case essentially
disallows the memory_region_is_romd() condition again. Further note that
RAM DEVICE regions are also RAM regions, so w
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4
target/arm/tcg/translate-a64.c | 7 ++-
target/arm/tcg/vec_helper.c| 25
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFMLALB, BFMLALT
* SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
so that they get the required behaviour changes.
We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour
rather than a bool is_fp16; existing callsites now select
FPST_FPCR_F
>with an error message indicating DMA mapping failed for the
passthrough >devices.
A correction - the message indicates UEFI failed to find a mapping for
the boot partition ("map: no mapping found"), not that DMA mapping
failed. But earlier EDK debug logs still show PCI host bridge resource
conf
On 2025/01/24 18:39, Christian Schoenebeck wrote:
On Friday, January 24, 2025 6:12:04 AM CET Akihiko Odaki wrote:
coreaudio had unnecessary explicit casts and they had extra whitespaces
around them so remove them.
Signed-off-by: Akihiko Odaki
---
audio/coreaudio.m | 6 +++---
1 file changed
On 2025/01/24 19:01, Christian Schoenebeck wrote:
On Friday, January 24, 2025 6:12:06 AM CET Akihiko Odaki wrote:
coreaudio had names that are not conforming to QEMU codding style.
coreaudioVoiceOut also had some members that are prefixed with redundant
words like "output" or "audio".
Global nam
Hi All,
This is an RFC mainly to seek feedback on the approach used, particularly
the aspect of how to get data from a TCG plugin into a device model.
Two options that we have tried
1. Socket over which the plugin sends data to an external server
(as seen here)
2. Register and manage a plugin f
On 1/25/25 05:13, Alex Williamson wrote:
> On Sat, 25 Jan 2025 03:12:45 +0800
> Tomita Moeko wrote:
>
>> Both enable opregion option (x-igd-opregion) and legacy mode require
>> setting up OpRegion copy for IGD devices. Move x-igd-opregion handler
>> in vfio_realize() to vfio_probe_igd_config_quir
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/vmstate.rs | 61 ++--
1 file changed, 58 insertions(+), 3 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index a262c315da1..9ac699b73b7 100644
--- a/ru
It is a poor match for what the code is doing, anyway.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 39 +++-
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/p
On Thu, 23 Jan 2025 19:23:50 +0100
Mauro Carvalho Chehab wrote:
> Em Thu, 23 Jan 2025 10:29:19 +
> Jonathan Cameron escreveu:
>
> > On Wed, 22 Jan 2025 16:46:20 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > There are two pointers that are needed during error injection:
> > >
> > > 1
Prepare for moving all references to the registers and the FIFO into a
separate struct.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOMMU gets
>disabled
>
>On Fri, Jan 24, 2025 at 12:01 PM Duan, Zhenzhong
> wrote:
>>
>>
>>
>> >-Original Message-
>> >From: Jason Wang
>> >Subject: Re: [PATCH] hw/virtio/vho
Unify the "Interrupt" enum and the "INT_*" constants with a struct
that contains the bits. The "int_level" and "int_enabled" fields
could use a crate such as "bitflags".
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 32 ++
rust/hw
We don't have any functional tests for this machine yet, thus let's
add a test with a MicroPython binary that is available online
(thanks to Joel Stanley for providing it, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg606064.html ).
Signed-off-by: Thomas Huth
---
MAINTAINERS
Generalize the existing optimization of "TSTNE x,sign" and "TSTNE x,-1".
This can be useful for example in the i386 frontend, which will generate
tests of zero-extended registers against 0x.
Ironically, on x86 hosts this is a very slight pessimization in the very
case it's meant to optimiz
Since the cost of gen_update_cc_op() must be paid anyway, it's easier
to place them manually and not rely on spilling that is buried under
multiple levels of function calls. While at it, clarify the circumstances
in which the gen_update_cc_op() is needed, and why it is not for REPxx
SCAS and REPxx
The condition for optimizing repeat instruction is more or less the
opposite of what you imagine: almost always the string instruction
was _not_ optimized and optimizing the loop relied on goto_tb.
This is obviously not great for performance, due to the cost of the
exit-to-main-loop check, but also
Allow using them in the code that translates REP/REPZ, without
forward declarations.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Link: https://lore.kernel.org/r/20241215090613.89588-7-pbonz...@redhat.com
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 80
From: Tao Su
Branch History Injection (BHI) is a CPU side-channel vulnerability, where
an attacker may manipulate branch history before transitioning from user
to supervisor mode or from VMX non-root/guest to root mode. CPUs that set
BHI_NO bit in MSR IA32_ARCH_CAPABILITIES to indicate no additio
Explicitly generate a TSTEQ branch (which is optimized to NE x,0 if possible).
This does not make much sense yet, but later we will add more checks and some
will use a temporary to check on the decremented value of CX/ECX/RCX; it will
be clearer for all checks to share the same logic using TSTEQ(re
This is a common operation that is executed many times in rep
movs or rep stos loops. It can improve performance by several
percentage points.
Signed-off-by: Paolo Bonzini
Link: https://lore.kernel.org/r/20241215090613.89588-13-pbonz...@redhat.com
Signed-off-by: Paolo Bonzini
---
target/i386/t
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