Unify the "Interrupt" enum and the "INT_*" constants with a struct
that contains the bits. The "int_level" and "int_enabled" fields
could use a crate such as "bitflags".
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 32 ++++++++++------------
rust/hw/char/pl011/src/lib.rs | 46 +++++++++++---------------------
2 files changed, 29 insertions(+), 49 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 4fd9bdc8584..eab3cf96f4c 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -191,7 +191,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) ->
ControlFlow<u32, u32> {
self.flags.set_receive_fifo_empty(true);
}
if self.read_count + 1 == self.read_trigger {
- self.int_level &= !registers::INT_RX;
+ self.int_level &= !Interrupt::RX.0;
}
// Update error bits.
self.receive_status_error_clear.set_from_data(c);
@@ -240,7 +240,7 @@ pub(self) fn write(
}
// interrupts always checked
let _ = self.loopback_tx(value);
- self.int_level |= registers::INT_TX;
+ self.int_level |= Interrupt::TX.0;
return true;
}
RSR => {
@@ -364,19 +364,19 @@ fn loopback_mdmctrl(&mut self) -> bool {
// Change interrupts based on updated FR
let mut il = self.int_level;
- il &= !Interrupt::MS;
+ il &= !Interrupt::MS.0;
if self.flags.data_set_ready() {
- il |= Interrupt::DSR as u32;
+ il |= Interrupt::DSR.0;
}
if self.flags.data_carrier_detect() {
- il |= Interrupt::DCD as u32;
+ il |= Interrupt::DCD.0;
}
if self.flags.clear_to_send() {
- il |= Interrupt::CTS as u32;
+ il |= Interrupt::CTS.0;
}
if self.flags.ring_indicator() {
- il |= Interrupt::RI as u32;
+ il |= Interrupt::RI.0;
}
self.int_level = il;
true
@@ -454,7 +454,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool {
}
if self.read_count == self.read_trigger {
- self.int_level |= registers::INT_RX;
+ self.int_level |= Interrupt::RX.0;
return true;
}
false
@@ -641,16 +641,12 @@ pub fn post_load(&self, _version_id: u32) -> Result<(),
()> {
/// Which bits in the interrupt status matter for each outbound IRQ line ?
const IRQMASK: [u32; 6] = [
/* combined IRQ */
- Interrupt::E
- | Interrupt::MS
- | Interrupt::RT as u32
- | Interrupt::TX as u32
- | Interrupt::RX as u32,
- Interrupt::RX as u32,
- Interrupt::TX as u32,
- Interrupt::RT as u32,
- Interrupt::MS,
- Interrupt::E,
+ Interrupt::E.0 | Interrupt::MS.0 | Interrupt::RT.0 | Interrupt::TX.0 |
Interrupt::RX.0,
+ Interrupt::RX.0,
+ Interrupt::TX.0,
+ Interrupt::RT.0,
+ Interrupt::MS.0,
+ Interrupt::E.0,
];
/// # Safety
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 2baacba2306..300c732ae1d 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -100,7 +100,6 @@ enum RegisterOffset {
//Reserved = 0x04C,
}
-#[allow(dead_code)]
mod registers {
//! Device registers exposed as typed structs which are backed by arbitrary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
@@ -521,38 +520,23 @@ fn default() -> Self {
}
/// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
- pub const INT_OE: u32 = 1 << 10;
- pub const INT_BE: u32 = 1 << 9;
- pub const INT_PE: u32 = 1 << 8;
- pub const INT_FE: u32 = 1 << 7;
- pub const INT_RT: u32 = 1 << 6;
- pub const INT_TX: u32 = 1 << 5;
- pub const INT_RX: u32 = 1 << 4;
- pub const INT_DSR: u32 = 1 << 3;
- pub const INT_DCD: u32 = 1 << 2;
- pub const INT_CTS: u32 = 1 << 1;
- pub const INT_RI: u32 = 1 << 0;
- pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
- pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
-
- #[repr(u32)]
- pub enum Interrupt {
- OE = 1 << 10,
- BE = 1 << 9,
- PE = 1 << 8,
- FE = 1 << 7,
- RT = 1 << 6,
- TX = 1 << 5,
- RX = 1 << 4,
- DSR = 1 << 3,
- DCD = 1 << 2,
- CTS = 1 << 1,
- RI = 1 << 0,
- }
+ pub struct Interrupt(pub u32);
impl Interrupt {
- pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
- pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
+ pub const OE: Self = Self(1 << 10);
+ pub const BE: Self = Self(1 << 9);
+ pub const PE: Self = Self(1 << 8);
+ pub const FE: Self = Self(1 << 7);
+ pub const RT: Self = Self(1 << 6);
+ pub const TX: Self = Self(1 << 5);
+ pub const RX: Self = Self(1 << 4);
+ pub const DSR: Self = Self(1 << 3);
+ pub const DCD: Self = Self(1 << 2);
+ pub const CTS: Self = Self(1 << 1);
+ pub const RI: Self = Self(1 << 0);
+
+ pub const E: Self = Self(Self::OE.0 | Self::BE.0 | Self::PE.0 |
Self::FE.0);
+ pub const MS: Self = Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0 |
Self::CTS.0);
}
}
--
2.48.1
