On Mon, Jan 20, 2025 at 03:46:15PM -0500, Peter Xu wrote:
> On Mon, Jan 20, 2025 at 09:22:50PM +1100, Alexey Kardashevskiy wrote:
> > > It is still uncertain how to implement the private MMIO. Our assumption
> > > is the private MMIO would also create a memory region with
> > > guest_memfd-like bac
Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri,
movdir64b)
Also add GDS-NO and RFDS-NO to indicate the related vulnerabilities are
mitig
On Mon, 20 Jan 2025, Bernhard Beschow wrote:
The USDHC emulation allows for running real-world images such as those generated
by Buildroot. Convert the board documentation accordingly instead of running a
Linux kernel with ephemeral storage.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/i
On 1/20/2025 9:11 PM, David Hildenbrand wrote:
> On 14.01.25 02:38, Chenyi Qiang wrote:
>>
>>
>> On 1/13/2025 6:56 PM, David Hildenbrand wrote:
>>> On 13.12.24 08:08, Chenyi Qiang wrote:
As guest_memfd is now managed by guest_memfd_manager with
RamDiscardManager, only block uncoordinat
On 20/01/2025 22.02, Alex Bennée wrote:
This replicates the changes from 92cb8f8bf6 (tests/qtest: remove
clock_steps from virtio tests) as there are no timers in the virtio
code. We still busy wait and timeout though.
Signed-off-by: Alex Bennée
---
tests/qtest/libqos/virtio-pci-modern.c | 6 +
On 21/1/25 08:44, Philippe Mathieu-Daudé wrote:
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ipack/ipack.h | 7
On 1/21/2025 2:33 AM, Peter Xu wrote:
> On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
>> On 20.01.25 18:21, Peter Xu wrote:
>>> On Mon, Jan 20, 2025 at 11:48:39AM +0100, David Hildenbrand wrote:
Sorry, I was traveling end of last week. I wrote a mail on the train and
>>
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus
- TPCI200 is a PCI device providing an IPack bus
- IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/Kconfig| 5 +
hw/char/meson.build
Clarify what is what in Kconfig,
replace qemu_allocate_irqs() by qemu_init_irq().
Philippe Mathieu-Daudé (2):
hw/ipack: Clarify KConfig symbols
hw/ipack: Remove legacy qemu_allocate_irqs() use
include/hw/ipack/ipack.h | 7 ++-
hw/ipack/ipack.c | 7 +++
hw/char/Kco
On Mon, 20 Jan 2025, Bernhard Beschow wrote:
On a real device, the boot ROM contains the very first instructions the CPU
executes. Also, U-Boot calls into the ROM to determine the boot device. While
we're not actually implementing this here, let's create the infrastructure and
add a dummy ROM wit
According to table 1-2 in Intel Architecture Instruction Set Extensions
and Future Features (rev 056) [1], ClearwaterForest has the following new
features which have already been virtualized:
- AVX-VNNI-INT16 CPUID.(EAX=7,ECX=1):EDX[bit 10]
- SHA512 CPUID.(EAX=7,ECX=1):EAX[bit 0]
- SM3
LoongArch ipi can send interrupt to multiple CPUs, interrupt routing
to CPU comes from destination physical cpu id. Here hotplug interface
is added for IPI object, so that parent irq line can be connected, and
routing table can be added for new created cpu.
Here only basic hotplug framework is add
Use hotplug_handler_plug() to nofity ipi object when cold-plug
cpu is created, so that ipi can set and configure irq routing
to new cpu.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt
LoongArch ipi can send intterrupt to multiple CPUs, physical cpu id is
used to route interrupt for CPUs.
With cpu hotplug feature in future, notification for ipi interrupt
controller is required. Here cpu hotplug interface is added on ipi
class, so that gpio irq line is connected to cpu irq line,
Add logic cpu allocation and cpu mapping with cpu hotplug interface.
When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/intc/loongarch_
On Thu, Jan 16, 2025 at 9:04 AM Ani Sinha wrote:
>
> commit 0788a56bd1ae3 ("i386: Make unversioned CPU models be aliases")
> introduced 'default_cpu_version' for PCMachineClass. This created three
> categories of CPU models:
> - Most unversioned CPU models would use version 1 by default.
> - For
The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC0 controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin
The design of the INTC has significant changes in the AST2700 A1. In the
AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
The previous INTC model only supported the AST2700 A0 and was implemented for
the INT
Currently, it does not support the CRYPT command.
Instead, it only sends an interrupt to notify the firmware
that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in
the Crypto Manager Self Test.
Full support for the CRYPT command will be implemented in the fu
Introduce a new ast2700 INTC1 class to support AST2700 INTC1.
Added new register definitions for INTC1, including enable and status registers
for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTC1, supporting six input pins and six
output pins, aligning with the newly defined
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the SCU
registers.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 3 +++
include/hw/misc/aspeed_scu.h
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
According to the AST2700 datasheet, the INTC0 (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC1 (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file changed, 15 insertions(+)
dif
The memory map for AST2700 A1 remains compatible with AST2700 A0.
However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts
now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the AST2700 EVB
machi
Currently, it is difficult to recognize whether these trace events are from
INTC0 or INTC1. To make these trace events more readable, add an ID to the
INTC trace events.
Updated trace events to include the "id" field for better identification.
Updated the "AspeedINTCClass" structure to include an "
The behavior of the INTC set IRQ is almost identical between INTC0 and INTC1.
To reduce duplicated code, introduce the `aspeed_intc_set_irq_handler` function
to handle both INTC0 and INTC1 IRQ behavior.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 56 +++--
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
ast2700a0-evb: Designed for AST2700 A0
ast2700-evb: Designed for AST2700 A1
Test information
1.
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces
Rename "aspeed_intc_read" to "aspeed_2700_intc0_read" and "aspeed_intc_write" to
"aspeed_2700_intc0_write".
Introduce a new memory region operation, "aspeed_2700_intc0_ops", for the
AST2700 INTC0 model.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 20 +++-
1 file changed
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 20
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 18b85081c7..86422cb3be
The behavior of the enable and status registers is almost identical between
INTC0 and INTC1. To reduce duplicated code, adds
"aspeed_2700_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_2700_intc_status_handler" functions to handle status
register write behavior.
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/m
Hi Jason,
On 1/21/25 4:27 AM, Jason Wang wrote:
> On Tue, Jan 21, 2025 at 1:33 AM Eric Auger wrote:
>> When a guest exposed with a vhost device and protected by an
>> intel IOMMU gets rebooted, we sometimes observe a spurious warning:
>>
>> Fail to lookup the translated address e000
>>
>> W
Branch History Injection (BHI) is a CPU side-channel vulnerability, where
an attacker may manipulate branch history before transitioning from user
to supervisor mode or from VMX non-root/guest to root mode. CPUs that set
BHI_NO bit in MSR IA32_ARCH_CAPABILITIES to indicate no additional
mitigation
Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
section "Preferred CPU models for Intel x86 hosts".
Also introduce bhi-no, gds-no and rfds-no in doc.
Suggested-by: Zhao Liu
Signed-off-by: Tao Su
---
docs/system/cpu-models-x86.rst.inc | 42 ++
1
Sorry for resending this series, because it didn't seem to be received by
the mailing list before.
Update SierraForest CPU model to stepping 3 as adding LAM and missing
features.
Clearwater Forest is a new Intel Xeon processor, which will debut in the
market in 2025, add the new CPU model Clearwa
On Tue, Jan 21, 2025 at 04:12:48AM +0100, BALATON Zoltan wrote:
> On Tue, 21 Jan 2025, Tao Su wrote:
> > Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
> > section "Preferred CPU models for Intel x86 hosts".
> >
> > Also introduce bhi-no, gds-no and rfds-no in doc.
> >
> >
On Tue, Jan 21, 2025 at 1:33 AM Eric Auger wrote:
>
> When a guest exposed with a vhost device and protected by an
> intel IOMMU gets rebooted, we sometimes observe a spurious warning:
>
> Fail to lookup the translated address e000
>
> We observe that the IOMMU gets disabled through a write to
On Tue, 21 Jan 2025, Tao Su wrote:
Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
section "Preferred CPU models for Intel x86 hosts".
Also introduce bhi-no, gds-no and rfds-no in doc.
Suggested-by: Zhao Liu
Signed-off-by: Tao Su
---
docs/system/cpu-models-x86.rst.inc |
On 21/1/25 05:39, Nicholas Piggin wrote:
On Mon Jan 20, 2025 at 3:29 PM AEST, Philippe Mathieu-Daudé wrote:
Hi Nick,
Only nitpicking comments...
Hey, no they're good comments actually.
On 17/1/25 18:22, Nicholas Piggin wrote:
Add assertions to ensure a BAR is not mapped twice, and only
pr
The decorators that use a lambda function are currently broken
and do not properly skip the test if the condition is not met.
Using "return skipUnless(lambda: ...)" does not work as expected.
To fix it, rewrite the decorators without lambda, it's simpler
that way anyway.
skipIfMissingImports also
On 1/19/25 23:27, Philippe Mathieu-Daudé wrote:
Constify argument in preparation of constifying CPUClass helpers.
Philippe Mathieu-Daudé (8):
accel/tcg: Constify curr_cflags()
accel/tcg: Constify tcg_cflags_has()
accel/tcg: Constify cpu_in_serial_context()
accel/tcg: Consfity tlb_ind
On Mon Jan 20, 2025 at 3:29 PM AEST, Philippe Mathieu-Daudé wrote:
> Hi Nick,
>
> Only nitpicking comments...
Hey, no they're good comments actually.
>
> On 17/1/25 18:22, Nicholas Piggin wrote:
>> Add assertions to ensure a BAR is not mapped twice, and only
>> previously mapped BARs are unmapped
On Sun Jan 19, 2025 at 8:38 PM AEST, Phil Dennis-Jordan wrote:
> Looks good to me. There is a risk here that the assertion will fail on
> existing code. (Unless you've rigorously audited all callers, which would
> be quite the task.) However, I agree that this would constitute a bug in
> the callin
On Sun Jan 19, 2025 at 7:22 PM AEST, Yan Vugenfirer wrote:
> On Fri, Jan 17, 2025 at 7:05 PM Nicholas Piggin wrote:
>
>> Assert there is no existing irq raised that would lead to a false
>> positive interrupt test.
>>
>> e1000e has to disable interrupt throttling for this test, because
>> it can c
On Mon, 20 Jan 2025, Bernhard Beschow wrote:
Xilinx QEMU implements a TCA6416 device model which may be useful for the
broader QEMU community, so upstream it. In the Xilinx fork, the device model
gets compiled whenever CONFIG_CADENCE is true, so have it maintained by the
"hw/*/cadence_*" maintain
On 2025/01/20 21:23, Alex Bennée wrote:
Akihiko Odaki writes:
On 2025/01/20 7:00, Dmitry Osipenko wrote:
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the
list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching
On Tue, 31 Dec 2024 18:22:39 +
Mark Harmstone wrote:
> Hi all,
>
> I've encountered a really weird bug when trying to run the fstest
> generic/476 in a loop on a microvm VM. The block device is a
> virtio-blk-device, formatted as btrfs.
>
> With acpi=on, it eventually grinds to a halt, and
On 1/20/25 17:52, Zhao Liu wrote:
Sorry I missed this comment before...
Now I have a MemTxAttrs like,
typedef struct MemTxAttrs {
unsigned int secure:1;
unsigned int space:2;
unsigned int user:1;
unsigned int memory:1;
unsigned int requester_id:16;
unsigned int pid
On Mon, Jan 20, 2025 at 11:48:39AM +0100, David Hildenbrand wrote:
> Sorry, I was traveling end of last week. I wrote a mail on the train and
> apparently it was swallowed somehow ...
>
> > > Not sure that's the right place. Isn't it the (cc) machine that controls
> > > the state?
> >
> > KVM doe
On 1/20/25 05:39, Daniel Henrique Barboza wrote:
@@ -1708,10 +1709,25 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
int size,
} else if (probe) {
return false;
} else {
-raise_mmu_exception(env, address, access_type, pmp_violation,
-
Le 19/01/2025 à 05:41, del...@kernel.org a écrit :
From: Helge Deller
Fixes those warnings:
Unsupported host ancillary data: 0/8
Signed-off-by: Helge Deller
v2: (based on feedback by Laurent Vivier)
- add target_in_pktinfo struct and fix copying target_in_addr fields
---
linux-user/sysca
Le 19/01/2025 à 05:41, del...@kernel.org a écrit :
From: Helge Deller
Fixes this warning:
Unknown host IFA type: 11
Signed-off-by: Helge Deller
Reviewed-by: Laurent Vivier
---
linux-user/fd-trans.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/fd-trans.c b/linux-user/fd
On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
> On 20.01.25 18:21, Peter Xu wrote:
> > On Mon, Jan 20, 2025 at 11:48:39AM +0100, David Hildenbrand wrote:
> > > Sorry, I was traveling end of last week. I wrote a mail on the train and
> > > apparently it was swallowed somehow ...
Two trivial comments I spot:
On Fri, Dec 13, 2024 at 03:08:44PM +0800, Chenyi Qiang wrote:
> +struct GuestMemfdManager {
> +Object parent;
> +
> +/* Managed memory region. */
> +MemoryRegion *mr;
> +
> +/*
> + * 1-setting of the bit represents the memory is populated (shared).
Le 19/01/2025 à 05:41, del...@kernel.org a écrit :
From: Helge Deller
Add IP_MULTICAST_IF and share the code with IP_ADD_MEMBERSHIP /
IP_DROP_MEMBERSHIP.
Sharing the code makes sense, because the manpage of ip(7) says:
IP_MULTICAST_IF (since Linux 1.2)
Set the local device for a multi
On 20.01.25 19:33, Peter Xu wrote:
On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
On 20.01.25 18:21, Peter Xu wrote:
On Mon, Jan 20, 2025 at 11:48:39AM +0100, David Hildenbrand wrote:
Sorry, I was traveling end of last week. I wrote a mail on the train and
apparently it was
On Mon, Jan 20, 2025 at 01:57:36PM +0100, David Hildenbrand wrote:
> > I don't want to overload those APIs, I prefer to see a new API that is
> > just about splitting areas. Splitting is a special operation that can
> > fail depending on driver support.
>
> So we'd just always perform a split-befo
Thomas Huth writes:
> QEMU currently crashes when you try to inspect the properties of the
> microvm machine:
>
> $ echo '{ "execute": "qmp_capabilities" }
> { "execute": "qom-list-properties","arguments":
>{ "typename": "microvm-machine"}}' | \
>./qemu-system-x86_64 -qm
On Fri, Dec 06, 2024 at 02:13:57PM -0500, Paolo Bonzini wrote:
> Date: Fri, 6 Dec 2024 14:13:57 -0500
> From: Paolo Bonzini
> Subject: Re: [RFC 06/13] rust: add bindings for memattrs
>
> Il ven 6 dic 2024, 09:42 Peter Maydell ha
> scritto:
>
> > On Fri, 6 Dec 2024 at 14:28, Paolo Bonzini wrote
Hi,
On 20/01/2025 17:38, Zhao Liu wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Hi Peter,
>
>>> /*
>>>* PID (PCI PASID) support: Limited to 8 bits process identifier.
>>
The USDHC emulation allows for running real-world images such as those generated
by Buildroot. Convert the board documentation accordingly instead of running a
Linux kernel with ephemeral storage.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 39 +++
On a real device, the boot ROM contains the very first instructions the CPU
executes. Also, U-Boot calls into the ROM to determine the boot device. While
we're not actually implementing this here, let's create the infrastructure and
add a dummy ROM with all zeros. This allows for implementing a ROM
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one
and a Designware one. There is no device model for the latter, so only add the
ENET one.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 8
hw/arm/
This series adds a new aarch64 machine to QEMU: i.MX 8M Plus EVK [1]. It allows
for running Linux distributions such as Buildroot
(freescale_imx8mpevk_defconfig) and Arch Linux [2] via direct kernel boot.
U-Boot does not work yet. I plan to use this machine myself and I also want to
make it availab
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 11 +++
include/hw/timer/imx_gpt.h | 1 +
hw/arm/fsl-imx8mp.c| 53 ++
hw/timer/imx_gpt.c | 25
hw/arm/Kconf
Linux checks for the PLLs in the PHY to be locked, so implement a model
emulating that.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 2 +
docs/system/arm/imx8mp-evk.rst | 13 +
include/hw/arm/fsl-imx8mp.h | 10
include/hw/pci-host/fsl_imx8m_phy
Xilinx QEMU implements a TCA6416 device model which may be useful for the
broader QEMU community, so upstream it. In the Xilinx fork, the device model
gets compiled whenever CONFIG_CADENCE is true, so have it maintained by the
"hw/*/cadence_*" maintainers.
The code is based on Xilinx QEMU version
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 14 +
hw/arm/fsl-imx8mp.c| 55 ++
3 files changed, 70 insertions(+)
diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp
On Mon, Jan 20, 2025 at 09:25:51PM +0100, David Hildenbrand wrote:
> Yes, calling it "attributes" popped up during RFC discussion: in theory,
> disacard vs. populated and shared vs. private could co-exist (maybe in the
> future with virtio-mem or something similar).
Yes makes sense. The attribute
On Mon, Jan 20, 2025 at 09:22:50PM +1100, Alexey Kardashevskiy wrote:
> > It is still uncertain how to implement the private MMIO. Our assumption
> > is the private MMIO would also create a memory region with
> > guest_memfd-like backend. Its mr->ram is true and should be managed by
> > RamdDiscard
On 1/20/25 19:17, Laurent Vivier wrote:
Le 19/01/2025 à 05:41, del...@kernel.org a écrit :
From: Helge Deller
Add IP_MULTICAST_IF and share the code with IP_ADD_MEMBERSHIP /
IP_DROP_MEMBERSHIP.
Sharing the code makes sense, because the manpage of ip(7) says:
IP_MULTICAST_IF (since Linux 1.2
On 1/20/25 21:42, Helge Deller wrote:
On 1/20/25 19:17, Laurent Vivier wrote:
Le 19/01/2025 à 05:41, del...@kernel.org a écrit :
From: Helge Deller
Add IP_MULTICAST_IF and share the code with IP_ADD_MEMBERSHIP /
IP_DROP_MEMBERSHIP.
Sharing the code makes sense, because the manpage of ip(7)
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might trigger.
This is not the case ATM as shown in [1]. Adding a breakpoint in an
address that deliberatel
Hi,
This second version implements the change Richard suggested in v1, i.e.
do not search for wps twice.
To do that we need to make an assumption that a watchpoint for a 64 bit
address will have size 8, in particular when the user does not set a
watchpoint size. To be consistent we also need to c
Hi Alberto,
You are listed as odd-fix maintainer for IPack.
After your contribution in 2012, I only see maintenance
changes on this code (besides test addition by Andreas in 2014).
Is it still worthwhile maintaining this code? If so, can we
have real world tests? I'm updating legacy APIs and th
On Mon, Jan 20, 2025 at 07:47:18PM +0100, David Hildenbrand wrote:
> "memory_attribute_manager" is weird if it is not memory, but memory-mapped
> I/O ... :)
What you said sounds like a better name already than GuestMemfdManager in
this patch.. :) To me it's ok to call MMIO as part of "memory" too,
On 20.01.25 21:19, Peter Xu wrote:
On Mon, Jan 20, 2025 at 07:47:18PM +0100, David Hildenbrand wrote:
"memory_attribute_manager" is weird if it is not memory, but memory-mapped
I/O ... :)
What you said sounds like a better name already than GuestMemfdManager in
this patch..
Agreed.
:) To m
The value of the UCFR register is respected when echoing characters to the
terminal, but its reset value is reserved. Fix the reset value to the one
documented in the datasheet.
While at it move the related attribute out of the section of unimplemented
registers since its value is actually respect
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of
each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share
the MSI IRQ with the INTx lines, so expose it as a dedicated pin.
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx6.h|
The implementation just allows Linux to determine date and time.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 1 +
hw/rtc/rs5c372.c| 227
hw/rtc/Kconfig | 5 +
hw/rtc/meson.build | 1 +
hw/rtc/trace-events | 4 +
5 files
Fixes quite a few stack traces during the Linux boot process. Also provides the
clocks for devices added later, e.g. enet1.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS| 2 +
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 3 +
include/hw/misc/
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
serial. All other devices of the A53 memory map are represented as
TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
for running Linux without it crashing due to invalid memory accesses.
Signe
Input GPIO values such as a present SD card may get notified before the GPIO
controller itself gets reset. Claring the input values thus loses data. Assuming
that input GPIO events are only fired when the state changes, the input values
shouldn't be reset.
Signed-off-by: Bernhard Beschow
---
hw/
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 8
hw/arm/fsl-imx8mp.c| 26 ++
3 files changed, 35 insertions(+)
diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst
SNVS contains an RTC which allows Linux to deal correctly with time. This is
particularly useful when handling persistent storage which will be done in the
next patch.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 2 ++
hw/arm/fsl-im
Fixes characters to be "echoed" after each keystroke rather than after every
other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY
only after every other keystroke.
Signed-off-by: Bernhard Beschow
---
hw/char/imx_serial.c | 6 +++---
1 file changed, 3 insertions(+), 3 del
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 7 +++
hw/arm/fsl-imx8mp.c| 28
hw/arm/Kconfig | 1 +
4 files changed, 37 insertions(+)
diff --git a/docs/system/arm/imx8mp-e
Split the USB MMIO regions to better keep track of the implemented vs.
unimplemented regions.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 12 +++
hw/arm/fsl-imx8mp.c| 37 --
hw/arm
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 11 +++
hw/arm/fsl-imx8mp.c| 29 +
hw/arm/Kconfig | 2 ++
4 files changed, 43 insertions(+)
diff --git a/docs/system/arm/im
While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference
manual.
Signed-off-by: Bernhard Beschow
---
include/hw/usb/hcd-dwc3.h | 2 +-
hw/usb/hcd-dwc3.c | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx8mp.h | 1 +
hw/arm/fsl-imx8mp.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index 326c4ddf69..e0442665fc 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++
This reverts commit bc02be4508d8753d1f6071b77d10f4661587df6f.
Now we catch attempts to clock_step to the next timer when none are
enabled we can revert the previous attempt to prevent deadlock. As
long as a new target time is given we will move time forward even if
no timers will fire. This is des
Don't both creating a GString to temporarily hold our qtest command.
Instead do a simpler g_strndup and use autofree to clean up
afterwards.
Signed-off-by: Alex Bennée
---
system/qtest.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/system/qtest.c b/sy
This replicates the changes from 92cb8f8bf6 (tests/qtest: remove
clock_steps from virtio tests) as there are no timers in the virtio
code. We still busy wait and timeout though.
Signed-off-by: Alex Bennée
---
tests/qtest/libqos/virtio-pci-modern.c | 6 ++
tests/qtest/libqos/virtio-pci.c
This allows people to run the test locally:
make docker-test-rust@fedora-rust-nightly
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 3 +++
tests/docker/test-rust| 21 +
2 files changed, 24 insertions(+)
create mode 100755 tests/docker/test-rust
It is invalid to call clock_step with an implied time to step forward
as if no timers are running we won't be able to advance.
Signed-off-by: Alex Bennée
---
system/qtest.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/system/qtest.c b/system/qtest.c
index 28b6fac37c.
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