On 1/20/25 05:39, Daniel Henrique Barboza wrote:
@@ -1708,10 +1709,25 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, - first_stage_error, two_stage_lookup, - two_stage_indirect_error); - cpu_loop_exit_restore(cs, retaddr); + CPUWatchpoint *wp = riscv_cpu_addr_has_watchpoint(env, address); + int wp_access = 0; + + if (wp) { + if (access_type == MMU_DATA_LOAD) { + wp_access |= BP_MEM_READ; + } else if (access_type == MMU_DATA_STORE) { + wp_access |= BP_MEM_WRITE; + } + + cpu_check_watchpoint(cs, address, wp->len, + MEMTXATTRS_UNSPECIFIED, + wp_access, retaddr); + } else {
No point in walking the watchpoint list twice: cpu_check_watchpoint(cs, address, size, MEMTXATTRS_UNSPECIFIED, wp_access, retaddr); will return if and only if there is no wp match. Then just fall through to ...
+ raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, two_stage_lookup, + two_stage_indirect_error); + cpu_loop_exit_restore(cs, retaddr);
... this. r~