Philippe Mathieu-Daudé writes:
> mc146818rtc's migration stream is at version 3 since commit
> 56038ef6234 ("RTC: Update the RTC clock only when reading it")
> from 12 years ago, released in QEMU v1.3.0!
> No versioned machines are that old, we can safely remove
> support for older streams and th
On Thu, Jan 16, 2025 at 01:59:40PM +, David Woodhouse wrote:
> (Posting one last time with the header commits split out).
>
> The vmclock device addresses the problem of live migration with
> precision clocks. The tolerances of a hardware counter (e.g. TSC) are
> typically around ±50PPM. A gue
On 1/15/25 15:20, Ilya Leoshkevich wrote:
Currently single-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are not
handled by cpu_restore_state_from_tb(). For x86 this is not a problem,
because x86_restore_state_to_opc() only restores
On Thu, 2025-01-16 at 09:44 -0500, Michael S. Tsirkin wrote:
>
> Reviewed-by: Michael S. Tsirkin
>
> feel free to merge.
Thanks. I've added your R-b to all three (replacing your previous
Acked-by), and will post the PR tomorrow to give others a chance to
comment on the header bits.
smime.p7s
Thanks Thomas,
Looks good to me. I've tested and verified that the problem is fixed.
Tested-by: Jared Rossi
On 1/16/25 6:58 AM, Thomas Huth wrote:
The boot can currently fail after the s390-ccw bios used a network
device since we do not properly shut down the device afterwards, so
that incomi
On Thu, Jan 16, 2025 at 02:37:38PM +0900, Akihiko Odaki wrote:
> On 2025/01/16 1:14, Peter Xu wrote:
> > On Thu, Jan 16, 2025 at 12:52:56AM +0900, Akihiko Odaki wrote:
> > > Functionally, the ordering of container/subregion finalization matters if
> > > some device tries to a container during final
On Tue, 14 Jan 2025 at 19:12, Peter Xu wrote:
>
> On Tue, Jan 14, 2025 at 05:42:57PM +, Peter Maydell wrote:
> > There's at least one test in the arm qtests that will hit this.
> > I suspect that you'll find that most architectures except x86
> > (where we don't have models of complex SoCs and
The versioned 'virt' machines up to 2.12 been marked as deprecated
two releases ago, and are older than 6 years, so according to our
support policy we can remove them. Remove associated dead code.
Since v1:
- Corrected disallow_affinity_adjustment removal (Thomas)
- Do not modify docs/about/remove
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
The VirtMachineClass::no_its field was only used by
virt-2.7 machine, which got removed. Remove it and
simplify virt_instance_init() and virt_acpi_build().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
include/hw/arm/virt.h| 1 -
hw/arm/virt-acpi-build.c | 5 ++---
hw
The VirtMachineClass::disallow_affinity_adjustment
field was only used by virt-2.6 machine, which got
removed. Remove it and simplify virt_cpu_mp_affinity().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/virt.h | 1 -
hw/arm/virt.c | 30 +++---
2 files
The VirtMachineClass::no_pmu field was only used by
virt-2.6 machine, which got removed. Remove it and
simplify machvirt_init().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
include/hw/arm/virt.h | 1 -
hw/arm/virt.c | 4
2 files changed, 5 deletions(-)
diff
The VirtMachineClass::claim_edge_triggered_timers field
was only used by virt-2.8 machine, which got removed.
Remove it and simplify fdt_add_timer_nodes() and build_gtdt().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
include/hw/arm/virt.h| 1 -
hw/arm/virt-acpi-build.
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-D
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
The VirtMachineClass::no_highmem_ecam field was only
used by virt-2.12 machine, which got removed. Remove it
and simplify virt_instance_init().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
include/hw/arm/virt.h | 1 -
hw/arm/virt.c | 2 +-
2 files changed, 1 insert
The VirtMachineClass::smbios_old_sys_ver field was
only used by virt-2.11 machine, which got removed.
Remove it and simplify virt_build_smbios().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
include/hw/arm/virt.h | 1 -
hw/arm/virt.c | 4 +---
2 files changed, 1 in
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c |
On Thu, 2025-01-16 at 06:54 -0800, Richard Henderson wrote:
> On 1/15/25 15:20, Ilya Leoshkevich wrote:
> > Currently single-insn TBs created from I/O memory are not added to
> > region_trees. Therefore, when they generate exceptions, they are
> > not
> > handled by cpu_restore_state_from_tb(). For
Peter Maydell writes:
> On Thu, 16 Jan 2025 at 11:48, Ilya Leoshkevich wrote:
>>
>> On Thu, 2025-01-16 at 11:06 +, Peter Maydell wrote:
>> > The original reported problem here seems to me like it's a
>> > problem with whatever target's frontend code this is.
>> > This is a single instruction
Hi David,
On 16/1/25 14:59, David Woodhouse wrote:
From: David Woodhouse
The vmclock device addresses the problem of live migration with
precision clocks. The tolerances of a hardware counter (e.g. TSC) are
typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that
counter agains
On 16/1/25 16:09, Alex Bennée wrote:
Peter Maydell writes:
On Thu, 16 Jan 2025 at 11:48, Ilya Leoshkevich wrote:
On Thu, 2025-01-16 at 11:06 +, Peter Maydell wrote:
The original reported problem here seems to me like it's a
problem with whatever target's frontend code this is.
This is
On Thu, Jan 16, 2025 at 03:59:34PM +0100, Philippe Mathieu-Daudé wrote:
> The VirtMachineClass::disallow_affinity_adjustment
> field was only used by virt-2.6 machine, which got
> removed. Remove it and simplify virt_cpu_mp_affinity().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw
On 1/16/25 07:06, Ilya Leoshkevich wrote:
On Thu, 2025-01-16 at 06:54 -0800, Richard Henderson wrote:
On 1/15/25 15:20, Ilya Leoshkevich wrote:
Currently single-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are
not
handled by cpu_
On 1/16/25 03:25, Peter Maydell wrote:
In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
raise the Invalid exception regardless of target architecture. (This
was a change affecting hppa, i386, sh4 and tricore.)
16/01/25 14:32, Peter Maydell пишет:
On Thu, 16 Jan 2025 at 11:17, Artem Nasonov wrote:
This assert was found during fuzzing and can be triggered with some qtest
commands.
So instead of assert failure I suggest to handle this error and abort the
command.
This patch is required at least to imp
On 1/15/25 9:49 PM, Atish Patra wrote:
As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.
[1]https://github.com/riscv/riscv-isa-manual/issues/1578
Signed-off-by: Atish Patra
---
Reviewed-by:
The upper bound of pointer position in InputMoveEvent should be 0x7fff,
according to INPUT_EVENT_ABS_MAX.
Signed-off-by: Zhang Boyang
---
qapi/ui.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 460a26b981..7b18662018 100644
--- a/qapi/ui
On 2025/1/16 20:40, Markus Armbruster wrote:
Zhang Boyang writes:
The upper bound of pointer position in InputMoveEvent should be 0x7fff,
according to INPUT_EVENT_ABS_MAX.
Signed-off-by: Zhang Boyang
---
qapi/ui.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/q
Zhang Boyang writes:
> On 2025/1/16 20:40, Markus Armbruster wrote:
>> Zhang Boyang writes:
>>
>>> The upper bound of pointer position in InputMoveEvent should be 0x7fff,
>>> according to INPUT_EVENT_ABS_MAX.
>>>
>>> Signed-off-by: Zhang Boyang
>>> ---
>>> qapi/ui.json | 2 +-
>>> 1 file ch
Gustavo Romero writes:
> Add me as the maintainer for the ivshmem-flat device.
>
> Signed-off-by: Gustavo Romero
> ---
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2101b51217..461f98525b 100644
> --- a/MAINTAINERS
> +++ b/MAINTA
On 1/16/25 03:25, Peter Maydell wrote:
Add a test case which tests some corner case behaviour of
fused-multiply-add on x86:
* 0 * Inf + SNaN should raise Invalid
* 0 * Inf + QNaN shouldh not raise Invalid
* tininess should be detected after rounding
There is also one currently-disabled tes
On Thu, 2025-01-16 at 16:15 +0100, Philippe Mathieu-Daudé wrote:
>
> > --- a/hw/acpi/Kconfig
> > +++ b/hw/acpi/Kconfig
> > @@ -60,6 +60,11 @@ config ACPI_VMGENID
> > default y
> > depends on PC
> >
> > +config ACPI_VMCLOCK
> > + bool
> > + default y
> > + depends on PC
>
On Thu, 2025-01-16 at 12:58 +0100, Thomas Huth wrote:
> The boot can currently fail after the s390-ccw bios used a network
> device since we do not properly shut down the device afterwards, so
> that incoming network packets can corrupt the memory. We have to make
> sure to put the virtio-net devic
On Tue, 7 Jan 2025 14:06:04 +0100
Cédric Le Goater wrote:
> The risk is mainly theoretical since the applied bit mask will keep
> the 'ggms' shift value below 3. Nevertheless, let's use a 64 bit
> integer type and resolve the coverity issue.
>
> Resolves: Coverity CID 1585908
> Fixes: 1e1eac5f3
On 1/8/25 19:26, Helge Deller wrote:
Add some missing fields which may be parsed by userspace
applications.
Signed-off-by: Helge Deller
v2:
- fixed cpu name and type depending on currently active CPU
Queued, thanks
r~
On Thu, 16 Jan 2025 at 15:22, Richard Henderson
wrote:
>
> On 1/16/25 03:25, Peter Maydell wrote:
> > In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
> > pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
> > raise the Invalid exception regardless of target arc
Richard Henderson writes:
> On 1/16/25 07:06, Ilya Leoshkevich wrote:
>> On Thu, 2025-01-16 at 06:54 -0800, Richard Henderson wrote:
>>> On 1/15/25 15:20, Ilya Leoshkevich wrote:
Currently single-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they genera
On Thu, 16 Jan 2025 at 15:40, Alex Bennée wrote:
>
> Richard Henderson writes:
>
> > On 1/16/25 07:06, Ilya Leoshkevich wrote:
> >> On Thu, 2025-01-16 at 06:54 -0800, Richard Henderson wrote:
> >>> On 1/15/25 15:20, Ilya Leoshkevich wrote:
> Currently single-insn TBs created from I/O memory
On Fri, Jan 10, 2025 at 6:09 PM Jonah Palmer wrote:
>
> Implements the GPA->IOVA tree for handling mapping and unmapping for
> guest memory. This, alongside the SVQ IOVA->HVA tree & IOVA-only tree
> implemented in the previous patches, allows us to handle guest and
> host-only memory mapping opera
On 16/1/25 19:05, Philippe Mathieu-Daudé wrote:
On 28/11/23 17:42, Igor Mammedov wrote:
On Mon, 18 Sep 2023 18:02:39 +0200
Philippe Mathieu-Daudé wrote:
While create_vcpu_thread() creates a vCPU thread, its counterpart
is cpu_remove_sync(), which join and destroy the thread.
create_vcpu_thre
On Fri, Jan 10, 2025 at 6:09 PM Jonah Palmer wrote:
>
> Adds the in_xlat_addr & out_xlat_addr hwaddr arrays to the
> VirtQueueElement struct and introduces an optional GPA output parameter
> to dma_memory_map().
>
> These arrays will store a VirtQueueElement's input/output descriptors'
> GPA of th
Steve Sistare writes:
> Add a migration test for cpr-transfer mode. Defer the connection to the
> target monitor, else the test hangs because in cpr-transfer mode QEMU does
> not listen for monitor connections until we send the migrate command to
> source QEMU.
>
> To test -incoming defer, send
On Fri, Jan 10, 2025 at 6:09 PM Jonah Palmer wrote:
>
> Propagates the GPAs (in_xlat_addr/out_xlat_addr) of a VirtQueueElement
> to vhost_svq_translate_addr() to translate to IOVAs via GPA->IOVA tree
> when descriptors are backed by guest memory.
>
> For descriptors backed by guest memory, the tra
On 16/01/2025 16.16, Andrew Jones wrote:
On Thu, Jan 16, 2025 at 03:59:34PM +0100, Philippe Mathieu-Daudé wrote:
The VirtMachineClass::disallow_affinity_adjustment
field was only used by virt-2.6 machine, which got
removed. Remove it and simplify virt_cpu_mp_affinity().
Signed-off-by: Philippe
On 1/16/2025 2:06 PM, Fabiano Rosas wrote:
Steve Sistare writes:
[...]
+/*
+ * The cpr channel must be included in outgoing channels, but not in
+ * migrate-incoming channels.
+ */
if (args->connect_channels) {
+in_channels = qobject_from_json(args->connect_chann
On 16/01/2025 15.59, Philippe Mathieu-Daudé wrote:
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed
On 16/01/2025 15.59, Philippe Mathieu-Daudé wrote:
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed
On 16/01/2025 15.59, Philippe Mathieu-Daudé wrote:
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed
On 16/01/2025 15.59, Philippe Mathieu-Daudé wrote:
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed
On 16/01/2025 15.59, Philippe Mathieu-Daudé wrote:
This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signed
Background
==
Currently the base CXL support for arm platforms is only on Jonathan's
patches[1] which have not yet merged into upstream. Some platform like
SBSA-REF can be more like a real machine, thus the support of cxl could
be meaningful. However, the pxb-cxl-host realization on this pl
This work defines a new cxl host bridge type (TYPE_CXL_HOST). This
could be considered as a prototype of an independent cxl host bridge
which combines gpex features (ecam, mmio windows & irq) and pxb-cxl
features(CHBCR) at meanwhile.
The root bus path of CXL_HOST is "0001:00", that would not affec
On Wed, Jan 15, 2025 at 6:23 PM Igor Mammedov wrote:
>
> Current versions of Windows call _DSM(func=7) regardless
> of whether it is supported or not. It leads to NICs having bogus
> 'PCI Label Id = 0', where none should be set at all.
>
> Also presence of 'PCI Label Id' triggers another Windows b
17.01.2025 02:39, Bernhard Beschow wrote:
Am 15. Januar 2025 12:55:29 UTC schrieb Michael Tokarev :
Is this a qemu-stable material?
Good question. Given that this part of the code has some further issues [1] I'd
rather not alter stable behavior because we might just trade one bug for
anoth
On 1/16/25 13:31, Ilya Leoshkevich wrote:
These similarly named functions serve different purposes; add
docstrings to highlight them.
Suggested-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
---
accel/tcg/cpu-exec.c | 15 ++-
include/tcg/tcg.h| 41 ++
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-2-e83d797ae...@ri
03.12.2024 15:19, Sebastian Ott wrote:
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport :08:01.0: pciehp: Slot(2): Card present
pcieport :08:01.0: pciehp: Slot(2): Link Up
pcieport :08:01.0:
On 2025/01/16 23:33, Peter Xu wrote:
On Thu, Jan 16, 2025 at 02:37:38PM +0900, Akihiko Odaki wrote:
On 2025/01/16 1:14, Peter Xu wrote:
On Thu, Jan 16, 2025 at 12:52:56AM +0900, Akihiko Odaki wrote:
Functionally, the ordering of container/subregion finalization matters if
some device tries to
12.12.2024 15:04, Nicholas Piggin wrote:
The end vector calculation has a bug that results in polling fewer
than required vectors when reading at a non-zero offset in PBA memory.
Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll")
Signed-off-by: Nicholas Piggin
This sm
On 2025/01/17 1:13, BALATON Zoltan wrote:
On Thu, 16 Jan 2025, Peter Maydell wrote:
On Tue, 14 Jan 2025 at 19:12, Peter Xu wrote:
On Tue, Jan 14, 2025 at 05:42:57PM +, Peter Maydell wrote:
There's at least one test in the arm qtests that will hit this.
I suspect that you'll find that mos
15.01.2025 15:53, Igor Mammedov wrote:
Current versions of Windows call _DSM(func=7) regardless
of whether it is supported or not. It leads to NICs having bogus
'PCI Label Id = 0', where none should be set at all.
Also presence of 'PCI Label Id' triggers another Windows bug
on localized versions
On 16/01/2025 18:50, Jonathan Cameron wrote:
> On Thu, 16 Jan 2025 01:18:28 +
> "Zhijian Li (Fujitsu)" wrote:
>
>> On 15/01/2025 21:51, Jonathan Cameron wrote:
>>> On Wed, 15 Jan 2025 15:58:46 +0800
>>> Li Zhijian wrote:
>>>
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specif
Hi David, Nick,
Sorry about not getting back on this for long!
On 2/28/24 2:22 AM, David Gibson wrote:
On Tue, Feb 27, 2024 at 10:21:23PM +1000, Nicholas Piggin wrote:
On Fri Feb 2, 2024 at 12:46 AM AEST, Shivaprasad G Bhat wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property
indi
From: Daniel Henrique Barboza
shcounterenw is defined in RVA22 as:
"For any hpmcounter that is not read-only zero, the corresponding bit in
hcounteren must be writable."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Fran
From: Craig Blackmore
Replace `continus` with `continuous`.
Signed-off-by: Craig Blackmore
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Max Chou
Reviewed-by: Richard Henderson
Message-ID: <20241218142353.1027938-2-craig.blackm...@embecosm.com>
Signed-off-by: Alistair Francis
---
targe
From: Yanfeng Liu
This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.
Note that GDB may display `INVALID` tag for `priv` reg when V bit
is set, this doesn't affect actual access to the bit though.
Signed-off-by: Y
From: Daniel Henrique Barboza
shtvala is described in RVA22 as:
"htval must be written with the faulting guest physical address
in all circumstances permitted by the ISA."
This is the case since commit 3067553993, so claim support for shtvala.
Signed-off-by: Daniel Henrique Barboza
Reviewed-b
From: Daniel Henrique Barboza
shvstvecd is defined in RVA22 as:
"vstvec.MODE must be capable of holding the value 0 (Direct).
When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any
valid four-byte-aligned address."
This is always true for TCG so let's claim support for it.
Signed-
From: Philippe Mathieu-Daudé
Keep kvm_riscv_get_timebase_frequency() prototype aligned with
the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
cpu as argument. Include "target/riscv/cpu-qom.h" which declares
the RISCVCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5:
Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu
into staging (2025-01-16 09:03:43 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/
From: Clément Léger
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-8-cle...@rivosin
From: Daniel Henrique Barboza
When using system mode we can get the CPU traps being taken via the
'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of
logging/showing exceptions to users.
Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users
to check all exc
From: Daniel Henrique Barboza
'sha' is the augmented hypervisor extension, defined in RVA22 as a set of
the following extensions:
- RVH
- Ssstateen
- Shcounterenw (always present)
- Shvstvala (always present)
- Shtvala (always present)
- Shvstvecd (always present)
- Shvsatpa (always present)
- S
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-3-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-4-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.c | 78 ++
From: Daniel Henrique Barboza
shgatpa is defined in RVA22 as:
"For each supported virtual memory scheme SvNN supported in satp, the
corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare
must also be supported."
Claim support for shgatpa since this is always true for TCG.
Signe
From: Kaiwen Xue
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen Xue
Co-developed-by: Atish Patra
Reviewed
From: Clément Léger
Add the switch to enable the Smdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-10-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff
From: Clément Léger
Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-
From: Alexey Baturo
The Zjpm v1.0 spec states there should be Supm and Sspm extensions that
are used in profile specification. Enabling Supm extension enables both
Ssnpm and Smnpm, while Sspm enables only Smnpm.
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Message-ID: <202
From: Kaiwen Xue
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegation-v5-6-e83d797ae...@rivosinc.com>
Signed-o
From: Craig Blackmore
Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes
significantly improves performance.
Co-authored-by: Helene CHELIN
Co-authored-by: Paolo Savini
Co-authored-by: Craig Blackmore
Signed-off-by: Helene CHELIN
Signed-off-by: Paolo Savini
Signed-off-by: Crai
From: Clément Léger
With the current implementation, if we had the following scenario:
- Set bit x in menvcfg
- Set bit x in henvcfg
- Clear bit x in menvcfg
then, the internal variable env->henvcfg would still contain bit x due
to both a wrong menvcfg mask used in write_henvcfg() as well as a
mi
From: Jason Chien
This commit introduces a translation tag to avoid invalidating an entry
that should not be invalidated when IOMMU executes invalidation commands.
E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping
of single stage translation and a mapping of nested translation
From: Atish Patra
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extensio
From: Daniel Henrique Barboza
shvsatpa is defined in RVA22 as:
"All translation modes supported in satp must be supported in vsatp."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241218114026.1652
From: Clément Léger
When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
to VU from HS.
Signed-off-by: Clément Léger
Reviewed-by: Alist
From: Clément Léger
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-6-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Message-ID: <20250106054336.1878291-2-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
targe
From: Kaiwen Xue
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20250110-counter_delegatio
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-8-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of MNP
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-ID: <20250106102346.1100149-6-baturo.ale...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helpe
From: Atish Patra
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.
Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei
Enable the corresponding bits in [m|h]stateen and enable correspond
From: Clément Léger
When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20250110125441.3208676-5-cle...@rivosinc.com>
Signed-
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disabl
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