When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. In particular, this allow to remove one global
&first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4 +++-
2 files changed, 4 in
Propagate the target specific CPU env to the locally
declared bootcpu_supports_isa() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
ind
Propagate the target specific CPU env to the locally
declared bl_gen_nop() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 918ce7795c4..b2be9267516
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_kernel() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 2 +-
hw/mips/bootloader.c | 14 +++---
hw/mips/boston.c | 2 +-
hw/mips/fuloong2e.c |
Propagate the target specific CPU env to the locally
declared bl_gen_load_ulong() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u64() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 9 +
hw/mips/boston.c | 6 +++---
3 files changed, 10 insertions(+),
Propagate the target specific CPU env to the locally
declared bl_gen_dli() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 32811e48cdd..95e
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_to() function.
Include "target/mips/cpu-qom.h" to get MIPSCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 10 +-
2 files changed, 7
Propagate the target specific CPU env to the locally
declared bl_gen_jalr() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 7cf1f01d225..9f35b23653
Propagate the target specific CPU env to the locally
declared bl_gen_dsll() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index b2be9267516..7cf1f01
Pass MaltaState as argument to write_bootloader() so next
commit can propagate it to bl_setup_gt64120_jump_kernel().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index a0
Now than bl_setup_gt64120_jump_kernel() has access to the
MaltaState::cpus[] array, it doesn't need the &first_cpu
global anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/malta.c
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_ulong() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 13 +++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/inclu
Propagate the target specific CPU env to the locally
declared bl_gen_sd() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 30e6422d331..34c3043a5
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u32() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 9 +
hw/mips/malta.c | 18 +-
3 files changed, 16
Propagate the target specific CPU env to the locally
declared bl_gen_sw() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9f35b23653a..30e6422d3
Propagate the target specific CPU env to the locally
declared bl_gen_li() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 34c3043a563..32811e
In boston_mach_init(), resolves the first CPU from the CPS
container using the QOM "cpu[0]" path. Propagate it to
gen_firmware(), removing the &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --
mips_fuloong2e_init() created the vCPU so has its reference,
propagate it to write_bootloader(), removing the &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fulo
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> Pass RISCVCPU to kvm_riscv_get_timebase_frequency(),
> then access the first vCPU via Virt::Array::Hart[]
> rather than the &first_cpu global, which is going to
> be removed as part of the heterogeneous emulation
> effort.
>
> Phili
Propagate MaltaState to bl_setup_gt64120_jump_kernel() so
it can access the MaltaState::cpus[] array.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 589e1a07e47..61b47b0d
main_cpu_reset() is misleadingly named "main": it resets
all vCPUs, with a special case for the first vCPU.
Factor generic_cpu_reset() out of main_cpu_reset(),
allowing to remove one &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 26 +---
From: Bernhard Beschow
In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and
"DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU
currently misses to set the DMA bit which causes the driver to loop forever. Fix
that by setting the DMA bit if enabl
From: Phil Dennis-Jordan
The XHCI specification, section 4.17.1 specifies that "If the
Number of Interrupters (MaxIntrs) field is greater than 1, then
Interrupter Mapping shall be supported." and "If Interrupter
Mapping is not supported, the Interrupter Target field shall be
ignored by the xHC an
Declare TX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3
triboard_machine_init() has access to the single CPU via:
TriBoardMachineState {
TC27XSoCState {
TriCoreCPU cpu;
...
} tc27x_soc;
} ms;
Pass it as argument to tricore_load_kernel() so we can
remove the &first_cpu global use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250108092538.11474-11-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/imx_gpt.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/
From: Helge Deller
Although the hppa_is_pa20() helper is costly due to string comparisons
in object_dynamic_cast(), it is called quite often during memory lookups
and at each start of a block of instruction translations.
Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at
CPU cr
From: Bernhard Beschow
Also print the QOM canonical path when tracing which allows for distinguishing
the many instances a typical i.MX SoC has.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-12-shen...@gm
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_GIE. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now
unused. Not a concern, this array will soon di
Commit 7df6f751176 ("hw/hppa: Split out machine creation")
renamed the 'hppa' machine as 'B160L', but forgot to update
the boot serial test, which ended being skipped.
Cc: qemu-sta...@nongnu.org
Fixes: 7df6f751176 ("hw/hppa: Split out machine creation")
Reported-by: Thomas Huth
Signed-off-by: Phi
On reset:
"All PSW bits except the M bit is reset. The M bit is set."
Commit 1a19da0da44 ("target/hppa: Fill in hppa_cpu_do_interrupt /
hppa_cpu_exec_interrupt") inadvertently set the W bit at RESET,
remove it and set the M bit.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Me
From: Bibo Mao
Code cleanup with directory hw/loongarch/, removing errors from
command "scripts/checkpatch.pl hw/loongarch/*"
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250103064514.2660438-1-maob...@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lo
For a particular physical address within the EthLite MMIO range,
addr_to_port_index() returns which port is accessed.
txbuf_ptr() points to the beginning of a (RAM) TX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Message-Id: <2024111218104
From: Keoseong Park
In ufs_write_attr_value(), the value parameter is handled in the CPU's
endian format but provided in big-endian format by the caller. Thus, it
is converted to the CPU's endian format. The related test code is also
fixed to reflect this change.
Fixes: 7c85332a2b3e ("hw/ufs: mi
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-ID: <20250108092538.11474-14-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/imx6_src.c | 23 +--
hw/misc/trace-even
Factor sdhci_sdma_transfer() out of sdhci_data_transfer().
Re-use it in sdhci_write(), so we don't try to run multi
block transfer for a single block.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Message-Id: <20250109122029.22780-1-phi...@linaro.org>
---
hw/sd/sdhci.c | 2
From: Nikita Shubin
Drop debug printing macros and replace them with according trace
functions.
Signed-off-by: Nikita Shubin
Reviewed-by: Alistair Francis
Message-ID: <20241220111756.16511-1-nikita.shu...@maquefel.me>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/stm32f2xx_usart.c | 49 +
In order to track access to reserved I/O space, use yet
another UnimplementedDevice covering the whole device
memory range. Mapped with lower priority (-1).
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio
From: Gustavo Romero
Add me as the maintainer for the ivshmem-flat device.
Signed-off-by: Gustavo Romero
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250107015639.27648-1-gustavo.rom...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 7 +++
1 file changed, 7 ins
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> When instanciating the machine model, the machine_init()
> implementations usually create the CPUs, so have access
> to its first CPU. Use that rather then the &first_cpu
> global.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewe
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> While the TYPE_ARMV7M object forward its NVIC interrupt lines,
> it is somehow misleading to name it 'nvic'. Add the 'armv7m'
> local variable for clarity, but also keep the 'nvic' variable
> behaving like before when used for wirin
Keep references of all vCPUs created. That allows
to directly access the first vCPU without using the
&first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/m
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_bootp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
index 91b58a71a68..1aab26df69e 100644
--- a/hw/mips/loongson3_bootp.c
+++ b/hw/mips/loongson3_bootp.c
Pass the first vCPU as argument, allowing to remove
another &first_cpu global use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 032ff92383e..0
loongson3_bootp.c doesn't contain any target-specific code
and can be build generically, move it to common_ss[].
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index fcb
Remove one &first_cpu use in hw/mips/loongson3_bootp.c.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_bootp.h | 2 +-
hw/mips/loongson3_bootp.c | 5 ++---
hw/mips/loongson3_virt.c | 1 +
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_bootp.h b/hw/
MemMapEntry is declared in "exec/hwaddr.h", cpu_to_le32() in
"qemu/bswap.h". These headers are indirectly included via "cpu.h".
Include them explicitly in order to avoid when removing "cpu.h":
In file included from ../../hw/mips/loongson3_bootp.c:27:
hw/mips/loongson3_bootp.h:234:14: error: un
Remove one use of the 'current_machine' global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index af1937455b0..a240662016b 100644
--- a/hw/mips/lo
Add quick firmware boot tests (less than 1sec) for the
B160L (32-bit) and C3700 (64-bit) HPPA machines:
$ make check-functional-hppa
...
4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabiosOK 0.22s 2 subtests
passed
Remove the duplicated B160L test in qtest/boot-serial-test.c.
Sugge
Having all its address range mapped by subregions,
s->mmio MemoryRegion effectively became a container.
Rename it as 'container' for clarity.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20241112181044.92193-21-phi...@linaro.org>
---
hw/net/xilinx_ethlite.c
From: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-9-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/imx_serial.c | 58 +---
Follow the assumed QOM type definition style, prefixing with
'TYPE_', and dropping the '_DEVICE' suffix which doesn't add
any value.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Marc-André Lureau
Message-Id: <20250102132624.53443-1-phi...@linaro.org>
---
include/hw/misc/vmcoreinfo.h | 7 +
From: Helge Deller
Rather than manually (and incompletely) resetting vCPUs,
call resettable_reset() which will fully reset the vCPUs.
Remove redundant assignations.
Signed-off-by: Helge Deller
Co-developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <202412311
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> The ARMv7MState object is not simply a CPU, it also
> contains the NVIC, SysTick timer, and various MemoryRegions.
>
> Rename the field as 'armv7m', like other Cortex-M boards.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by
On 11/01/2025 16.07, Rahul Chandra wrote:
Hi,
I am not sure if this is the right list to send this to, but the
https://download.qemu.org/ download server is showing no files available for
listing. Is this unintentional? Or should I be querying the Gitlab tags from
now on for version info?
I
On 12/01/2025 15.34, Michael Tokarev wrote:
09.01.2025 21:52, Fabiano Rosas wrote:
Commit a55ae46683 ("s390: move css_migration_enabled from machine to
css.c") disabled CSS migration globally instead of doing it
per-instance.
CC: Paolo Bonzini
CC: qemu-sta...@nongnu.org #9.1
Fixes: a55ae46683
On 12/01/2025 15.29, Michael Tokarev wrote:
12.01.2025 16:06, Michael Tokarev wrote:
09.01.2025 21:52, Fabiano Rosas wrote:
The parsing for the S390StorageAttributes section is currently leaving
an unconsumed token that is later interpreted by the generic code as
QEMU_VM_EOF, cutting the parsin
v1:
- Support timer for AST2700
- Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write"
callback functions and "aspeed_2700_timer_ops" memory
region operation for AST2700.
Introduce a new ast2700 class to support AST2700.
v2:
Refactor Timer Callbacks for SoC-Sp
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3
The register set have a significant change in AST2700. The TMC00-TMC3C
are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,
TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,
respectively.
Besides, each TIMER has their own control and interrupt status regi
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
TIMER0 – TIMER7 has their own individual control and interrupt status register.
In other words, users are able to
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