On Fri, Jan 10, 2025 at 07:09:09PM +0100, Philippe Mathieu-Daudé wrote:
> triboard_machine_init() has access to the single CPU via:
>
> TriBoardMachineState {
> TC27XSoCState {
> TriCoreCPU cpu;
> ...
> } tc27x_soc;
> } ms;
>
> Pass it as argument to tricore_load_kernel()
On 1/10/25 22:31, Kevin Wolf wrote:
Am 10.01.2025 um 19:45 hat Paolo Bonzini geschrieben:
rustc will check that every reachable #[cfg] matches a list of
the expected config names and values. Recent versions of rustc are
also complaining about #[cfg(test)], even if it is basically a standard
par
03.12.2024 15:49, Shameer Kolothum via wrote:
From Commit 90fa121c6c07 ("migration/multifd: Inline page_size and
page_count") onwards page_size is not part of MutiFD*Params but uses
an inline constant instead.
However, it missed updating an old usage, causing a compile error.
Fixes: 90fa121c6c
09.01.2025 21:52, Fabiano Rosas wrote:
The parsing for the S390StorageAttributes section is currently leaving
an unconsumed token that is later interpreted by the generic code as
QEMU_VM_EOF, cutting the parsing short.
The migration will issue a STATTR_FLAG_DONE between iterations, which
the scr
Am 31. Dezember 2024 11:59:50 UTC schrieb "Volker Rümelin"
:
>Windows only:
>
>The libSDL2 Windows message loop needs the libSDL2 Windows low
>level keyboard hook procedure to grab the left and right Windows
>keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
>
>Since SDL2 2.30.
12.01.2025 16:06, Michael Tokarev wrote:
09.01.2025 21:52, Fabiano Rosas wrote:
The parsing for the S390StorageAttributes section is currently leaving
an unconsumed token that is later interpreted by the generic code as
QEMU_VM_EOF, cutting the parsing short.
The migration will issue a STATTR_F
09.01.2025 21:52, Fabiano Rosas wrote:
Commit a55ae46683 ("s390: move css_migration_enabled from machine to
css.c") disabled CSS migration globally instead of doing it
per-instance.
CC: Paolo Bonzini
CC: qemu-sta...@nongnu.org #9.1
Fixes: a55ae46683 ("s390: move css_migration_enabled from machi
09.01.2025 21:52, Fabiano Rosas wrote:
Commit a55ae46683 ("s390: move css_migration_enabled from machine to
css.c") disabled CSS migration globally instead of doing it
per-instance.
CC: Paolo Bonzini
CC: qemu-sta...@nongnu.org #9.1
Or should it be applied to 9.1 ONLY, but not to 9.2?
/mjt
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 1/8/25 16:14, Michael S. Tsirkin wrote:
> On Mon, Nov 11, 2024 at 01:18:32AM +0300, Dmitry Osipenko wrote:
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>
>> Contarary to Virgl and Venus contexts which mediate high level GFX APIs,
>> DRM native context [1] mediates low
On 1/10/25 15:16, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>
>> Contarary to Virgl and Venus contexts which mediate high level GFX APIs,
>> DRM native context [1] mediates lower level kernel driver UAPI, which
>> refle
On 1/10/25 16:38, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>
>> Contarary to Virgl and Venus contexts which mediate high level GFX APIs,
>> DRM native context [1] mediates lower level kernel driver UAPI, which
>> refle
Am 9. Januar 2025 12:20:29 UTC schrieb "Philippe Mathieu-Daudé"
:
>Factor sdhci_sdma_transfer() out of sdhci_data_transfer().
>Re-use it in sdhci_write(), so we don't try to run multi
>block transfer for a single block.
>
>Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
18.12.2024 12:14, Yuan Liu wrote:
This set of patches is used to fix the bugs of incorrect migration
memory data when compression is enabled.
The method to reproduce this bug is as follows
1. Run "stress-ng --class memory --all 1" in the source side, the
stress-ng tool comes from https://github.
On 1/11/25 13:52, Stefan Weil via wrote:
Each DLL should only be checked once for dependencies, but
several hundred (781 in my test) unneeded checks were done.
Now the script is significantly faster (16 s in my build).
Signed-off-by: Stefan Weil
---
scripts/nsis.py | 10 +-
1 file c
On 1/11/25 14:08, Stefan Weil wrote:
Am 10.01.25 um 21:33 schrieb Pierrick Bouvier:
For now, it was only possible to build plugins using GCC on Windows. However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc_struct attribute, which is not
supported by Clang. A
On 16/2/24 12:02, Philippe Mathieu-Daudé wrote:
Various QDev cleanups extracted to my "enforce QDev API" branch.
- When available, instead of plain QOM, use QDev API equivalent
- Add missing QOM parentship for some obj created with qdev_*new()
- Prefer object_initialize_child() over object_initia
On 11/1/25 22:52, Stefan Weil via wrote:
Each DLL should only be checked once for dependencies, but
several hundred (781 in my test) unneeded checks were done.
Now the script is significantly faster (16 s in my build).
Signed-off-by: Stefan Weil
---
scripts/nsis.py | 10 +-
1 file c
On 10/1/25 19:09, Philippe Mathieu-Daudé wrote:
triboard_machine_init() has access to the single CPU via:
TriBoardMachineState {
TC27XSoCState {
TriCoreCPU cpu;
...
} tc27x_soc;
} ms;
Pass it as argument to tricore_load_kernel() so we can
remove the &first_cpu glob
On 2/1/25 23:53, Jiaxun Yang wrote:
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches
On 11/1/25 16:47, Philippe Mathieu-Daudé wrote:
On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc_st
On 9/1/25 17:20, Bernhard Beschow wrote:
Am 9. Januar 2025 11:40:10 UTC schrieb "Philippe Mathieu-Daudé"
:
Hi Bernhard,
On 8/1/25 10:25, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/sd/sd.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
@@ -87
Dmitry Osipenko writes:
> On 1/12/25 19:14, Alex Bennée wrote:
>> So this goes away with:
>>
>> Linux draig 6.13.0-rc6-ajb-00144-g8c8d54116fa2-dirty #27 SMP
>> PREEMPT_DYNAMIC Fri Jan 10 16:57:29 GMT 2025 x86_64 GNU/Linux
>>
>> So I think is an artefact of the PFN page locking failing. I gue
On 1/12/25 19:14, Alex Bennée wrote:
> So this goes away with:
>
> Linux draig 6.13.0-rc6-ajb-00144-g8c8d54116fa2-dirty #27 SMP
> PREEMPT_DYNAMIC Fri Jan 10 16:57:29 GMT 2025 x86_64 GNU/Linux
>
> So I think is an artefact of the PFN page locking failing. I guess
> native context is more prone
Alex Bennée writes:
> Dmitry Osipenko writes:
>
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>
>> Contarary to Virgl and Venus contexts which mediate high level GFX APIs,
>> DRM native context [1] mediates lower level kernel driver UAPI, which
>> reflects in a less CP
On 14/11/24 21:59, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (19):
hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit
hw/net/xilinx_ethlite: Convert some debug logs to trace events
hw/net/xilinx_ethlite: Remove unuseful debug logs
hw/net/xilinx_ethlite: Upda
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> Keep kvm_riscv_get_timebase_frequency() prototype aligned with
> the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
> cpu as argument. Include "target/riscv/cpu-qom.h" which declares
> the RISCVCPU typedef.
>
> Signed
On Fri, Nov 8, 2024 at 9:03 PM Jason Chien wrote:
>
> This commit introduces a translation tag to avoid invalidating an entry
> that should not be invalidated when IOMMU executes invalidation commands.
> E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping
> of single stage transla
On 1/10/2025 5:50 AM, Xu Yilun wrote:
> On Fri, Jan 10, 2025 at 05:00:22AM +0800, Xu Yilun wrote:
https://github.com/aik/qemu/commit/3663f889883d4aebbeb0e4422f7be5e357e2ee46
but I am not sure if this ever saw the light of the day, did not it?
(ironically I am using it as
On 10/01/2025 21.54, Pierrick Bouvier wrote:
On 1/10/25 08:30, Peter Maydell wrote:
On Thu, 19 Dec 2024 at 18:32, Pierrick Bouvier
wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/virt.rst | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/docs/s
Philippe Mathieu-Daudé writes:
> On 2/1/25 23:53, Jiaxun Yang wrote:
>> b4 [1] is a convenient tool to manage patch series with mailing list
>> working flow.
>> Add a project default config file to match QEMU's mailing list conventions
>> as well as adopting differences on scripting.
>> Examples
On Sat, Jan 11, 2025 at 1:43 PM Akihiko Odaki wrote:
>
> Hi Jason,
>
> Can you check this patch again?
I would like to have this if
1) it would be used by libvirt.
or
2) there's no other way to do this
Thanks
>
> Regards,
> Akihiko Odaki
>
> On 2024/10/22 13:59, Akihiko Odaki wrote:
> > On 2
On Sat, Jan 11, 2025 at 1:11 PM Akihiko Odaki wrote:
>
> Jason, can you pull this series?
Queued.
Thanks
>
> Regards,
> Akihiko Odaki
>
> On 2024/05/08 23:51, Philippe Mathieu-Daudé wrote:
> > ping?
> >
> > On 28/4/24 13:11, Akihiko Odaki wrote:
> >> iov_from_buf(), iov_to_buf(), iov_memset(),
On Fri, Jan 10, 2025 at 6:23 PM Atish Patra wrote:
>
> This series adds the counter delegation extension support. The counter
> delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
> extensions.
>
> 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
>
Zhaoxin currently uses two vendors: "Shanghai" and "Centaurhauls".
It is important to note that the latter now belongs to Zhaoxin. Therefore,
this patch replaces CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1.
The previous CPUID_VENDOR_VIA macro was only defined but never used in
QEMU, making this ch
Zhaoxin CPUs (including vendors "Shanghai" and "Centaurhauls") handle the
CMPLegacy bit similarly to Intel CPUs. Therefore, this commit masks the
CMPLegacy bit in CPUID[0x8001].ECX for Zhaoxin CPUs, just as it is done
for Intel CPUs.
AMD uses the CMPLegacy bit (CPUID[0x8001].ECX.bit1) alon
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
Reviewed-by:
This patch series introduces a new CPU model, Zhaoxin YongFeng, which is
Zhaoxin's latest server processor. Additionally, it consolidates vendor naming
within QEMU: since both " Shanghai " and "Centaurhauls" now belong to
Zhaoxin, the logic has been updated to treat "Centaurhauls" as part of the
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target/i38
13.01.2025 09:39, Thomas Huth wrote:
On 12/01/2025 15.29, Michael Tokarev wrote:
# starting QEMU: exec ./qemu-system-s390x -qtest unix:/tmp/ qtest-1137270.sock -qtest-log /dev/null -chardev socket,path=/tmp/
qtest-1137270.qmp,id=char0 -mon chardev=char0,mode=control -display none - audio none
This patch set introduces a new ARM and macOS HVF specific machine type
called "vmapple". There are also some patches for fixing XHCI spec
compliance issues and adding a workaround to a quirk in the macOS guest's
XHCI driver.
The vmapple machine type approximates the configuration in macOS's own
V
From: Alexander Graf
The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG
emulation) via virtio-pci as well as a special, simple backdoor platform
device.
This patch implements this backdoor platform device to the best of my
understanding. I left out any USB OTG parts; they
QEMU would crash with a failed assertion if the XHCI controller
attempted to raise the interrupt on an interrupter corresponding
to a MSI vector with a higher index than the highest configured
for the device by the guest driver.
This behaviour is correct on the MSI/PCI side: per PCI 3.0 spec,
devi
From: Alexander Graf
VMApple contains an "aes" engine device that it uses to encrypt and
decrypt its nvram. It has trivial hard coded keys it uses for that
purpose.
Add device emulation for this device model.
Signed-off-by: Alexander Graf
Signed-off-by: Phil Dennis-Jordan
Reviewed-by: Akihiko
From: Alexander Graf
We will introduce a number of devices that are specific to the vmapple
target machine. To keep them all tidily together, let's put them into
a single target directory.
Signed-off-by: Alexander Graf
Signed-off-by: Phil Dennis-Jordan
Reviewed-by: Akihiko Odaki
Tested-by: Ak
The XHCI specification, section 4.17.1 specifies that "If the
Number of Interrupters (MaxIntrs) field is greater than 1, then
Interrupter Mapping shall be supported." and "If Interrupter
Mapping is not supported, the Interrupter Target field shall be
ignored by the xHC and all Events targeted at In
From: Philippe Mathieu-Daudé
The TYPE_ARM_GICV3 model doesn't have any particular
dependency on TCG, remove it. Rename the Kconfig selector
ARM_GICV3_TCG -> ARM_GICV3.
Fixes: a8a5546798c ("hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig
selector")
Signed-off-by: Philippe Mathieu-Daudé
From: Alexander Graf
Apple defines a new "vmapple" machine type as part of its proprietary
macOS Virtualization.Framework vmm. This machine type is similar to the
virt one, but with subtle differences in base devices, a few special
vmapple device additions and a vastly different boot chain.
This
From: Alexander Graf
In addition to the ISA and PCI variants of pvpanic, let's add an MMIO
platform device that we can use in embedded arm environments.
Signed-off-by: Alexander Graf
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Phil Dennis-Jordan
Revie
From: Alexander Graf
Apple has its own virtio-blk PCI device ID where it deviates from the
official virtio-pci spec slightly: It puts a new "apple type"
field at a static offset in config space and introduces a new barrier
command.
This patch first creates a mechanism for virtio-blk downstream c
From: Alexander Graf
Instead of device tree or other more standardized means, VMApple passes
platform configuration to the first stage boot loader in a binary encoded
format that resides at a dedicated RAM region in physical address space.
This patch models this configuration space as a qdev dev
This change addresses an edge case that trips up macOS guest drivers
for PCI based XHCI controllers. The guest driver would attempt to
schedule events to XHCI event rings 1 and 2 even when using PCI
pin-based interrupts. Interrupts would therefore be dropped, and events
only handled on timeout.
So
On 11/01/2025 16.47, Philippe Mathieu-Daudé wrote:
On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Message-Id: <20241219153857.57450-6-phi...@linaro.org>
---
hw/misc/vmcoreinfo.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/misc/vmcoreinfo.c b/hw/misc/vmcoreinfo.c
index 145f13a65cf..b0145fa
From: Helge Deller
On reset:
"The CPU begins fetching instructions from address 0xf004.
This address is in PDC space."
Switch vCPUs to 32-bit mode (PSW_W bit is not set) and start
execution at address 0xf004.
Signed-off-by: Helge Deller
Co-developed-by: Philippe Mathieu-Daudé
Si
From: Bernhard Beschow
While at it add a trace event for input GPIO events.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-14-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/gpio/imx_gpio
From: Gabriel Barrantes
Do not propagate error to the upper, directly output the error
to avoid leaks.
Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2714
Signed-off-by: Gabriel Barrantes
Reviewed-by: zhenwei pi
Message-I
virt_machine_init() creates the HARTs vCPUs, then later
virt_machine_done() calls create_fdt_sockets(), so the
latter has access to the first vCPU via:
RISCVVirtState {
RISCVHartArrayState {
RISCVCPU *harts;
...
} soc[VIRT_SOCKETS_MAX];
...
} s;
Directly use that ins
Keep kvm_riscv_get_timebase_frequency() prototype aligned with
the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
cpu as argument. Include "target/riscv/cpu-qom.h" which declares
the RISCVCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/kvm/kvm_riscv.h | 4 +++-
Pass RISCVCPU to kvm_riscv_get_timebase_frequency(),
then access the first vCPU via Virt::Array::Hart[]
rather than the &first_cpu global, which is going to
be removed as part of the heterogeneous emulation
effort.
Philippe Mathieu-Daudé (2):
target/riscv: Have kvm_riscv_get_timebase_frequency()
When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. This will be helpful to remove &first_cpu uses
in few commits.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
Propagate values from machine_init() in order to remove
use of globals such &first_cpu and ¤t_machine.
Philippe Mathieu-Daudé (11):
hw/mips/loongson3_virt: Factor generic_cpu_reset() out
hw/mips/loongson3_virt: Keep reference of vCPUs in machine_init()
hw/mips/loongson3_virt: Have fw_conf_in
Propagate the %cpu_count from the machine file, allowing
to remove the "hw/boards.h" dependency (which is machine
specific) from loongson3_bootp.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_bootp.h | 1 +
hw/mips/loongson3_bootp.c | 11 ++-
hw/mips/loongson3_virt.c | 1
Propagate %processor_id from mips_loongson3_virt_init() where
we have a reference to the first vCPU, so use it instead of
the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/mips/l
'loaderparams' is declared statically. Let fw_conf_init()
access its 'cpu_freq' and 'ram_size' fields.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_
QEMU consumes some device tree blobs, so these have been committed
to the tree in as firmware, along with the device tree source used
to generate them. We know the blobs are "good enough" to have QEMU
boot a system, so we don't really maintain and rebuild the sources.
These blobs were generated wi
Prefer QDev API for QDev objects, avoid the underlying QOM layer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
Message-Id: <20240216110313.17039-8-phi...@linaro.org>
---
target/mips/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
gs/hw-misc-20250112
for you to fetch changes up to 4a0031691596bd81c5949cf4632a6d178f8c2fe5:
Add a b4 configuration file (2025-01-12 23:06:29 +0100)
Misc HW patches queue
- Silent unuseful DTC warnings (Philippe)
- Add few QOM
Prefer QDev API for QDev objects, avoid the underlying QOM layer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
Message-Id: <20240216110313.17039-7-phi...@linaro.org>
---
hw/arm/musicpal.c | 2 +-
hw/sparc/sun4m.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff -
Add TX_GIE to the TX registers MMIO region.
Before TX_GIE1 was accessed as RAM, with no effect.
Now it is accessed as MMIO, also without any effect.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_LEN. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now
unused. Not a concern, this array will soon di
All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20241105130431.22564-8-phi...@linaro.org>
---
hw/intc/xilinx_in
QDev objects created with object_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
Message-Id: <20240216110313.17039-22-phi...@linaro.org>
---
hw/i386/x86-common.c | 1 +
hw/micr
The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/nrf51_soc.h | 2 +-
hw/arm/nrf51_soc.c | 18 +-
When instanciating the machine model, the machine_init()
implementations usually create the CPUs, so have access
to its first CPU. Use that rather then the &first_cpu
global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/b-l475e-iot01a.c| 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/mp
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/stellari
After renaming a pair of fields in NRF51 & Stellaris boards,
remove the &first_cpu global uses in Cortex-M boards.
Rational is &first_cpu is going to be restricted to generic
accelerator code, then be removed. Similarly the global
'cpus_queue' containing target-agnostic CPUs is going to be
restric
On 12/1/25 23:56, Philippe Mathieu-Daudé wrote:
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-of
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> virt_machine_init() creates the HARTs vCPUs, then later
> virt_machine_done() calls create_fdt_sockets(), so the
> latter has access to the first vCPU via:
>
> RISCVVirtState {
> RISCVHartArrayState {
> RISCVCPU *harts;
By changing the way the main QEMU event loop is invoked, I inadvertently
changed the BQL status of exit notifiers: some of them implicitly
assumed they would be called with the BQL held; the BQL is however
not held during the exit(status) call in qemu_default_main().
Instead of attempting to ensur
Declare RX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3
Rather than using I/O registers for RAM buffer, having to
swap endianness back and forth (because the core memory layer
automatically swaps endiannes for us), declare the buffers
as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have
any more I/O regions. Remove the now unused s->regs[] array.
From: Jiaxun Yang
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches using
From: Akihiko Odaki
Commit 8b46d7e2dc8e ("audio: Rename coreaudio extension to use
Objective-C compiler") renamed coreaudio.c to coreaudio.m.
Signed-off-by: Akihiko Odaki
Reviewed-by: Christian Schoenebeck
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250111-maintainers-v1-1-faebe6ef0...
Inline the single use of usb_try_new().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
Message-Id: <20240216110313.17039-10-phi...@linaro.org>
---
include/hw/usb.h | 5 -
hw/usb/bus.c | 2 +-
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/include/hw/usb.h b/i
From: Helge Deller
hppa_cpu_initfn() is called once when a HPPA CPU instance is
initialized, but it sets fields which should be set each time
a CPU resets. Rename it as a reset handler, having it matching
the ResettablePhases::hold() signature, and register it as
ResettableClass handler.
Since o
Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_CTRL. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now
unused. Not a concern, this array will soon
From: Alexander Graf
The documentation says that Nitro Enclaves are based on Firecracker.
AWS has never made that statement.
This patch nudges the wording to instead say it "looks like a
Firecracker microvm".
Signed-off-by: Alexander Graf
Reviewed-by: Dorjoy Chowdhury
Message-ID: <20241211222
From: Akihiko Odaki
The renamed state will not only represent powering state of PFs, but
also represent SR-IOV VF enablement in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250109-reuse-v19-1-f541e82ca...@daynix.com>
Signed-off-by: Philippe Mathie
Inline the 3 uses of usb_new().
Reviewed-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240216110313.17039-11-phi...@linaro.org>
---
include/hw/usb.h| 7 +--
hw/usb/bus.c| 3 ++-
hw/usb/dev-serial.c | 2 +-
3 files changed, 4 insertions(+), 8 deletions(-)
dif
Add TX_CTRL to the TX registers MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3 (prio 0, i/o): ethlite.mdio
81
rxbuf_ptr() points to the beginning of a (RAM) RX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Message-Id: <20241112181044.92193-11-phi...@linaro.org>
---
hw/net/xilinx_ethlite.c | 39 +--
1 file changed
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Fabiano Rosas
Message-ID: <20250108092538.11474-12-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/libqos/arm-imx25-pdk-machine.
From: Marcin Juszkiewicz
I am ending my time with Linaro and do not have plans to continue
working on SBSA Reference Platform anymore.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Leif Lindholm
Message-ID: <20241218123055.11220-1-marcin.juszkiew...@linaro
> -Original Message-
> From: Michael Tokarev
> Sent: Sunday, January 12, 2025 9:13 PM
> To: Liu, Yuan1 ; pet...@redhat.com; faro...@suse.de
> Cc: qemu-devel@nongnu.org; Zeng, Jason ; Wang,
> Yichen ; qemu-stable
> Subject: Re: [PATCH 0/3] bugfixes for migration using compression methods
>
Since create_cpu_without_cps() creates the vCPUs iterating
up to the machine SMP count, it knows the first CPU is
created upon the first iteration, at index #0 :)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --g
- Keep references to vCPUs in CPS and MaltaState,
- Refactor the MIPS Bootloader API to take CPU argument
- Access first CPU propagate from machine_init()
Based-on: <20250112215835.29320-1-phi...@linaro.org>
"hw/mips/loongson3: Remove uses of &first_cpu global"
Philippe Mathieu-Daudé (23):
hw/m
"exec/hwaddr.h" defines:
typedef uint64_t hwaddr;
typedef struct MemMapEntry {
hwaddr base;
hwaddr size;
} MemMapEntry;
Since MemMapEntry::base is always of type uint64_t,
we can directly use bl_gen_write_u64().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 12
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