Signed-off-by: Jiaxun Yang
---
Changes in v3:
- Added PATCH 1 (Richard)
- Link to v2:
https://lore.kernel.org/r/20241224-la-direct-kernel-boot-v2-1-3e8336c54...@flygoat.com
Changes in v2:
- Use extract API for getting bit fields (philmd)
- Mimic arm's load_aarch64_image to handle vmlinuz.efi
- L
Peter Xu writes:
> On Thu, Jan 02, 2025 at 03:58:31PM -0300, Fabiano Rosas wrote:
>> The analyze-migration script was seen failing in s390x in misterious
>> ways. It seems we're reaching the subsection constructor without any
>
> It might be a good idea to add some debug lines indeed. Though are
Convert to use sszie_t to represent size internally to avoid
large image overflowing the size.
Suggested-by: Richard Henderson
Signed-off-by: Jiaxun Yang
---
hw/arm/boot.c | 2 +-
hw/core/loader.c| 4 ++--
include/hw/loader.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
d
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 69 ++
On 2025/1/3 上午6:47, Jiaxun Yang wrote:
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
On Thu, Jan 02, 2025 at 01:36:01PM -0500, Steven Sistare wrote:
> On 12/24/2024 12:18 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:16:47AM -0800, Steve Sistare wrote:
> > > Extend qemu_ram_alloc_from_fd to support resizable ram, and define
> > > qemu_ram_resize_cb to clean up the API.
> > >
Philippe Mathieu-Daudé writes:
> From: Philippe Mathieu-Daudé
>
> AMSAT closed its email service [*] so my personal email
> address is now defunct. Remove it to avoid bouncing emails.
>
> [*]
> https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-2024/
>
> S
On Thu, Jan 02, 2025 at 01:35:01PM -0500, Steven Sistare wrote:
> On 12/24/2024 3:01 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
> > > Add a migration test for cpr-transfer mode. Defer the connection to the
> > > target monitor, else the test hangs becaus
Liu Jaloo writes:
> in qemu branch statble-9.2
>
> $ ./build/qemu-system-arm -M microbit -device
> loader,file=/path/to/heart-hearts-makecode.hex
>
> Segmentation fault
Is it really a hex file?
The code in question is generic_loader_realize() and it falls back
through a series of steps:
Merry Christmas and a Happy New Year!
And kindly ping...
On 13/12/2024 17:36, Li Zhijian wrote:
> This assertion always happens when we sanitize the CXL memory device.
> $ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
>
> It is incorrect to register an MSIX number beyond the device's ca
On 1/2/2025 2:48 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 01:36:01PM -0500, Steven Sistare wrote:
On 12/24/2024 12:18 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:16:47AM -0800, Steve Sistare wrote:
Extend qemu_ram_alloc_from_fd to support resizable ram, and define
qemu_ram_resize_cb to c
On Thu, Jan 02, 2025 at 02:21:13PM -0500, Steven Sistare wrote:
> On 12/24/2024 2:24 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:17:00AM -0800, Steve Sistare wrote:
> > > Add the cpr-transfer migration mode, which allows the user to transfer
> > > a guest to a new QEMU instance on the same h
On Thu, Jan 02, 2025 at 03:58:31PM -0300, Fabiano Rosas wrote:
> The analyze-migration script was seen failing in s390x in misterious
> ways. It seems we're reaching the subsection constructor without any
It might be a good idea to add some debug lines indeed. Though are you sure
it's from parsing
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was introduced. As
a result, a file smaller than offset passes the verification and causes
errors later. Fi
On 1/2/2025 4:14 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 12:34:50PM -0800, Steve Sistare wrote:
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was in
On 12/25/24 03:03, Steven Lee wrote:
This patch introduces a new machine, ast2700-fc, which supports all cores
available in the AST27x0 SoC. In this machine
- The first 4 cores are Cortex-A35 cores.
- CPU 4 is designated as the SSP core.
- CPU 5 is designated as the TSP core.
Test Step:
wge
On 12/25/24 03:03, Steven Lee wrote:
This commit adds a section describing the ast2700-fc multi-SoC machine.
Signed-off-by: Steven Lee
---
docs/system/arm/aspeed.rst | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/as
On 2/1/25 08:34, Thomas Huth wrote:
ASSET_IMAGE needs to be prefixed with "self." ... this bug
apparently went in unnoticed because the test is not run by
default.
Signed-off-by: Thomas Huth
---
tests/functional/test_arm_quanta_gsj.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
R
- Ping
On Fri, Dec 20, 2024 at 7:46 PM Hyman Huang wrote:
> Both the spice server and the qemu (iothread/main loop) context
> can access the cursor field in struct SimpleSpiceDisplay.
>
> Add the mutex lock before accessing cursor in
> qxl_spice_reset_cursor().
>
> Signed-off-by: Hyman Huang
>
Hello Steven,
On 12/25/24 03:03, Steven Lee wrote:
This initial module adds support for the AST27x0 SoC, which features
four Cortex-A35 cores and two Cortex-M4 cores. The patch enables emulation
of the Cortex-M4 cores, laying the groundwork for co-processor support.
These changes introduce imp
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 02/01/2025 10.23, Philippe Mathieu-Daudé wrote:
Add quick firmware boot tests (less than 1sec) for the
B160L (32-bit) and C3700 (64-bit) HPPA machines:
$ make check-functional-hppa
...
4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabiosOK 0.22s 2
subtests passed
Remove the d
On 2/1/25 10:45, Thomas Huth wrote:
On 02/01/2025 10.23, Philippe Mathieu-Daudé wrote:
Add quick firmware boot tests (less than 1sec) for the
B160L (32-bit) and C3700 (64-bit) HPPA machines:
$ make check-functional-hppa
...
4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabios OK 0
For system emulation, qemu_create_machine() is
called from qemu_init().
TCG accelerator always calls tcg_init_machine().
Use it to call qemu_create_machine() on user
emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-all.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion
On 2/1/25 16:12, Philippe Mathieu-Daudé wrote:
To satisfy QOM containers design, implement qemu_create_machine()
for user emulation, creating a 'fake' machine.
Suggested-by: Peter Xu
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/qdev-user-stubs.c | 11 +++
hw/core/meson.build
We need to create a 'fake' machine container for the
QOM API. We already have the system implementation
for qemu_create_machine(). Expose its prototype to
be able to add the user implementation.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 2 ++
system/vl.c| 3 +
From: Peter Xu
Add a helper to fetch a root container (under object_get_root()). Sanity
check on the type of the object.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-12-pet...@redhat.com>
Signed-off-by: Philip
Respin of Peter's v2:
https://lore.kernel.org/qemu-devel/20241121192202.4155849-1-pet...@redhat.com/
'The series is about container_get() and its removal.'
(See v2's cover).
Since v2:
- Create fake machine container for user emulation to avoid:
$ ./qemu-x86_64 /bin/echo foo
qemu-x86_64: ../.
From: Peter Xu
Use machine_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-11-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/gpio.c| 3 +--
hw/core/qdev.c
To satisfy QOM containers design, implement qemu_create_machine()
for user emulation, creating a 'fake' machine.
Suggested-by: Peter Xu
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/qdev-user-stubs.c | 11 +++
hw/core/meson.build | 1 +
2 files changed, 12 insertions(+)
crea
From: Peter Xu
Currently, qdev_get_machine() has a slight misuse on container_get(), as
the helper says "get a container" but in reality the goal is to get the
machine object. It is still a "container" but not strictly.
Note that it _may_ get a container (at "/machine") in our current unit test
From: Peter Xu
Use object_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-13-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
backends/cryptodev.c | 4 ++--
chardev/char.c |
From: Peter Xu
Add a helper to fetch machine containers. Add some sanity check around.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-10-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 10 ++
hw/c
Only qemu_create_machine_containers() uses the
machine_containers[] array, restrict the scope
to this single user.
Signed-off-by: Philippe Mathieu-Daudé
---
system/vl.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/system/vl.c b/system/vl.c
index 933ad83a935.
From: Peter Xu
Now there's no user of container_get(), remove it.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-14-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 11 ---
qom/container.c | 23 -
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c | 235 ++
On 02/01/2025 11.03, Philippe Mathieu-Daudé wrote:
Commit 7df6f751176 ("hw/hppa: Split out machine creation")
renamed the 'hppa' machine as 'B160L', but forgot to update
the boot serial test, which ended being skipped.
Cc: qemu-sta...@nongnu.org
Fixes: 7df6f751176 ("hw/hppa: Split out machine cr
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 6035ec2c61..f0df03c43e 1
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
From: Philippe Mathieu-Daudé
AMSAT closed its email service [*] so my personal email
address is now defunct. Remove it to avoid bouncing emails.
[*]
https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-2024/
Signed-off-by: Philippe Mathieu-Daudé
Signed-off
Code cleanup with directory hw/loongarch/, removing errors from
command "scripts/checkpatch.pl hw/loongarch/*"
Signed-off-by: Bibo Mao
---
hw/loongarch/acpi-build.c | 3 ++-
hw/loongarch/boot.c | 4 ++--
hw/loongarch/virt.c | 10 ++
3 files changed, 10 insertions(+), 7 dele
On 02/01/2025 06.49, Liu Jaloo wrote:
in qemu branch statble-9.2
$ ./build/qemu-system-arm -M microbit -device loader,file=/path/to/
heart-hearts-makecode.hex
Segmentation fault
That's a bug of course - a segfault should never happen...
...
according to docs/system/arm/nrf.rst
Now that we've got a find_free_port() function in the functional
test framework, we can convert the migration test, too.
While the original avocado test was only meant to run on aarch64,
ppc64 and x86, we can turn this into a more generic test by now
and run it on all architectures that have a mach
Valgrind complains about the probe_o_direct_support() function reading
from an uninitialized buffer. For probing O_DIRECT support we don't
actually need to write to the file, just make sure the pwrite call
doesn't reject the write. Still, write zeroes to the buffer to
suppress the warning.
Reviewe
On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
> Add a migration test for cpr-transfer mode. Defer the connection to the
> target monitor, else the test hangs because in cpr-transfer mode QEMU does
> not listen for monitor connections until we send the migrate command to
> source Q
On Thu, Jan 02, 2025 at 01:35:22PM -0500, Steven Sistare wrote:
> > > > +MigrateCommon args = {
> > > > +.start.opts_source = opts,
> > > > +.start.opts_target = opts_target,
> > > > +.start.defer_target_connect = true,
> >
> > One more comment: maybe we can even drop d
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches using:
scripts/checkpatch.pl -q --t
ASSET_IMAGE needs to be prefixed with "self." ... this bug
apparently went in unnoticed because the test is not run by
default.
Message-ID: <20250102073403.36328-1-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
tests/functional/test_arm_quanta_gsj.py | 2 +-
On 20/12/2024 17.28, Peter Xu wrote:
On Thu, Dec 19, 2024 at 03:53:22PM -0300, Fabiano Rosas wrote:
Stefan Hajnoczi writes:
Hi Fabiano,
Please take a look at this CI failure:
MALLOC_PERTURB_=61 QTEST_QEMU_BINARY=./qemu-system-s390x
UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summa
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
Hi Daniel, Peter,
On 2/12/24 17:54, Daniel P. Berrangé wrote:
On Mon, Dec 02, 2024 at 04:41:48PM +, Peter Maydell wrote:
On Tue, 19 Nov 2024 at 11:29, Daniel P. Berrangé wrote:
We expect all new code to be contributed with the "GPL-2.0-or-later"
license tag. Divergance is permitted if th
Hi Peter,
On 29/7/24 17:51, Peter Maydell wrote:
On Fri, 19 Jul 2024 at 19:11, Philippe Mathieu-Daudé wrote:
Do not receive characters when UART or receiver are disabled.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/char/pl011.c | 7 +--
1 file changed
Ivan Klokov writes:
> These patches add functionality for unit testing RISC-V-specific registers.
> The first patch adds a Qtest backend, and the second implements a simple test.
>
> ---
> v8:
>- Delete RFC label.
> v7:
>- Fix build errors, add Reviewed-by, Acked-by.
> ---
>
> Ivan Klokov
On 02/01/2025 16.25, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
AMSAT closed its email service [*] so my personal email
address is now defunct. Remove it to avoid bouncing emails.
[*]
https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-202
On 1/2/2025 2:57 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 02:21:13PM -0500, Steven Sistare wrote:
On 12/24/2024 2:24 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:00AM -0800, Steve Sistare wrote:
Add the cpr-transfer migration mode, which allows the user to transfer
a guest to a new QEM
Respin of Peter's v2:
https://lore.kernel.org/qemu-devel/20241121192202.4155849-1-pet...@redhat.com/
'The series is about container_get() and its removal.'
(See v2's cover).
Since v3:
- Implement qdev_create_fake_machine() in single patch (peterx)
Since v2:
- Create fake machine container for us
Hi Gustavo,
On 31/12/24 21:22, Philippe Mathieu-Daudé wrote:
From: Gustavo Romero
Add a new device, ivshmem-flat, which is similar to the ivshmem PCI but
does not require a PCI bus. It's meant to be used on machines like those
with Cortex-M MCUs, which usually lack a PCI/PCIe bus, e.g. lm3s696
From: Peter Xu
Currently, qdev_get_machine() has a slight misuse on container_get(), as
the helper says "get a container" but in reality the goal is to get the
machine object. It is still a "container" but not strictly.
Note that it _may_ get a container (at "/machine") in our current unit test
From: Peter Xu
Now there's no user of container_get(), remove it.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-14-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 11 ---
qom/container.c | 23 -
From: Peter Xu
Add a helper to fetch machine containers. Add some sanity check around.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-10-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 10 ++
hw/c
From: Peter Xu
Use object_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-13-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
backends/cryptodev.c | 4 ++--
chardev/char.c |
From: Peter Xu
Add a helper to fetch a root container (under object_get_root()). Sanity
check on the type of the object.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-12-pet...@redhat.com>
Signed-off-by: Philip
Only qemu_create_machine_containers() uses the
machine_containers[] array, restrict the scope
to this single user.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Peter Xu
---
system/vl.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/system/vl.c b/system/v
When a QDev instance is realized, qdev_get_machine() ends up called.
In the next commit, qdev_get_machine() will require a "machine"
container to be always present. To satisfy this QOM containers design,
Implement qdev_create_fake_machine() which creates a fake "machine"
container for user emulatio
On 2/1/25 18:29, Peter Xu wrote:
On Thu, Jan 02, 2025 at 04:12:34PM +0100, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
qdev: Expose qemu_create_machine()
qdev: Implement qemu_create_machine() for user emulation
qdev: Call qemu_create_machine() on user emulation
qdev: In
On Thu, Jan 02, 2025 at 12:34:50PM -0800, Steve Sistare wrote:
> qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
> it uses the existing space and verifies it is large enough, but the
> verification was broken when the offset parameter was introduced. As
> a result, a file s
From: Peter Xu
Use machine_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-11-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/gpio.c| 3 +--
hw/core/qdev.c
On Thu, Jan 02, 2025 at 10:17:53PM +0100, Philippe Mathieu-Daudé wrote:
> When a QDev instance is realized, qdev_get_machine() ends up called.
> In the next commit, qdev_get_machine() will require a "machine"
> container to be always present. To satisfy this QOM containers design,
> Implement qdev_
The dirty_limit test does two migrations in a row and is leaking the
first 'to' instance. Do proper cleanup.
Reviewed-by: Peter Xu
Message-Id: <20241209204427.17763-2-faro...@suse.de>
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration/precopy-tests.c | 5 +
1 file changed, 5 insertions(
From: Ani Sinha
Remove code that is already compiled out. This prevents confusion.
CC: qemu-triv...@nongnu.org
Signed-off-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20250101081555.1050736-1-anisi...@redhat.com>
Signed-off-by: Fabiano Rosas
---
tests/qtest/fw_cfg-test.c |
From: Shameer Kolothum
Removes accidental inclusion of unrelated functions within CONFIG_UADK
as this causes compile errors like:
error: redefinition of ‘migrate_hook_start_xbzrle’
Fixes: 932f74f3fe6e ("tests/qtest/migration: Split compression tests from
migration-test.c")
Signed-off-by: Shame
From: Peter Xu
Coverity complained about them. These two variables are never used now
after commit 832c732c5d ("migration-test: Create arch_opts"), and/or commit
34cc54fb35 ("tests/qtest/migration-test: Use custom asm bios for ppc64").
Resolves: Coverity CID 1568379
Resolves: Coverity CID 156838
The following changes since commit 8b70d7f2071e2db51b1910502bfb7f84ebf926be:
Merge tag 'hw-misc-20241231' of https://github.com/philmd/qemu into staging
(2025-01-01 15:17:08 -0500)
are available in the Git repository at:
https://gitlab.com/farosas/qemu.git tags/qtest-20250102-pu
The dump_aml_files() function calls load_expected_aml() to allocate
the tables but never frees it. Add the missing call to
free_test_data().
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20241209204427.17763-4-faro...@suse.de>
Signed-off-by: Fabiano Rosas
---
tests/qtest/bios-tables-test.c |
Postcopy tests have been inadvertently disabled since commit
124a3c58b8 ("tests/qtest/migration: Move ufd_version_check to
utils"). That commit moved the ufd_version_check() function to another
file but failed to make sense of the ifdefs and includes:
The include was incorrectly dropped. It is ne
Valgrind complains about:
Use of uninitialised value of size 8
&
Conditional jump or move depends on uninitialised value(s)
both at:
at 0x5265931: _itoa_word (_itoa.c:180)
by 0x527EEC7: __vfprintf_internal (vfprintf-internal.c:1687)
by 0x528C8B0: __vsprintf_internal (iovsprintf.c:96)
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 2 summary:
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
*** BLURB HERE ***
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
- corrected commit message format
- combine DAWR(0/1) handling into a single function
- add DAWR1 & DAWRX1 to init_proc_PO
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
Signed-off-by: dan
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was introduced. As
a result, a file smaller than offset passes the verification and causes
errors later. Fi
Hi,
First of all Happy New Year :)
On Mon, Dec 30, 2024 at 12:41 PM Marc-André Lureau
wrote:
[cut]
> > +
> > +for (i = 0; i < d->be_cnt; i++) {
> > +written = d->be_written[i] - d->be_min_written;
> > +if (written) {
> > +/* Written in the previous call so take
On 1/2/25 02:03, Philippe Mathieu-Daudé wrote:
Since v5:
- Correct boot-serial-test machine name for stable (th_huth)
Philippe Mathieu-Daudé (2):
tests/qtest/boot-serial-test: Correct HPPA machine name
tests: Add functional tests for HPPA machines
MAINTAINERS |
On Wed, 25 Dec 2024 11:03:42 +0800
Zhao Liu wrote:
> > > About smp-cache
> > > ===
> > >
> > > The API design has been discussed heavily in [3].
> > >
> > > Now, smp-cache is implemented as a array integrated in -machine.
> > > Though -machine currently can't support JSON format, th
On 1/2/25 02:58, Philippe Mathieu-Daudé wrote:
This series split a patch [*] which was previously posted
too compact in multiple trivial steps. The last patch
initializes the PL011 Control register, enabling the
UART and its transmit channel, before using it to send
the 'T' character in the boot-
Since v5:
- Correct boot-serial-test machine name for stable (th_huth)
Philippe Mathieu-Daudé (2):
tests/qtest/boot-serial-test: Correct HPPA machine name
tests: Add functional tests for HPPA machines
MAINTAINERS | 1 +
tests/qtest/boot-serial-test.c| 2 --
Add quick firmware boot tests (less than 1sec) for the
B160L (32-bit) and C3700 (64-bit) HPPA machines:
$ make check-functional-hppa
...
4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabiosOK 0.22s 2 subtests
passed
Remove the duplicated B160L test in qtest/boot-serial-test.c.
Sugge
Commit 7df6f751176 ("hw/hppa: Split out machine creation")
renamed the 'hppa' machine as 'B160L', but forgot to update
the boot serial test, which ended being skipped.
Cc: qemu-sta...@nongnu.org
Fixes: 7df6f751176 ("hw/hppa: Split out machine creation")
Reported-by: Thomas Huth
Signed-off-by: Phi
Allow the backend to make constraint choices based on
the entire TCGOp. The type and vector element fields
within the main TCGOp structure are valid to inspect,
as well as any constant operands, e.g. a MemOp.
We lose the ability to assert the correctness of the map
from TCGOpcode to constraint se
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 12 --
tcg/optimize.c | 6 ++---
tcg/tcg-op.c | 38
tcg/tcg.c| 29 ++--
tcg/tci.c
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-has.h | 22 --
tcg/s390x/tcg-target.c.inc | 37 +
2 files changed,
For TCI, we're losing type information from the interpreter.
Limit the opcodes to the host register size; on 64-bit host
it's just as easy to reconstruct 64-bit operands for normal add/sub.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 6 +--
tcg/tci/tcg-target-has.h |
Based-on: 20250102180654.1420056-1-richard.hender...@linaro.org
("[PATCH 00/73] tcg: Merge *_i32 and *_i64 opcodes")
While riscv does not yet have a completely general extract,
the Zbs extension added a single-bit extract.
Tested on cfarm95, a Banana Pi BPI-F3.
r~
Richard Henderson (2):
uti
Test each vector type, not just lumping them all together.
Add tests for I32 (always true) and I64 (64-bit hosts).
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 66 ---
1 file changed, 43 insertions(+), 23 deletions(-)
diff --git a/tcg/tcg.
Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint
arrays based on those. Only afterward process the TCGOpcodes and
share those TCGArgConstraint arrays.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 +-
tcg/tcg.c | 273 +++
We already have these assertions during opcode creation.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index b7c58671f0..dbffbeff5f 100644
Use the fully general extract opcodes instead.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 10 -
tcg/aarch64/tcg-target-has.h | 11 -
tcg/arm/tcg-target-has.h | 6 -
tcg/i386/tcg-target-has.h| 11 -
tcg/loongarch64/tcg-target-has.h | 16 --
t
This is and, or, xor, andc, orc, eqv, nand, nor, not.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 27 ++--
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate-sve.c | 2 +-
target/sh4/translate.c | 14 +-
target/tricore/translate.c
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