[PATCH 2/2] improve precision of throttle_pct

Using the current algorithm, there are issues with precision not being handled correctly during division operations. (Even though double type casting is used in the function, it does not seem to have any effect.) Refer to the results of the test program from [1]. When there is a large discrepancy b

[PATCH 0/2] some optimize in dirtylimit_throttle_pct

From: fuqiang Patch 1 optimizes the trace event dirtylimit_throttle_pct, making it print the throttle percentage and throttle adjustment more reasonably. Patch 2 improves the precision of the throttle percentage, allowing it to decrease more quickly during linear adjustments. fuqiang wang (2):

[PATCH 1/2] optimize the dirtylimit_throttle_pct trace event

The current dirtylimit_throttle_pct trace event is triggered when the throttle time is adjusted linearly. Modify the trace event so that it can record non-linear adjustments. Additionally, since the throttle time might be adjusted again at the end of the dirtylimit_set_throttle function, move the t

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/31 09:18, bibo mao wrote: On 2024/12/31 上午9:09, bibo mao wrote: On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons. On 2024/12/19 17:57, bibo mao wrote: Hi Miao, Thanks for doing this. It is

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/31 上午10:08, Miao Hao wrote: On 2024/12/31 09:18, bibo mao wrote: On 2024/12/31 上午9:09, bibo mao wrote: On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons. On 2024/12/19 17:57, bibo mao wrote

Re: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

On Thu, Dec 26, 2024 at 8:42 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote: > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and '

[PATCH v11 6/6] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of MNP

[PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disabl

[PATCH v11 0/6] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741) * mn

[PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to

[PATCH v11 2/6] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 7 target/riscv/cpu_bits.h | 11 ++ target

[PATCH v11 4/6] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu

[PATCH v11 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/

[PATCH v3 3/5] target/hppa: Only set PSW 'M' bit on reset

On reset: "All PSW bits except the M bit is reset. The M bit is set." Commit 1a19da0da44 ("target/hppa: Fill in hppa_cpu_do_interrupt / hppa_cpu_exec_interrupt") inadvertently set the W bit at RESET, remove it and set the M bit. Signed-off-by: Philippe Mathieu-Daudé --- Only tested using QEMU

[PATCH v3 0/5] hppa CPU reset and speedup

Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1-del...@kernel.org/ "Add CPU reset function and speed up runtime and translation." - Remove hppa_cpu_init() - Reset PSW using M bit (untested) Helge, could we add a functional test booting Linux? Helge Deller (4): target/hppa:

[PATCH v3 2/5] hw/hppa: Reset vCPUs calling resettable_reset()

From: Helge Deller Rather than manually (and incompletely) resetting vCPUs, call resettable_reset() which will fully reset the vCPUs. Remove redundant assignations. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- hw/hppa/machine.c

[PATCH v3 4/5] target/hppa: Set PC on vCPU reset

From: Helge Deller On reset: "The CPU begins fetching instructions from address 0xf004. This address is in PDC space." Switch vCPUs to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Si

[PATCH v3 1/5] target/hppa: Convert hppa_cpu_init() to ResetHold handler

From: Helge Deller hppa_cpu_initfn() is called once when a HPPA CPU instance is initialized, but it sets fields which should be set each time a CPU resets. Rename it as a reset handler, having it matching the ResettablePhases::hold() signature, and register it as ResettableClass handler. Since o

[PATCH v3 5/5] target/hppa: Speed up hppa_is_pa20()

From: Helge Deller Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at CPU cr

Re: [PATCH 0/5] hw: Mark architecture specific devices with specific endianness

On 6/11/24 19:46, Philippe Mathieu-Daudé wrote: When a device is only built for an architecture built for a particular endianness, we can simplify the device to not use the "target native endianness" definition and directly use the proper target endianness. Philippe Mathieu-Daudé (5): hw/i386

Re: [PATCH 1/2] hw/s390x: Declare loadparm as char[LOADPARM_LEN]

ping for this single cleanup patch? On 20/11/24 09:52, Philippe Mathieu-Daudé wrote: "hw/s390x/ipl/qipl.h" defines loadparm[] length as LOADPARM_LEN, use that instead of the magic '8' value. Use a char type for char buffer. Signed-off-by: Philippe Mathieu-Daudé --- hw/s390x/ccw-device.h

Re: [PATCH-for-9.2] hw/avr/arduino: Check for CPU types in machine_run_board_init()

Hi Peter, On 18/11/24 14:07, Peter Maydell wrote: On Mon, 18 Nov 2024 at 13:02, Philippe Mathieu-Daudé wrote: Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. This allows reporting an error for invalid

[PATCH 2/3] target/cpus: Remove pointless re-assignment of CPUState::exception_index

The CPUState::exception_index field is always re-initialized by the parent CPU ResetHold() handler in cpu_common_reset_hold(), no need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 1 - target/loongarch/cpu.c | 1 - target/openrisc/c

[PATCH 0/3] cpus: Avoid re-initializing fields cleared in cpu_common_reset_hold()

Having this call tree: cpu_reset() -> device_cold_reset() -> DeviceClass::reset() -> target_cpu_reset() -> ResettablePhases::hold() -> CPUClass::phases::hold() -> cpu_common_reset_hold() If we call cpu_reset(), common fields will be reset

[PATCH 3/3] target/cpus: Remove pointless re-assignment of CPUState::halted

The CPUState::halted field is always re-initialized in cpu_common_reset_hold(), itself called by cpu_reset(). No need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/mips_cpc.c| 1 - hw/ppc/e500.c | 1 - target/arm/arm-powerctl.c |

[PATCH 1/3] accel/tcg: Remove pointless initialization of cflags_next_tb

cflags_next_tb is always re-initialized in the CPU Reset() handler in cpu_common_reset_hold(), no need to initialize it in cpu_common_initfn(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-13-phi...@linaro.org> --- hw/core/cpu-common.c |

Re: [PULL 16/49] clock: treat outputs and inputs the same in NamedClockList

Hi Paolo, The commit description is missing... See: https://lore.kernel.org/qemu-devel/20241129180326.722436-3-pbonz...@redhat.com/ >> Leave around a reference not just for inputs but also for outputs. >> This is a better choice because in principle the monitor could walk >> the NamedClockList a

Re: [PATCH v16 00/14] macOS PV Graphics and new vmapple machine type

On Mon, 30 Dec 2024 at 19:55, Philippe Mathieu-Daudé wrote: > Cc'ing Joelle (FYI https://github.com/utmapp/UTM/issues/3491) > > On 23/12/24 23:16, Phil Dennis-Jordan wrote: > > This patch set introduces a new ARM and macOS HVF specific machine type > > called "vmapple", as well as a family of dis

Re: [PATCH v3 0/5] hppa CPU reset and speedup

Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1-del...@kernel.org/ "Add CPU reset function and speed up runtime and translation." - Remove hppa_cpu_init() Thanks for picking up my patches and integrating them p

Re: [PATCH v16 01/14] ui & main loop: Redesign of system-specific main thread event handling

Hi, On 23/12/24 23:16, Phil Dennis-Jordan wrote: macOS's Cocoa event handling must be done on the initial (main) thread of the process. Furthermore, if library or application code uses libdispatch, the main dispatch queue must be handling events on the main thread as well. So far, this has affe

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and translation." - Remove hppa_cpu_init() Thanks for p

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/31 10:23, bibo mao wrote: On 2024/12/31 上午10:08, Miao Hao wrote: On 2024/12/31 09:18, bibo mao wrote: On 2024/12/31 上午9:09, bibo mao wrote: On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons

Re: [PATCH 1/1] docs/nitro-enclave: Clarify Enclave and Firecracker relationship

On Thu, Dec 12, 2024 at 8:14 PM Dorjoy Chowdhury wrote: > > On Thu, Dec 12, 2024 at 4:25 AM Alexander Graf wrote: > > > > The documentation says that Nitro Enclaves are based on Firecracker. AWS > > has never made that statement. > > > > This patch nudges the wording to instead say it "looks like

Re: [PATCH v16 01/14] ui & main loop: Redesign of system-specific main thread event handling

On 23/12/24 23:16, Phil Dennis-Jordan wrote: macOS's Cocoa event handling must be done on the initial (main) thread of the process. Furthermore, if library or application code uses libdispatch, the main dispatch queue must be handling events on the main thread as well. So far, this has affected

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and translation." - Remove hppa_cpu_init() Thanks for p

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 30/12/24 21:39, Philippe Mathieu-Daudé wrote: On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and tran

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 12/30/24 21:36, Philippe Mathieu-Daudé wrote: On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and transl

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and translation." - Remove hppa_cpu_init() Thanks for p

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 30/12/24 21:41, Philippe Mathieu-Daudé wrote: On 30/12/24 21:39, Philippe Mathieu-Daudé wrote: On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Ad

Ping (2): [PATCH v3] net/vmnet: Pad short Ethernet frames

On Sat, Nov 2, 2024 at 1:56 PM William Hooper wrote: > At least on macOS 12.7.2, vmnet doesn't pad Ethernet frames, such as the > host's ARP replies, to the minimum size (60 bytes before the frame check > sequence) defined in IEEE Std 802.3-2022, so guests' Ethernet device > drivers may drop them

Re: [PATCH v3 0/5] hppa CPU reset and speedup

On 12/30/24 21:47, Philippe Mathieu-Daudé wrote: On 30/12/24 21:24, Helge Deller wrote: Hi Philippe, On 12/30/24 16:25, Philippe Mathieu-Daudé wrote: Respin of: https://lore.kernel.org/qemu-devel/20241229234154.32250-1- del...@kernel.org/ "Add CPU reset function and speed up runtime and transl

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/31 上午10:51, Miao Hao wrote: On 2024/12/31 10:23, bibo mao wrote: On 2024/12/31 上午10:08, Miao Hao wrote: On 2024/12/31 09:18, bibo mao wrote: On 2024/12/31 上午9:09, bibo mao wrote: On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my

Re: [PULL 1/2] target/hppa: Add CPU reset method

Hi Helge, On 30/12/24 01:22, del...@kernel.org wrote: From: Helge Deller Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Although we currently want to zero ou

Re: [PATCH v6 6/8] chardev/char-mux: implement backend chardev multiplexing

Hi On Mon, Dec 23, 2024 at 5:24 PM Roman Penyaev wrote: > > This patch implements multiplexing capability of several backend > devices, which opens up an opportunity to use a single frontend > device on the guest, which can be manipulated from several > backend devices. > > The idea of the change

Re: [PATCH v6 0/8] chardev: implement backend chardev multiplexing

Hi On Mon, Dec 23, 2024 at 5:29 PM Roman Penyaev wrote: > > Mux is a character backend (host side) device, which multiplexes > multiple frontends with one backend device. The following is a > few lines from the QEMU manpage [1]: > > A multiplexer is a "1:N" device, and here the "1" end is your

Re: [PATCH v5 09/16] tests/qtest: Update tests using PL011 UART

On 29/7/24 17:47, Peter Maydell wrote: On Fri, 19 Jul 2024 at 19:11, Philippe Mathieu-Daudé wrote: We weren't enabling the PL011 TX UART before using it on the raspi and virt machines. Update the ASM code prefixing: *UART_CTRL = UART_ENABLE | TX_ENABLE; to: while (true) { *UART

Re: [PATCH v4] hw/smbios: support for type 7 (cache information)

On Sun, 22 Dec 2024 10:40:05 + Hal Martin wrote: > This patch adds support for SMBIOS type 7 (Cache Information) to qemu. > > level: cache level (1-8) > size: cache size > > Example usage: > -smbios type=7,level=1,size=1M > > Note: this does not change the actual layout of the CPU cache(s)

Re: [PATCH v3] fw_cfg: Don't set callback_opaque NULL in fw_cfg_modify_bytes_read()

On Wed, 11 Dec 2024 09:15:53 + Shameerali Kolothum Thodi via wrote: > Hi, > > A gentle ping on this. > > Hope the fix here is still valid and can be picked up. > Not sure by whom this will get picked up though. Perhaps Michael an pik it up, CCed. > > @Gerd? > > Thanks, > Shameer > > >

Re: [PATCH 1/2] target/hppa: Add CPU reset method

On 30/12/24 00:41, del...@kernel.org wrote: From: Helge Deller Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Although we currently want to zero out all value

Re: [RFC PATCH 0/4] cpu: Drop CPUState::nr_cores

On Thu, 5 Dec 2024 09:57:12 -0500 Xiaoyao Li wrote: > The series is motivated by auditing the usage of CPUState::nr_cores and > CPUState::nr_threads, which is motivated by [1]. > > The initial goal is to initialize nr_threads and nr_cores earlier for > x86, which leads to patches [2] and [3]. P

Re: [PATCH v16 00/14] macOS PV Graphics and new vmapple machine type

Cc'ing Joelle (FYI https://github.com/utmapp/UTM/issues/3491) On 23/12/24 23:16, Phil Dennis-Jordan wrote: This patch set introduces a new ARM and macOS HVF specific machine type called "vmapple", as well as a family of display devices based on the ParavirtualizedGraphics.framework in macOS. One

Re: [PATCH v16 00/14] macOS PV Graphics and new vmapple machine type

On 27/12/24 13:19, Phil Dennis-Jordan wrote: On Mon, 23 Dec 2024 at 23:58, Philippe Mathieu-Daudé > wrote: > Alexander Graf (8): >    hw: Add vmapple subdir >    hw/misc/pvpanic: Add MMIO interface >    gpex: Allow more than 4 legacy IRQs >

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons. On 2024/12/19 17:57, bibo mao wrote: Hi Miao, Thanks for doing this. It is useful to debug VM. On 2024/12/19 上午11:24, Miao Hao wrote: Signed-off-by: Miao

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

On 2024/12/31 上午9:09, bibo mao wrote: On 2024/12/30 下午3:04, Miao Hao wrote: Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons. On 2024/12/19 17:57, bibo mao wrote: Hi Miao, Thanks for doing this. It is useful to debug VM. On 2024/12/19 上午11

Addressing CVE-2024-3446 in qemu versions shipped in debian bullseye and older

Hello there, (Please CC me since I am not subscribed to the QEMU devel list.) I am working on backporting some CVE fixes to old Debian versions (bullseye and previous), and I would like to ask you some help to confirm if QEMU in those debian releases is affected by CVE-2024-3446 or not. This is Q

[RFC PATCH 2/9] rust: vmstate: implement VMState for non-leaf types

Arrays, pointers and cells use a VMStateField that is based on that for the inner type. The implementation therefore delegates to the VMState implementation of the inner type. Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 66 +++- 1 file changed

[RFC PATCH 5/9] rust: vmstate: implement VMState for scalar types

Scalar types are those that have their own VMStateInfo. This poses a problem in that references to VMStateInfo can only be included in associated consts starting with Rust 1.83.0, when the const_refs_static was stabilized. Removing the requirement is done by placing a limited list of VMStateInfos

[RFC PATCH 8/9] rust: pl011: switch vmstate to new-style macros

Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 3 ++- rust/hw/char/pl011/src/device_class.rs | 36 +- rust/hw/char/pl011/src/lib.rs | 6 + 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/rust/hw/char/pl011/src/devi

[RFC PATCH 0/9] rust: (mostly) type safe VMState

The existing translation of the C macros for vmstate does not make any attempt to type-check vmstate declarations against the struct, so introduce a new system that computes VMStateField based on the actual struct declaration. Macros do not have full access to the type system, therefore a full imp

[RFC PATCH 3/9] rust: vmstate: add varray support to vmstate_of!

Untested... Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 45 +--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs index e20f27b172b..079c19c687b 100644 --- a/rust/qemu-ap

[RFC PATCH 4/9] rust: vmstate: implement Zeroable for VMStateField

This shortens a bit the constants. Do not bother using it in the vmstate macros since most of them will go away soon. Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 18 +++--- rust/qemu-api/src/zeroable.rs | 31 +++ 2 files changed, 34 i

[RFC PATCH 9/9] rust: vmstate: remove translation of C vmstate macros

Keep vmstate_clock!; because it uses a field of type VMStateDescription, it cannot be converted to the VMState trait without access to the const_refs_static feature. Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 274 +++ 1 file changed, 23 insert

[RFC PATCH 1/9] rust: vmstate: add new type safe implementation

The existing translation of the C macros for vmstate does not make any attempt to type-check vmstate declarations against the struct, so introduce a new system that computes VMStateField based on the actual struct declaration. Macros do not have full access to the type system, therefore a full imp

[RFC PATCH 7/9] rust: qemu_api: add vmstate_struct and vmstate_cell

These are not type safe, but they're the best that can be done without const_refs_static. Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 34 ++ 1 file changed, 34 insertions(+) diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate

[RFC PATCH 6/9] rust: vmstate: add public utility macros to implement VMState

Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/vmstate.rs | 61 ++-- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs index edd0cbff162..b59a4b66339 100644 --- a/rust/qemu-api/src/vmstate

Re: [PULL 0/2] Hppa updates

Hi Stefan, On 30/12/24 01:22, del...@kernel.org wrote: From: Helge Deller The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7: Update version for v9.2.0 release (2024-12-10 16:20:54 +) are available in the Git repository at: https://github.com/hdeller/qemu-

Re: [PATCH] 9pfs: improve v9fs_open() tracing

On Monday, December 16, 2024 11:30:09 AM CET Christian Schoenebeck wrote: > Improve tracing of 9p 'Topen' request type by showing open() flags as > human-readable text. > > E.g. trace output: > > v9fs_open tag 0 id 12 fid 2 mode 100352 > > would become: > > v9fs_open tag=0 id=12 fid=2 mode=