Re: [PATCH v3 10/26] target/arm/kvm-rme: Add Realm Personalization Value parameter

On Tue, Nov 26, 2024 at 08:20:42AM +0100, Markus Armbruster wrote: > > +# @personalization-value: Realm personalization value, as a 64-byte > > +# hex string. This optional parameter allows to uniquely identify > > +# the VM instance during attestation. (default: 0) > > QMP commonly uses b

Re: [PATCH v3 00/24] Multifd 🔀 device state transfer support with VFIO consumer

On Sun, Nov 17, 2024 at 08:19:55PM +0100, Maciej S. Szmigiero wrote: > Important note: > 4 VF benchmarks were done with commit 5504a8126115 > ("KVM: Dynamic sized kvm memslots array") and its revert-dependencies > reverted since this seems to improve performance in this VM config if the > multifd t

Re: [PATCH v3 10/26] target/arm/kvm-rme: Add Realm Personalization Value parameter

On Tue, Nov 26, 2024 at 12:47:59PM +, Daniel P. Berrangé wrote: > On Tue, Nov 26, 2024 at 08:20:42AM +0100, Markus Armbruster wrote: > > Jean-Philippe Brucker writes: > > > > > The Realm Personalization Value (RPV) is provided by the user to > > > distinguish Realms that have the same initial

Re: [PATCH RFC 09/11] tests/qtest/migration: Don't use hardcoded strings for -serial

Peter Xu writes: > From: Fabiano Rosas > > Stop using hardcoded strings for -serial so we can in the next patches > perform more than one migration in a row. Having the serial path > hardcoded means we cannot reuse the code when dst becomes the new src. > > Signed-off-by: Fabiano Rosas > Link:

Re: [PATCH v3 02/24] thread-pool: Remove thread_pool_submit() function

On Sun, Nov 17, 2024 at 08:19:57PM +0100, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > This function name conflicts with one used by a future generic thread pool > function and it was only used by one test anyway. > > Update the trace event name in thread_pool_submit_aio() accord

Re: [PATCH v3 03/24] thread-pool: Rename AIO pool functions to *_aio() and data types to *Aio

On Sun, Nov 17, 2024 at 08:19:58PM +0100, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > These names conflict with ones used by future generic thread pool > equivalents. > Generic names should belong to the generic pool type, not specific (AIO) > type. > > Signed-off-by: Maciej S.

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote: > >> Make sure postcopy threads are released when migrate_cancel is > >> issued. Kick the postcopy_pause semaphore and have the fault thread > >>

[PATCH 0/7] RFC: gitlab: enable use of ccache in FreeBSD / macOS Cirrus CI jobs

We've seen that we exhaust the Cirrus CI free credits for the QEMU account, especially during the end of a release cycle. It is hard to cut down the CI credits burn beyond its current level without dropping features from the build configuration, which harms CI coverage. This proposes two things

[PATCH 1/7] gitlab: don't fail cirrus CI jobs when credits are exhausted

In the last week of the month we have often run out of credits on Cirrus CI, which causes the jobs to fail, in turn causing the overall pipeline to fail. The cirrus-run tool can now detect the "out of credits" scenario and exits with a code of '3'. We can tell gitlab to treat this exit code as sp

[PATCH 6/7] tests: update libvirt-ci submodule for newer ccache

This update pulls in ccache4 for FreeBSD, to match other platforms Signed-off-by: Daniel P. Berrangé --- .gitlab-ci.d/cirrus/freebsd-14.vars | 2 +- tests/lcitool/libvirt-ci| 2 +- tests/vm/generated/freebsd.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --gi

[PATCH 3/7] gitlab: clean packages in cirrus tasks

The FreeBSD VM is somewhat low on disk space after all QEMU build deps are installed and a full QEMU build performed. Purging the package manager cache is a simple thing that reclaims about 1 GB of space. Signed-off-by: Daniel P. Berrangé --- .gitlab-ci.d/cirrus.yml | 2 ++ .gitlab-ci.d/ci

[PATCH 5/7] gitlab: enable ccache with Cirrus CI

Add rules to configure the use of ccache with Cirrus CI jobs, and preserve the cache across jobs. The HomeBrew PATH was already present, but incorrect, while the FreeBSD PATH was missing. About 1 GB is enough to get a 99% hit rate on a pristine rebuild with no code changes. Setting it much higher

[PATCH 7/7] gitlab: force ccache to validate compiler version

By default ccache checks the compiler 'mtime' to determine if it should invalidate the cache. On FreeBSD the 'mtime' reflects when the compiler package was installed, rather than when it was built. IOW, on throwaway CI VMs, the 'mtime' changes on every single job and is thus useless. It could vali

[PATCH 2/7] gitlab: use new(ish) cirrus-vars command for creating config

Rather than a giant sed command with a hardcoded list of env var name, we can now use the new(ish) cirrus-vars command that libvirt has added to the 'cirrus-run' container. Signed-off-by: Daniel P. Berrangé --- .gitlab-ci.d/cirrus.yml | 23 +++ .gitlab-ci.d/cirrus/build

[PATCH 4/7] gitlab: purge build files from cirrus CI jobs

Uploading artifacts in Cirrus CI requires sufficient disk space to create a tarball of the artifact files. IOW, whatever size the artifacts are, double that. This results in space pressure on the FreeBSD jobs due to limited disk size. Purging the .o files from the meson build directory reclaims sig

[PATCH] vvfat: fix ubsan issue in create_long_filename

Found with test sbsaref introduced in [1]. [1] https://patchew.org/QEMU/20241203213629.2482806-1-pierrick.bouv...@linaro.org/ ../block/vvfat.c:433:24: runtime error: index 14 out of bounds for type 'uint8_t [11]' #0 0x56151a66b93a in create_long_filename ../block/vvfat.c:433 #1 0x56151a

Re: [PATCH v2] Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG

On 11/5/2024 10:27 AM, Taylor Simpson wrote: All Hexagon debugging is now done with QEMU mechanisms (e.g., -d in_asm) or with a connected debugger (lldb). Signed-off-by: Taylor Simpson Reviewed-by: Matheus Tavares Bernardino --- I was wondering why I didn't see an update on this patch.  So

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote: > On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote: > > Peter Xu writes: > > > > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote: > > >> Make sure postcopy threads are released when migrate_cancel is > > >> iss

Re: [PATCH v4] tests/functional/aarch64: add tests for FEAT_RME

On 12/4/24 01:38, Alex Bennée wrote: Pierrick Bouvier writes: This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier Queued to testing/next, thanks. Thanks Alex. FYI, th

Re: [PATCH v3 04/24] thread-pool: Implement generic (non-AIO) pool support

On Sun, Nov 17, 2024 at 08:19:59PM +0100, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > Migration code wants to manage device data sending threads in one place. > > QEMU has an existing thread pool implementation, however it is limited > to queuing AIO operations only and essentia

[PATCH 03/20] target/arm: Implement CPUClass::datapath_is_big_endian

arm_cpu_virtio_is_big_endian() already returns whether the data path is in big endian. Re-use that. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..3061b2ac1

[PATCH 01/20] exec/tswap: Rename target_words_bigendian -> qemu_binary_is_bigendian

target_words_bigendian() doesn't return whether a target vCPU expects data in big-endian order, but whether the *binary* has been compiled with big-endian flavor by default. Rename it appropriately to reduce confusion. Mechanical change doing: $ sed -i -e s/target_words_bigendian/qemu_binary_is_

[PATCH 00/20] target: Implement CPUClass::datapath_is_big_endian() handlers

The long term goal is to remove endianness knowledge from QEMU system binaries, allowing them to run vCPU in any endianness. For that target_words_bigendian(), TARGET_BIG_ENDIAN and few other things (like MO_TE) must be removed. Have each target implement a datapath_is_big_endian() handler to expr

[PATCH 12/20] target/xtensa: Implement xtensa_isa_is_big_endian()

Xtensa internal fields are opaque, only accessible by the Xtensa libisa. Implement xtensa_isa_is_big_endian() to get vCPU endianness. This should be implemented in libisa, not QEMU, but I couldn't figure out where to contribute this. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/xtensa/xt

[PATCH 13/20] target/xtensa: Implement CPUClass::datapath_is_big_endian

Implement Xtensa datapath_is_big_endian() helper via libisa. Signed-off-by: Philippe Mathieu-Daudé --- Other accesses to xtensa_isa_internal fields don't call cpu_synchronize_state(), and the libisa doesn't provide a way to switch endianness from translation code. Should we add a sync just in cas

[PATCH 10/20] target/microblaze: Implement CPUClass::datapath_is_big_endian

Implement the MicroBlaze datapath_is_big_endian() handler, returning the value of the ENDI bit. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 11 +++ 2 files changed, 13 insertions(+) diff --git a/target/microblaze/cpu.h b/target/mi

[PATCH 09/20] target/sh4: Implement CPUClass::datapath_is_big_endian

Implement SH4 datapath_is_big_endian() helper, returning the 'little_endian' property set at reset. Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index f54005644c9..69108c1676e 100644 ---

[PATCH 16/20] hw/core/cpu: Expose cpu_datapath_is_big_endian() method

All target implement their CPUClass::datapath_is_big_endian() helper, we can expose the generic cpu_datapath_is_big_endian() method. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 8 hw/core/cpu-common.c | 7 +++ 2 files changed, 15 insertions(+) diff --git a/in

[PATCH 20/20] hw/core/cpu: Remove cpu_virtio_is_big_endian()

There are no more calls to cpu_virtio_is_big_endian(). Remove the method and the SysemuCPUOps::virtio_is_big_endian helpers altogether. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 9 - include/hw/core/sysemu-cpu-ops.h | 8 hw/core/cpu-sysemu.c

[PATCH 08/20] target/sh4: Expose CPUSH4State::little_endian property

SH4 CPUs endianness is set with an external pin in a power-on reset. Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h | 6 ++ target/sh4/cpu.c | 8 2 files changed, 14 insertions(+) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d928bcf0067..2502ddba102 100644 ---

[PATCH 04/20] target/ppc: Register CPUClass::datapath_is_big_endian

ppc_cpu_is_big_endian() already returns whether the data path is in big endian. Re-use that, exposing this helper for user emulation. Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu_init.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu_init.c

[PATCH 02/20] hw/core/cpu: Introduce CPUClass::datapath_is_big_endian() handler

Introduce the CPUClass::datapath_is_big_endian() handler, which returns whether a vCPU expects data in memory to be in big endian order or not. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/core/

[PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian

While the RISC-V data endianness can be changed at runtime, we do not implement that. The current translation code assumes little-endian memory accesses (See commit a2f827ff4f4 "target/riscv: accessors to registers upper part and 128-bit load/store"). Signed-off-by: Philippe Mathieu-Daudé --- ta

Re: [PATCH 7/7] gitlab: force ccache to validate compiler version

On 4/12/24 20:48, Daniel P. Berrangé wrote: By default ccache checks the compiler 'mtime' to determine if it should invalidate the cache. On FreeBSD the 'mtime' reflects when the compiler package was installed, rather than when it was built. IOW, on throwaway CI VMs, the 'mtime' changes on every

[PATCH 14/20] target: Implement CPUClass::datapath_is_big_endian (little-endian)

For all targets which have endianness architecturally predefined as little endian (built using TARGET_BIG_ENDIAN=n), their datapath_is_big_endian() handler simply returns %false. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 6 ++ target/avr/cpu.c | 7 ++- targ

[PATCH 17/20] disas: Use cpu_datapath_is_big_endian()

Rather that using the binary endianness, use the vCPU one. Signed-off-by: Philippe Mathieu-Daudé --- disas/disas-common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/disas/disas-common.c b/disas/disas-common.c index 7377de0715c..ef91c43449e 100644 --- a/disas/disas-comm

[PATCH 11/20] target/mips: Implement CPUClass::datapath_is_big_endian

Implement MIPS datapath_is_big_endian() handler using the already existing mips_env_is_bigendian() method. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c7..13d0ceaa8af

[PATCH 05/20] target/rx: Implement CPUClass::datapath_is_big_endian

While on RX the endianness can be set at RESET, we do not implement that; only little endianness is used. Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..391f3214168 100

[PATCH 18/20] hw/core/generic-loader: Use cpu_datapath_is_big_endian()

Rather that using the binary endianness, use the vCPU one. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/generic-loader.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index abdd4c08a38..7b3b5f06565 100644 --- a

Re: [PATCH 4/7] gitlab: purge build files from cirrus CI jobs

On 4/12/24 20:48, Daniel P. Berrangé wrote: Uploading artifacts in Cirrus CI requires sufficient disk space to create a tarball of the artifact files. IOW, whatever size the artifacts are, double that. This results in space pressure on the FreeBSD jobs due to limited disk size. Purging the .o fil

[RFC PATCH 19/20] hw/virtio: Use cpu_datapath_is_big_endian()

Rather that using the binary endianness, use the vCPU one. The target affected by this change are MIPS, MicroBlaze, SH-4 and Xtensa. SPARC, RISC-V and RX could be affected later if their CPUClass::datapath_is_big_endian() handler is fully implemented. Signed-off-by: Philippe Mathieu-Daudé --- h

[PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian)

For all targets which have endianness architecturally predefined as big endian (built using TARGET_BIG_ENDIAN=y), their datapath_is_big_endian() handler simply returns %true. Signed-off-by: Philippe Mathieu-Daudé --- target/hexagon/cpu.c | 6 ++ target/hppa/cpu.c | 6 ++ target/m68k

[PATCH v2 1/4] docs/system/arm/orangepi: update links

www.orangepi.org does not support https, it's expected to stick to http. Reviewed-by: Niek Linnenbank Signed-off-by: Pierrick Bouvier --- docs/system/arm/orangepi.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.

[PATCH v2 2/4] docs/system/arm/fby35: document execute-in-place property

Signed-off-by: Pierrick Bouvier --- docs/system/arm/fby35.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst index bf6da6baa2a..ed9faef363c 100644 --- a/docs/system/arm/fby35.rst +++ b/docs/system/arm/fby35.rst @@ -45,3 +45,6 @@ proces

[PATCH v2 0/4] Minor fixes for Arm documentation

Reviewed following things: - system/arm/cpu-features (options) - system/arm/virt (options) - boards documented and listed with -machine help (arm and aarch64) - grep object_class_property_set_description hw/arm: ensure all options are documented - reviewed boards description - reviewed all Arm fe

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

Daniel P. Berrangé writes: > On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote: >> On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote: >> > Peter Xu writes: >> > >> > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote: >> > >> Make sure postcopy threads are releas

[PATCH v2 3/4] docs/system/arm/xlnx-versal-virt: document ospi-flash property

Signed-off-by: Pierrick Bouvier --- docs/system/arm/xlnx-versal-virt.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst index 0bafc76469d..c5f35f28e4f 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/

[PATCH v2 4/4] docs/system/arm/virt: document missing properties

Signed-off-by: Pierrick Bouvier --- docs/system/arm/virt.rst | 16 1 file changed, 16 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 11ceb898264..d25275c27ce 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -169,10 +16

[PATCH] target/sparc: Use memcpy() in memcpy32()

Rather than manually copying each register, use the libc memcpy(), which is well optimized. Signed-off-by: Philippe Mathieu-Daudé --- Worth renaming as reg8cpy()? --- target/sparc/win_helper.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/sparc/win_helper.c b

Re: [PATCH 1/1] hw/arm/sbsa-ref: bump default memory size to 2GB

On 4/12/24 13:17, Leif Lindholm wrote: On 2024-12-02 10:53, Marcin Juszkiewicz wrote: W dniu 26.11.2024 o 14:14, Peter Maydell pisze: On Tue, 26 Nov 2024 at 08:49, Marcin Juszkiewicz wrote: We are working on adding RME support to SBSA Reference Platform. When RME is enabled then RMM (Realm M

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

On Wed, Dec 04, 2024 at 08:02:31PM +, Daniel P. Berrangé wrote: > On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote: > > On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote: > > > Peter Xu writes: > > > > > > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote: >

[PATCH v2] hw/arm/sbsa-ref: Require at least 2 GiB of RAM when RME feature enabled

We are working on adding RME support to SBSA Reference Platform. When RME is enabled then RMM (Realm Managment Monitor) takes 1072MB of memory for own use. Which ends with firmware panic on 1GB machine. Report an error so users directly start with more RAM in this case: $ qemu-system-aarch64 -M

A glimpse at PL011 emulation in safe Rust

Hi all, this is finally a look at what the PL011 device model would look like in Rust, without having to write unsafe so often. The attached file is a synopsis of the C code, the Rust code and my commentary (the C code is partly rearranged to match the ordering of the Rust code). The code compi

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

On Wed, Dec 04, 2024 at 05:40:17PM -0300, Fabiano Rosas wrote: > To be clear, I'm not arguing against cancel. I'm just pointing out that > it's silly because it's just like pressing C-c in the shell in the > middle of something. What's the expected end state? Completely > unspecified. I don't find

Re: [PATCH] 9pfs: improve v9fs_walk() tracing

On Tue, Dec 03, 2024 at 10:14:28AM +0100, Christian Schoenebeck wrote: > 'Twalk' is the most important request type in the 9p protocol to look out > for when debugging 9p communication. That's because it is the only part > of the 9p protocol which actually deals with human-readable path names, > wh

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

Peter Xu writes: > On Wed, Dec 04, 2024 at 08:02:31PM +, Daniel P. Berrangé wrote: >> On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote: >> > On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote: >> > > Peter Xu writes: >> > > >> > > > On Mon, Dec 02, 2024 at 07:01:33PM -030

[PATCH] MAINTAINERS: Add correct email address for Vikram Garhwal

Previously, maintainer role was paused due to inactive email id. Commit id: c009d715721861984c4987bcc78b7ee183e86d75. Signed-off-by: Vikram Garhwal --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aaf0505a21..b4723eecde 100644 --- a/MAINTAINER

Re: [PATCH 2/6] migration: Kick postcopy threads on cancel

On Wed, Dec 04, 2024 at 06:01:39PM -0300, Fabiano Rosas wrote: > > Considering it's confusing to mostly everyone, and tons of people asked me > > about this.. maybe I should send a patch to remove yank from migration? > > Take a look at my suggestion in the other thread, it might make yank > make

[PATCH 0/2] Change default pointer authentication algorithm on aarch64 to impdef

qemu-system-aarch64 default pointer authentication (QARMA5) is expensive, we spent up to 50% of the emulation time running it (when using TCG). Switching to pauth-impdef=on is often given as a solution to speed up execution. Thus we talked about making it the new default. The first patch introduc

[PATCH 1/2] target/arm: add new property to select pauth-qarma5

Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... Signed-off-by: Pierrick Bouvier --- docs/system/arm/cpu-features.rst | 5 - target/arm/cpu.h | 1 + target/a

Re: [PATCH v2] hw/arm/sbsa-ref: Require at least 2 GiB of RAM when RME feature enabled

On 12/4/24 12:56, Philippe Mathieu-Daudé wrote: We are working on adding RME support to SBSA Reference Platform. When RME is enabled then RMM (Realm Managment Monitor) takes 1072MB of memory for own use. Which ends with firmware panic on 1GB machine. Report an error so users directly start with

Re: [PATCH] target/sparc: Use memcpy() in memcpy32()

On 12/4/24 12:41, Philippe Mathieu-Daudé wrote: Rather than manually copying each register, use the libc memcpy(), which is well optimized. Signed-off-by: Philippe Mathieu-Daudé --- Worth renaming as reg8cpy()? --- target/sparc/win_helper.c | 9 + 1 file changed, 1 insertion(+), 8 de

[PATCH 06/20] target/sparc: Implement CPUClass::datapath_is_big_endian

While the SPARC data endianness can be changed at runtime, we do not implement that; only big endianness is used. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af8

Re: QEMU wiki theme table of contents changes

On Thu, Nov 21, 2024 at 03:48:12PM +, Daniel P. Berrangé wrote: > On Tue, Nov 19, 2024 at 02:54:29PM -0500, Stefan Hajnoczi wrote: > > On Fri, Nov 15, 2024 at 07:38:06PM +, Daniel P. Berrangé wrote: > > > On Fri, Nov 15, 2024 at 02:21:12PM -0500, Stefan Hajnoczi wrote: > > > > On Fri, 15 No

Re: [PATCH v3 05/24] migration: Add MIG_CMD_SWITCHOVER_START and its load handler

On Sun, Nov 17, 2024 at 08:20:00PM +0100, Maciej S. Szmigiero wrote: > diff --git a/migration/colo.c b/migration/colo.c > index 9590f281d0f1..a75c2c41b464 100644 > --- a/migration/colo.c > +++ b/migration/colo.c > @@ -452,6 +452,9 @@ static int colo_do_checkpoint_transaction(MigrationState > *s, >

Re: [PATCH v3 06/24] migration: Add qemu_loadvm_load_state_buffer() and its handler

On Sun, Nov 17, 2024 at 08:20:01PM +0100, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > qemu_loadvm_load_state_buffer() and its load_state_buffer > SaveVMHandler allow providing device state buffer to explicitly > specified device via its idstr and instance id. > > Reviewed-by: Fa

Re: [PATCH v3 07/24] migration: Document the BQL behavior of load SaveVMHandlers

On Sun, Nov 17, 2024 at 08:20:02PM +0100, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > Some of these SaveVMHandlers were missing the BQL behavior annotation, > making people wonder what it exactly is. > > Signed-off-by: Maciej S. Szmigiero > --- > include/migration/register.h |

Re: [PATCH v2 2/9] vfio/igd: align generation with i915 kernel driver

On Tue, 3 Dec 2024 21:35:41 +0800 Tomita Moeko wrote: > Define the igd device generations according to i915 kernel driver to > avoid confusion, and adjust comment placement to clearly reflect the > relationship between ids and devices. > > The condition of how GTT stolen memory size is calculat

Re: [PATCH v2 3/9] vfio/igd: canonicalize memory size calculations

On Tue, 3 Dec 2024 21:35:42 +0800 Tomita Moeko wrote: > Add helper functions igd_gtt_memory_size() and igd_stolen_size() for > calculating GTT stolen memory and Data stolen memory size in bytes, > and use macros to replace the hardware-related magic numbers for > better readability. > > Signed-

Re: [PATCH v2 9/9] vfio/igd: add x-igd-gms option back to set DSM region size for guest

On Tue, 3 Dec 2024 16:30:56 + Corvin Köhne wrote: > On Tue, 2024-12-03 at 21:35 +0800, Tomita Moeko wrote: > > CAUTION: External Email!! > > DSM region is likely to store framebuffer in Windows, a small DSM > > region may cause display issues (e.g. half of the screen is black). > > By defaul

Re: [PATCH v2 7/9] vfio/igd: emulate GGC register in mmio bar0

On Tue, 3 Dec 2024 21:35:46 +0800 Tomita Moeko wrote: > The GGC register at 0x50 of pci config space is a mirror of the same > register at 0x108040 of mmio bar0 [1]. i915 driver also reads that > register from mmio bar0 instead of config space. As GGC is programmed > and emulated by qemu, the mm

Re: [RFC PATCH v3 01/11] plugins: add types for callbacks related to certain discontinuities

On 12/3/24 00:45, Julian Ganz wrote: Hi, December 2, 2024 at 8:26 PM, "Julian Ganz" wrote: diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 0fba36ae02..9c67374b7e 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -154,6 +154,49 @@ typedef void

[PATCH 2/2] target/arm: change default pauth algorithm to impdef

Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=on). The advice is always: use pauth-impdef=on. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we c

Re: [PATCH v3 08/24] migration: Add thread pool of optional load threads

On Thu, Nov 28, 2024 at 01:11:53PM +0100, Maciej S. Szmigiero wrote: > > > +static int qemu_loadvm_load_thread(void *thread_opaque) > > > +{ > > > +    struct LoadThreadData *data = thread_opaque; > > > +    int ret; > > > + > > > +    ret = data->function(&load_threads_abort, data->opaque); > > >

Re: [RFC PATCH v3 01/11] plugins: add types for callbacks related to certain discontinuities

Hi Julian, thanks for the update! Comments below. On 12/2/24 11:26, Julian Ganz wrote: The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. However, traps of any kind, i.e. interrupts or exceptions, were previously not covere

Re: [PATCH v2 6/9] vfio/igd: add macro for declaring mirrored registers

On Tue, 3 Dec 2024 21:35:45 +0800 Tomita Moeko wrote: > igd devices have multipe registers mirroring mmio address and pci > config space, more than a single BDSM register. To support this, > the read/write functions are made common and a macro is defined to > simplify the declaration of MemoryRe

Re: [RFC PATCH v3 02/11] plugins: add API for registering discontinuity callbacks

On 12/2/24 11:26, Julian Ganz wrote: The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. In addition to those events, we recently defined discontinuity events, which include traps. This change introduces a function to registe

Re: [RFC PATCH v3 03/11] plugins: add hooks for new discontinuity related callbacks

On 12/2/24 11:26, Julian Ganz wrote: The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. In addition, we recently introduced API for registering callbacks for discontinuity events, specifically for interrupts, exceptions and h

Re: [RFC PATCH v3 05/11] target/alpha: call plugin trap callbacks

On 12/2/24 11:26, Julian Ganz wrote: We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for Alpha targ

Re: [PATCH v3 08/24] migration: Add thread pool of optional load threads

On Wed, Nov 27, 2024 at 09:16:49PM +0100, Maciej S. Szmigiero wrote: > On 27.11.2024 10:13, Cédric Le Goater wrote: > > On 11/17/24 20:20, Maciej S. Szmigiero wrote: > > > From: "Maciej S. Szmigiero" > > > > > > Some drivers might want to make use of auxiliary helper threads during VM > > > state

Re: [RFC PATCH v3 00/11] tcg-plugins: add hooks for discontinuities

On 12/3/24 00:36, Julian Ganz wrote: Hi, I just realized that I forgot to run the checkpatch script on the patches again before sending and did not include the Sign-Off. Sorry about that. Regards, Julian Ganz No worries, it's pretty frequent that people forgot those. While at it, you can fi

Re: [RFC PATCH v3 04/11] contrib/plugins: add plugin showcasing new dicontinuity related API

On 12/2/24 11:26, Julian Ganz wrote: We recently introduced new plugin API for registration of discontinuity related callbacks. This change introduces a minimal plugin showcasing the new API. It simply counts the occurances of interrupts, exceptions and host calls per CPU and reports the counts w

Re: [RFC PATCH v3 11/11] tests: add plugin asserting correctness of discon event's to_pc

On 12/2/24 11:41, Julian Ganz wrote: We recently introduced plugin API for the registration of callbacks for discontinuity events, specifically for interrupts, exceptions and host call events. The callback receives, among other information, the VCPU index and the PC after the event. This change i

Re: [PATCH 01/20] exec/tswap: Rename target_words_bigendian -> qemu_binary_is_bigendian

On 12/4/24 14:25, Philippe Mathieu-Daudé wrote: target_words_bigendian() doesn't return whether a target vCPU expects data in big-endian order, but whether the*binary* has been compiled with big-endian flavor by default. Rename it appropriately to reduce confusion. Mechanical change doing: $

Re: [PATCH 03/20] target/arm: Implement CPUClass::datapath_is_big_endian

On 12/4/24 14:25, Philippe Mathieu-Daudé wrote: arm_cpu_virtio_is_big_endian() already returns whether the data path is in big endian. Re-use that. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) No, this is wrong. (1)

Re: [PATCH 17/20] disas: Use cpu_datapath_is_big_endian()

On 12/4/24 14:25, Philippe Mathieu-Daudé wrote: Rather that using the binary endianness, use the vCPU one. Signed-off-by: Philippe Mathieu-Daudé --- disas/disas-common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/disas/disas-common.c b/disas/disas-common.c index 73

Re: [PATCH v3 6/7] aspeed/soc: Support SDHCI for AST2700

On 12/4/24 09:05, Jamin Lin wrote: Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 slot and registers base address is start at 0x1408_ and its interrupt is connected to GICINT133_INTC at bit 1. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks

Re: [PATCH v3 7/7] aspeed/soc: Support eMMC for AST2700

On 12/4/24 09:05, Jamin Lin wrote: Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 slot and registers base address is start at 0x1209_ and its interrupt is connected to GICINT 15. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. --- h

Re: [PATCH v3 2/7] hw/arm/aspeed: Fix coding style

On 12/4/24 09:05, Jamin Lin wrote: Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed_ast2600.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_

Re: [PATCH v3 3/7] hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers

On 12/4/24 09:05, Jamin Lin wrote: Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support fo

Re: [PATCH 5/5] tests/functional: Convert the migration avocado test

On 04/12/2024 08.19, Thomas Huth wrote: Now that we've got a find_free_port() function in the functional test framework, we can convert the migration test, too. While the original avocado test was only meant to run on aarch64, ppc64 and x86, we can turn this into a more generic test by now and ru

[PATCH v3 7/7] aspeed/soc: Support eMMC for AST2700

Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 slot and registers base address is start at 0x1209_ and its interrupt is connected to GICINT 15. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 15 +++ 1 file changed, 15 insertions(+) diff --gi

[PATCH v3 3/7] hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers

Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg"

[PATCH v3 6/7] aspeed/soc: Support SDHCI for AST2700

Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 slot and registers base address is start at 0x1408_ and its interrupt is connected to GICINT133_INTC at bit 1. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 20 1 file changed, 20 ins

[PATCH v3 0/7] Support SDHCI and eMMC for ast2700

change from v1: This patch series do not support boot from an eMMC. Only support eMMC and SD Slot 0 as storages. change from v2: - Add hw/sd/aspeed_sdhci: Fix coding style patch change from v3: - Directly set capareg and sd_spec_version instead of property - Keep DEFINE_TYPES Jamin Lin (7): hw

[PATCH v3 1/7] hw/sd/aspeed_sdhci: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 98d5460905..acd6538261 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sd

[PATCH 5/5] tests/functional: Convert the migration avocado test

Now that we've got a find_free_port() function in the functional test framework, we can convert the migration test, too. While the original avocado test was only meant to run on aarch64, ppc64 and x86, we can turn this into a more generic test by now and run it on all architectures that have a defa

[PATCH 3/5] tests/functional/test_vnc: Do not use a hard-coded VNC port

Two tests here are using the hard-coded VNC port :0 ... if there is already a QEMU or other program running that is using this port, the tests will be failing. Let's better detect a free port for these tests and use that one instead. Signed-off-by: Thomas Huth --- tests/functional/test_vnc.py |

Re: [PATCH v3 1/7] hw/sd/aspeed_sdhci: Fix coding style

On 12/4/24 09:05, Jamin Lin wrote: Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. --- hw/sd/aspeed_sdhci.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdh

[PATCH v3 2/7] hw/arm/aspeed: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast2600.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index be3eb70cdd..c40d3d8443 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/

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