From: Daniel P. Berrangé
balloon_stats_get_all will iterate over guest stats upto the max
VIRTIO_BALLOON_S_NR value, calling visit_type_uint64 to populate
the QObject dict. The dict keys are obtained from the static
array balloon_stat_names which is VIRTIO_BALLOON_S_NR in size.
Unfortunately the
From: Daniel P. Berrangé
This test file is expected to be extended for arbitrary virtio-balloon
related tests, not merely those discovered by fuzzing.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fabiano Rosas
Message-ID: <20241129135507.699030-3-berra...
These warnings are breaking some build configurations since 2 months
now (https://gitlab.com/qemu-project/qemu/-/issues/2575):
ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated:
first deprecated in macOS 15.0 - use NSView.displayLink(target:selector:),
NSWindow.display
On Fri, 22 Nov 2024 10:11:30 +0100
Mauro Carvalho Chehab wrote:
> Currently, CPER address location is calculated as an offset of
> the hardware_errors table. It is also badly named, as the
> offset actually used is the address where the CPER data starts,
> and not the beginning of the error sourc
On Fri, 22 Nov 2024 10:11:31 +0100
Mauro Carvalho Chehab wrote:
> Extending to multiple sources require a BIOS pointer to the
> beginning of the HEST table, which in turn requires a backward-compatible
> code.
>
> So, the current code supports only one source. Ensure that and simplify
> the code
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport :08:01.0: pciehp: Slot(2): Card present
pcieport :08:01.0: pciehp: Slot(2): Link Up
pcieport :08:01.0: pciehp: Slot(2): Cannot train link: status 0
On Tue, 3 Dec 2024, Gerd Hoffmann wrote:
Hi,
For bochs and ati, there's a register to configure it as well, so there
*may* be an expectation that it gets reset there, I'm less certain.
The default is there for backward compatibility reasons and it should
default to machine byte order so you
Daniel P. Berrangé writes:
> On Mon, Dec 02, 2024 at 02:49:33PM -0500, Peter Xu wrote:
>> On Sat, Nov 30, 2024 at 10:01:43PM +0800, Yong Huang wrote:
>> > On Fri, Nov 29, 2024 at 9:44 PM Fabiano Rosas wrote:
>> For the stress.c warnings/error, I saw another one warning with gcc when
>> built it
>
> There was a question from Jonathan Cameron on the original posting of this
> patch that is awaiting your answer
Sorry, the reply is forgotten to cc qemu-devel, I have resend it.
>
>
> Regardless, at this time in the release cycle its too late for 9.2, so this
> patch would likely need to
On Tue, Dec 03, 2024 at 09:20:44AM -0300, Fabiano Rosas wrote:
> Daniel P. Berrangé writes:
>
> > On Mon, Dec 02, 2024 at 02:49:33PM -0500, Peter Xu wrote:
> >> On Sat, Nov 30, 2024 at 10:01:43PM +0800, Yong Huang wrote:
> >> > On Fri, Nov 29, 2024 at 9:44 PM Fabiano Rosas wrote:
> >> For the st
Daniel P. Berrangé writes:
> On Tue, Dec 03, 2024 at 09:20:44AM -0300, Fabiano Rosas wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Mon, Dec 02, 2024 at 02:49:33PM -0500, Peter Xu wrote:
>> >> On Sat, Nov 30, 2024 at 10:01:43PM +0800, Yong Huang wrote:
>> >> > On Fri, Nov 29, 2024 at 9:44 PM F
Shameer Kolothum via writes:
> From Commit 90fa121c6c07 ("migration/multifd: Inline page_size and
> page_count") onwards page_size is not part of MutiFD*Params but uses
> an inline constant instead.
>
> However, it missed updating an old usage, causing a compile error.
>
> Fixes: 90fa121c6c07 ("m
On arm/virt platform, Chen Xiang reported a Guest crash while
attempting the below steps,
1. Launch the Guest with nvdimm=on
2. Hot-add a NVDIMM dev
3. Reboot
4. Guest boots fine.
5. Reboot again.
6. Guest boot fails.
QEMU_EFI reports the below error:
ProcessCmdAddPointer: invalid pointer value i
On Tue, Dec 3, 2024 at 8:34 PM Philippe Mathieu-Daudé wrote:
>
> From: Peter Maydell
>
> In riscv_cpu_do_interrupt() we use the 'cause' value we got out of
> cs->exception as a shift value. However this value can be larger
> than 31, which means that "1 << cause" is undefined behaviour,
> becaus
On Wed, Nov 13, 2024 at 02:17:48PM -0300, Daniel Henrique Barboza wrote:
> ssstateen is defined in RVA22 as:
>
> "Supervisor-mode view of the state-enable extension. The supervisor-mode
> (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
> must be provided."
>
> Add ssstateen
On Fri, 22 Nov 2024 10:11:32 +0100
Mauro Carvalho Chehab wrote:
> While the spec defines a CPER size of 4KiB for each record,
> currently it is set to 1KiB. Fix the documentation and add
> a pointer to the macro name there, as this may help to keep
> it updated.
>
> Signed-off-by: Mauro Carvalho
From: Ahmad Fatoum
We used to only have a single UART on the platform and it was located at
address 0x9000. When the number of UARTs was increased to 4, the
first UART remained at it's location, but instead of being the first one
to be registered, it became the last.
This caused QEMU to pick
From: Daniel P. Berrangé
The 'maxmem' parameter parsed on the command line is held in uint64_t
and then assigned to the MachineState field that is 'ram_addr_t'. This
assignment will wrap on 32-bit hosts, silently changing the user's
config request if it were over-sized.
Improve the existing diag
When testing with a HVF-only binary, we get:
3/12 qemu:func-quick+func-aarch64 / func-aarch64-version
ERROR0.29s exit status 1
stderr:
Traceback (most recent call last):
File "tests/functional/test_version.py", line 22, in
test_qmp_hu
From: Daniel P. Berrangé
This test would have identified the crash caused by the addition of new
balloon stats fields.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Fabiano Rosas
Acked-by: Michael S. Tsirkin
Message-ID: <20241129135507.699030-4-berra...@redhat.com>
Signed-off-by: Philippe Ma
When building QEMU configure with --disable-gtk --disable-cocoa
on macOS we get:
User interface
Cocoa support : NO
SDL support : YES 2.30.5
SDL image support : NO
GTK support : NO
pixman
From: Bibo Mao
Song Gao is will be sick leave for a long time, I apply for maintainer
for LoongArch Virt Machine during this period, LoongArch TCG keeps unchanged
since I am not familiar with it. The maintainer duty will transfer to him
after he comes back to work.
Signed-off-by: Bibo Mao
Acked
From: Peter Maydell
In riscv_cpu_do_interrupt() we use the 'cause' value we got out of
cs->exception as a shift value. However this value can be larger
than 31, which means that "1 << cause" is undefined behaviour,
because we do the shift on an 'int' type.
This causes the undefined behaviour sa
On Fri, 22 Nov 2024 10:11:25 +0100
Mauro Carvalho Chehab wrote:
> Split the code into separate functions to allow using the
> common CPER filling code by different error sources.
>
> The generic code was moved to ghes_record_cper_errors(),
> and ghes_gen_err_data_uncorrectable_recoverable() now
On Sun, 1 Dec 2024 at 15:16, Richard Henderson
wrote:
>
> This includes REV16, REV32, REV64.
>
> Signed-off-by: Richard Henderson
> ---
> @@ -10070,10 +10003,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
> uint32_t insn)
> TCGv_ptr tcg_fpstatus;
>
> switch (opcode) {
> -
> > Some hardware devices now support PCIe 5.0, so change the default
> > speed of the PCIe root port on new machine types.
> >
> > For passthrough Nvidia H20, this will be able to increase the h2d/d2h
> > bandwidth ~17%.
>
>
> I'm curious. Why are you seeing the perf improvement?
>
>
> Maybe my me
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.com" which was ~briefly
used for some replies to mailing list traffic.
Signed-off-by: Brian Cain
Signed-off-by: Brian Cain
Tested-by: Philippe Mathieu-Daudé
Message-ID: <20241123164641.364748-2-bc...@quicinc.com>
Signed-off-by: Philip
The 'pci-vga' device allow setting a 'big-endian-framebuffer'
property since commit 3c2784fc864 ("vga: Expose framebuffer
byteorder as a QOM property"). Similarly, the 'virtio-vga'
device since commit 8be61ce2ce3 ("virtio-vga: implement
big-endian-framebuffer property").
Both call vga_common_reset
From: Joel Holdsworth
In the existing design, TTCR is prone to undercounting when running in
continuous mode. This manifests as a timer interrupt appearing to
trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
When the timer triggers, the virtual time delta in nanoseconds between
the
The following changes since commit eb22a064455aeebc105cc89bf77f48aa18b52938:
Merge tag 'pull-request-2024-12-02' of https://gitlab.com/thuth/qemu into
staging (2024-12-02 16:16:15 +)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-202
On 12/2/24 07:13, Peter Maydell wrote:
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
to get the NaN bit pattern to reset the FPU registers. This
works because it happens that our implementation of
floatx80_default_nan() doesn't actually look at the float_status
pointer except f
On Fri, 22 Nov 2024 14:14:10 +0100
Mauro Carvalho Chehab wrote:
> This series was part of the previous PR to add generic error injection
> support on GHES. It depends on a cleanup patch series sent earlier
> today:
>
>
> https://lore.kernel.org/qemu-devel/cover.1732266152.git.mchehab+hua
>From Commit 90fa121c6c07 ("migration/multifd: Inline page_size and
page_count") onwards page_size is not part of MutiFD*Params but uses
an inline constant instead.
However, it missed updating an old usage, causing a compile error.
Fixes: 90fa121c6c07 ("migration/multifd: Inline page_size and pag
Hi Peter!
The following changes since commit 72b88908d12ee9347d13539c7dd9a252625158d1:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-11-29 10:09:05 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2024-12-0
All gen 11 and 12 igd devices have 64 bit BDSM register at 0xC0 in its
config space, add them to the list to support igd passthrough on Alder/
Raptor/Rocket/Ice/Jasper Lake platforms.
Tested legacy mode of igd passthrough works properly on both linux and
windows guests with AlderLake-S GT1 (8086:4
Add helper functions igd_gtt_memory_size() and igd_stolen_size() for
calculating GTT stolen memory and Data stolen memory size in bytes,
and use macros to replace the hardware-related magic numbers for
better readability.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 99 +++
Both Gemini Lake and Comet Lake are gen 9 devices. Many user reports
on internet shows legacy mode of igd passthrough works as qemu treats
them as gen 8 devices by default before e433f208973f ("vfio/igd:
return an invalid generation for unknown devices").
Signed-off-by: Tomita Moeko
---
hw/vfio/
Since e433f208973f ("vfio/igd: return an invalid generation for unknown
devices"), the default return of igd_gen() was changed to unsupported.
There is no need to filter out those unsupported devices.
Reviewed-by: Alex Williamson
Reviewed-by: Corvin Köhne
Signed-off-by: Tomita Moeko
---
hw/vfi
DSM region is likely to store framebuffer in Windows, a small DSM
region may cause display issues (e.g. half of the screen is black).
By default, QEMU uses host's original value, which is determined by
DVMT Pre-Allocated option in Intel FSP of host bios. Some vendors
do not expose this config item
A recent commit in i915 driver [1] claims the BDSM register at 0x1080c0
of mmio bar0 has been there since gen 6. Mirror this register to the 32
bit BDSM register at 0x5c in pci config space for gen6-10 devices.
[1]
https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-7-ville.syrj...
The GGC register at 0x50 of pci config space is a mirror of the same
register at 0x108040 of mmio bar0 [1]. i915 driver also reads that
register from mmio bar0 instead of config space. As GGC is programmed
and emulated by qemu, the mmio address should also be emulated, in the
same way of BDSM regis
Em Tue, 3 Dec 2024 12:42:32 +0100
Igor Mammedov escreveu:
> > +/*
> > + * Clear the Read Ack Register, OSPM will write it to 1 when
> ^ typo?
> > + * it acknowledges this error.
> > + */
Yes. I'll add this hunk there:
This patchset extends the support of legacy mode igd passthrough to
all Intel Gen 11 and 12 devices (including Ice Lake, Jasper Lake,
Rocket Lake, Alder Lake and Raptor Lake), and emulates GGC register
in MMIO BAR0 for better compatibiltiy (It is tested Windows and GOP
driver will read this MMIO re
igd devices have multipe registers mirroring mmio address and pci
config space, more than a single BDSM register. To support this,
the read/write functions are made common and a macro is defined to
simplify the declaration of MemoryRegionOps.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 60 ++
From: Nicholas Piggin
Peter points out double underscore prefix names tend to be reserved
for the system. Clean these up.
Suggested-by: Peter Maydell
Signed-off-by: Nicholas Piggin
Reviewed-by: Marc-André Lureau
Reviewed-by: Peter Maydell
Message-ID: <20240828043337.14587-3-npig...@gmail.com
From: Marc-André Lureau
The following changes since commit eb22a064455aeebc105cc89bf77f48aa18b52938:
Merge tag 'pull-request-2024-12-02' of https://gitlab.com/thuth/qemu into
staging (2024-12-02 16:16:15 +)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/qe
From: Nicholas Piggin
qemu_chardev_set_replay() was being called in chardev creation to
set up replay parameters even if the chardev is NULL.
A segfault can be reproduced by specifying '-serial chardev:bad' with
an rr=record mode.
Fix this with a NULL pointer check.
Reported-by: Peter Maydell
On 3/12/24 15:31, Peter Maydell wrote:
On Tue, 3 Dec 2024 at 14:23, Brian Cain wrote:
On 12/2/2024 2:43 PM, Philippe Mathieu-Daudé wrote:
On 23/11/24 17:46, Brian Cain wrote:
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.com" which was ~briefly
used for some replies to mailin
On 29/11/2024 19:15, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
On 29.11.2024 15:08, Cédric Le Goater wrote:
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
It's possible for load_cleanup SaveVMHandler to get called withou
Hi Pierrick,
On 12/2/24 14:33, Pierrick Bouvier wrote:
On 12/2/24 03:04, Peter Maydell wrote:
On Mon, 2 Dec 2024 at 10:58, Marcin Juszkiewicz
wrote:
W dniu 1.12.2024 o 19:09, Pierrick Bouvier pisze:
Hi Marcin,
On 12/1/24 05:34, Marcin Juszkiewicz wrote:
So RME tests probably need longer
Pierrick Bouvier writes:
> This boot an OP-TEE environment, and launch a nested guest VM inside it
> using the Realms feature. We do it for virt and sbsa-ref platforms.
>
> Signed-off-by: Pierrick Bouvier
>
> +
> +self.vm.add_args('-accel', 'tcg')
> +self.vm.add_args('-cpu', 'ma
On 03.12.24 15:39, William Roche wrote:
On 12/3/24 15:08, David Hildenbrand wrote:
[...]
Let me take a look at your tool below if I can find an explanation of
what is happening, because it's weird :)
[...]
At the end of this email, I included the source code of a simplistic
test case that s
Hi Alex,
On 12/2/24 15:23, Alex Bennée wrote:
Pierrick Bouvier writes:
On 12/2/24 02:57, Peter Maydell wrote:
On Sun, 1 Dec 2024 at 18:09, Pierrick Bouvier
wrote:
Hi Marcin,
On 12/1/24 05:34, Marcin Juszkiewicz wrote:
W dniu 28.11.2024 o 22:37, Pierrick Bouvier pisze:
This boot an OP-T
On 12/3/2024 8:53 AM, Philippe Mathieu-Daudé wrote:
On 3/12/24 15:31, Peter Maydell wrote:
On Tue, 3 Dec 2024 at 14:23, Brian Cain
wrote:
On 12/2/2024 2:43 PM, Philippe Mathieu-Daudé wrote:
On 23/11/24 17:46, Brian Cain wrote:
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.
On 12/3/2024 3:33 PM, Zhao Liu wrote:
However, back to the patch, I think we cannot change it as this patch
directly. Instead, we need a compat_props for the changed behavior, because
this isn't a bug fix and it introduces guest-visible differences.
This is a fix, not a new feature, so compat_p
On Tue, Dec 03, 2024 at 11:04:12PM +0800, Xiaoyao Li wrote:
> Date: Tue, 3 Dec 2024 23:04:12 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for
> logical processors in the physical package
>
> On 12/3/2024 3:33 PM, Zhao Liu wrote:
> > > However, back
On Tue, Dec 03, 2024 at 03:33:41PM +0800, Zhao Liu wrote:
> > However, back to the patch, I think we cannot change it as this patch
> > directly. Instead, we need a compat_props for the changed behavior, because
> > this isn't a bug fix and it introduces guest-visible differences.
>
> This is a fi
Daniel P. Berrangé writes:
> These functions all return NULL rather than asserting, if the requested
> type is not registered and also cannot be dynamically loaded.
>
> In several cases their usage is pointless, since the caller then just
> reports an error & exits anyway. Easier to just let qdev
On Mon, Dec 02, 2024 at 12:06:09PM +0100, Paolo Bonzini wrote:
> Date: Mon, 2 Dec 2024 12:06:09 +0100
> From: Paolo Bonzini
> Subject: [PATCH v2 2/2] rust: add bindings for interrupt sources
> X-Mailer: git-send-email 2.47.0
>
> The InterruptSource bindings let us call qemu_set_irq() and sysbus_
Gustavo Romero writes:
> Hi Alex,
>
> On 12/2/24 15:23, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 12/2/24 02:57, Peter Maydell wrote:
On Sun, 1 Dec 2024 at 18:09, Pierrick Bouvier
wrote:
>
> Hi Marcin,
>
> On 12/1/24 05:34, Marcin Juszkiewicz wrote:
>>>
On 12/3/24 08:05, Peter Maydell wrote:
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 24 ++--
target/arm/tcg/a64.decode | 3 +++
2 files changed, 9 insertions(+), 18 deletions(-)
@@ -8
On 12/3/24 08:55, Gustavo Romero wrote:
It's not "really" using kvm acceleration right?
It's using kvm but the kvm module in the host kernel is actually running
fully emulated in QEMU system mode (-accel tcg is being passed to it).
So I understand it's "all TCG" in the end and no HW acceleratio
Gustavo Romero writes:
> Hi Pierrick,
>
> On 12/2/24 14:33, Pierrick Bouvier wrote:
>> On 12/2/24 03:04, Peter Maydell wrote:
>>> On Mon, 2 Dec 2024 at 10:58, Marcin Juszkiewicz
>>> wrote:
W dniu 1.12.2024 o 19:09, Pierrick Bouvier pisze:
> Hi Marcin,
>
> On 12/1/24 05:34,
On 27/11/24 12:40, Daniel P. Berrangé wrote:
The 'maxmem' parameter parsed on the command line is held in uint64_t
and then assigned to the MachineState field that is 'ram_addr_t'. This
assignment will wrap on 32-bit hosts, silently changing the user's
config request if it were over-sized.
Impro
On 21/11/24 14:19, Philippe Mathieu-Daudé wrote:
These warnings are breaking some build configurations since 2 months
now (https://gitlab.com/qemu-project/qemu/-/issues/2575):
ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated:
first deprecated in macOS 15.0 - use NSV
On 20/11/24 12:49, Philippe Mathieu-Daudé wrote:
When building QEMU configure with --disable-gtk --disable-cocoa
on macOS we get:
../system/main.c:30:10: fatal error: 'SDL.h' file not found
30 | #include
| ^~~
1 error generated.
Fix by adding the SDL dependenc
On 12/11/24 08:37, Bibo Mao wrote:
Song Gao is will be sick leave for a long time, I apply for maintainer
for LoongArch VirtMachien during this period, LoongArch TCG keeps unchanged
since I am not familiar with it. The maintainer duty will transfer to him
after he comes back to work.
Signed-off-
On 3/12/24 09:08, Michael S. Tsirkin wrote:
On Mon, Dec 02, 2024 at 08:50:55PM +0100, Philippe Mathieu-Daudé wrote:
Hi,
On 2/12/24 18:05, David Hildenbrand wrote:
On 29.11.24 14:55, Daniel P. Berrangé wrote:
See patch 1 for the background info on the problem
Changed in v2:
* Add qtest co
On Mon, Dec 02, 2024 at 04:17:41PM -0800, Pierrick Bouvier wrote:
> This boot an OP-TEE environment, and launch a nested guest VM inside it
> using the Realms feature. We do it for virt and sbsa-ref platforms.
>
> Signed-off-by: Pierrick Bouvier
>
> -
>
> v2:
> - move test to its own file
>
On Mon, 18 Nov 2024 at 17:24, Pierrick Bouvier
wrote:
>
> Present the various parts of QEMU and organization of codebase.
>
> Signed-off-by: Pierrick Bouvier
I like this; it's something I've thought for a while would
be good to have, but which I never got round to trying to
put together. Thanks
On 3/12/24 10:42, Philippe Mathieu-Daudé wrote:
When testing with a HVF-only binary, we get:
3/12 qemu:func-quick+func-aarch64 / func-aarch64-version
ERROR0.29s exit status 1
stderr:
Traceback (most recent call last):
File "tests
Define the RAM_PRIVATE flag.
In RAMBlock creation functions, if MAP_SHARED is 0 in the flags parameter,
in a subsequent patch the implementation may still create a shared mapping
if other conditions require it. Callers who specifically want a private
mapping, eg for objects specified by the user,
On Tue, Dec 3, 2024 at 12:39 PM Fea.Wang wrote:
>
> The spec explicitly says svukte doesn't support RV32. So check that it
> is not enabled in RV32.
>
> Signed-off-by: Fea.Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 5 +
> 1 file changed, 5 insertions
On 3/12/24 07:46, Bernhard Beschow wrote:
Am 21. November 2024 10:01:52 UTC schrieb "Philippe Mathieu-Daudé"
:
object_dynamic_cast() is expensive; IRQ helpers are certainly
a bad place to call it. Since the device type won't change at
runtime, resolve it once when the AHCI context is initialize
On 12/2/24 17:44, Corvin Köhne wrote:
> On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote:
>> CAUTION: External Email!!
>> A recent commit in i915 driver [1] claims the BDSM register at 0x1080c0
>> of mmio bar0 has been there since gen 6. Mirror this register to the 32
>> bit BDSM register
On Tue, 3 Dec 2024 at 10:19, Daniel P. Berrangé wrote:
> Separatley this from patch, we should also consider whether
> it is time to do the same for aarch64/arm7.
>
> If I look at this page:
>
> https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-socs.html
>
> and sort by 'announced' to see mso
On 03/12/2024 10.21, Philippe Mathieu-Daudé wrote:
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
Update the documentation when KVM is referred to.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/bypass-iommu.txt
On 11/26/24 11:21 AM, Jean-Philippe Brucker wrote:
On Tue, Nov 26, 2024 at 01:45:55PM +, Daniel P. Berrangé wrote:
On Mon, Nov 25, 2024 at 05:23:44PM -0500, Stefan Berger wrote:
On 11/25/24 2:56 PM, Jean-Philippe Brucker wrote:
Create an event log, in the format defined by Trusted Com
On Mon, Dec 02, 2024 at 08:50:55PM +0100, Philippe Mathieu-Daudé wrote:
> Hi,
>
> On 2/12/24 18:05, David Hildenbrand wrote:
> > On 29.11.24 14:55, Daniel P. Berrangé wrote:
> > > See patch 1 for the background info on the problem
> > >
> > > Changed in v2:
> > >
> > > * Add qtest coverage for
On Mon, Dec 02, 2024 at 02:49:33PM -0500, Peter Xu wrote:
> On Sat, Nov 30, 2024 at 10:01:43PM +0800, Yong Huang wrote:
> > On Fri, Nov 29, 2024 at 9:44 PM Fabiano Rosas wrote:
> For the stress.c warnings/error, I saw another one warning with gcc when
> built it locally, then I found Fabiano's CI
On Tue, Dec 03, 2024 at 11:09:14AM +0530, Ani Sinha wrote:
> On Mon, Dec 2, 2024 at 3:02 PM Thomas Huth wrote:
> >
> > On 29/11/2024 18.31, Daniel P. Berrangé wrote:
> > > This removes direct path manipulation to figure out the source dir
> > >
> > > Signed-off-by: Daniel P. Berrangé
> > > ---
>
Hi,
I just realized that I forgot to run the checkpatch script on the
patches again before sending and did not include the Sign-Off. Sorry
about that.
Regards,
Julian Ganz
On Tue, Dec 03, 2024 at 10:21:50AM +0100, Philippe Mathieu-Daudé wrote:
> Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
> options") we prefer the '-accel bar' command line option.
>
> Replace '-machine foo,accel=bar' -> '-machine foo -accel bar' in
> the device-crash-test scrip
On 3/12/24 10:54, Daniel P. Berrangé wrote:
On Tue, Dec 03, 2024 at 10:21:53AM +0100, Philippe Mathieu-Daudé wrote:
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
The new form started to be documented in commit 8d4e914
Hi Andrea,
On 3/12/24 10:47, Andrea Bolognani wrote:
Currently the script won't generate a configuration file that
sets up qemu-user-riscv32 on riscv64, likely under the
assumption that 64-bit RISC-V machines can natively run 32-bit
I'm confused by the "machines" description used for user emul
On Tue, Dec 03, 2024 at 10:38:26AM +0100, Philippe Mathieu-Daudé wrote:
> On 3/12/24 10:26, Philippe Mathieu-Daudé wrote:
> > On 3/12/24 10:18, Daniel P. Berrangé wrote:
> > > On Tue, Dec 03, 2024 at 10:10:35AM +0100, Philippe Mathieu-Daudé wrote:
> > > > When testing with a HVF-only binary, we get
On Tue, Dec 03, 2024 at 10:21:53AM +0100, Philippe Mathieu-Daudé wrote:
> Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
> options") we prefer the '-accel bar' command line option.
>
> The new form started to be documented in commit 8d4e9146b35 ("tcg:
> add options for enabling
On Tue, Dec 03, 2024 at 10:42:32AM +0100, Philippe Mathieu-Daudé wrote:
> When testing with a HVF-only binary, we get:
>
>3/12 qemu:func-quick+func-aarch64 / func-aarch64-version
>ERROR0.29s exit status 1
> stderr:
> Traceback (most rece
Hi all,
Kindly ping😊, any more comments on this version?
Thanks
Zhenzhong
>-Original Message-
>From: Duan, Zhenzhong
>Subject: [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated
>device
>
>Hi,
>
>Per Jason Wang's suggestion, iommufd nesting series[1] is split into
>"E
On Tue, Dec 3, 2024 at 2:20 PM Thomas Huth wrote:
>
> On 03/12/2024 09.11, Daniel P. Berrangé wrote:
> > On Tue, Dec 03, 2024 at 11:09:14AM +0530, Ani Sinha wrote:
> >> On Mon, Dec 2, 2024 at 3:02 PM Thomas Huth wrote:
> >>>
> >>> On 29/11/2024 18.31, Daniel P. Berrangé wrote:
> This removes
When testing with a HVF-only binary, we get:
3/12 qemu:func-quick+func-aarch64 / func-aarch64-version
ERROR0.29s exit status 1
stderr:
Traceback (most recent call last):
File "tests/functional/test_version.py", line 22, in
test_qmp_hu
When testing with a HVF-only binary, we get:
3/12 qemu:func-quick+func-aarch64 / func-aarch64-empty_cpu_model
ERROR0.62s exit status 1
stderr:
Traceback (most recent call last):
File "tests/functional/test_empty_cpu_model.py", line 21, in test
Explicit the QTest accelerator to have these 2 tests
pass on macOS when only HVF is built in.
v2: Use -accel (Thomas)
Philippe Mathieu-Daudé (2):
tests/functional/test_version: Use QTest accelerator
tests/functional/test_empty_cpu_model: Use QTest accelerator
tests/functional/test_empty_cpu
Thomas told '-machine foo,accel=bar' is sugar and almost
deprecated. Rather than having bad examples in the tree,
remove the legacy form and update to the new '-accel bar'
one.
Xen uses via MachineClass::default_machine_opts left for later:
hw/i386/pc_piix.c:818:m->default_machine_opts =
"ac
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
Update the documentation when KVM is referred to.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/bypass-iommu.txt| 3 ++-
docs/nvdimm.txt | 2
On Tue, Dec 03, 2024 at 10:10:35AM +0100, Philippe Mathieu-Daudé wrote:
> When testing with a HVF-only binary, we get:
>
>3/12 qemu:func-quick+func-aarch64 / func-aarch64-version
>ERROR0.29s exit status 1
> stderr:
> Traceback (most rece
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
Replace '-machine foo,accel=bar' -> '-machine foo -accel bar' in
fuzzer scripts and tests.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/fuzz/generic_fuzz.c
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
The new form started to be documented in commit 8d4e9146b35 ("tcg:
add options for enabling MTTCG"); it is safe to remove the mentions
of the legacy option.
Signed-off-by: P
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
Replace '-machine foo,accel=bar' -> '-machine foo -accel bar' in
functional tests.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_virtio_gpu.py | 6 --
Since commit 6f6e1698a68 ("vl: configure accelerators from -accel
options") we prefer the '-accel bar' command line option.
Replace '-machine foo,accel=bar' -> '-machine foo -accel bar' in
functional tests.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_ppc64_hv.py | 3 ++-
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