Re: [PATCH v4 1/6] hw/loongarch/virt: Add CPU topology support

2024-11-19 Thread bibo mao
On 2024/11/19 上午12:22, Igor Mammedov wrote: On Mon, 18 Nov 2024 17:10:29 +0100 Igor Mammedov wrote: On Tue, 12 Nov 2024 10:17:33 +0800 Bibo Mao wrote: Add topological relationships for Loongarch VCPU and initialize topology member variables. Also physical cpu id calculation method comes

Re: [PATCH 1/7] docs/devel: remove dead video link for sourcehut submit process

2024-11-19 Thread Thomas Huth
On 18/11/2024 18.23, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- docs/devel/submitting-a-patch.rst | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitting-a-patch.rst index 83e9092b8c0..349c32ee3a9 1006

Re: [PATCH 2/7] docs/devel: add git-publish for patch submitting

2024-11-19 Thread Marcin Juszkiewicz
W dniu 18.11.2024 o 18:23, Pierrick Bouvier pisze: Signed-off-by: Pierrick Bouvier --- docs/devel/submitting-a-patch.rst | 14 ++ 1 file changed, 14 insertions(+) diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitting-a-patch.rst index 349c32ee3a9..953682f20cb 10

Re: [PATCH 3/7] docs/devel: add b4 for patch retrieval

2024-11-19 Thread Marcin Juszkiewicz
W dniu 19.11.2024 o 10:14, Daniel P. Berrangé pisze: +b4 shazam $msg-id I'm wondering how b4 knows where to find the mails for $msg-id for QEMU ? It goes for https://lore.kernel.org/qemu-devel/$msg-id by default or checks b4.midmask in git config.

Re: [PATCH v4 3/6] hw/loongarch/virt: Add generic function to init interrupt pin of CPU

2024-11-19 Thread bibo mao
On 2024/11/19 上午12:43, Igor Mammedov wrote: On Tue, 12 Nov 2024 10:17:35 +0800 Bibo Mao wrote: Here generic function virt_init_cpu_irq() is added to init interrupt pin of CPU object, IPI and extioi interrupt controllers are connected to interrupt pin of CPU object. The generic function can

Re: [PATCH v4 5/6] hw/loongarch/virt: Update the ACPI table for hotplug cpu

2024-11-19 Thread bibo mao
On 2024/11/19 上午12:51, Igor Mammedov wrote: On Tue, 12 Nov 2024 10:17:37 +0800 Bibo Mao wrote: On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug handler, here CPU hotplug support feature is added based on GED handler, also CPU scan and reject method is added about CPU dev

Re: [PATCH 3/7] docs/devel: add b4 for patch retrieval

2024-11-19 Thread Daniel P . Berrangé
On Tue, Nov 19, 2024 at 10:56:36AM +0100, Marcin Juszkiewicz wrote: > W dniu 19.11.2024 o 10:14, Daniel P. Berrangé pisze: > > > > +b4 shazam $msg-id > > > > I'm wondering how b4 knows where to find the mails for $msg-id for QEMU ? > > It goes for https://lore.kernel.org/qemu-devel/$msg-id

[PATCH] docs: aspeed: Reorganize the "Boot options" section

2024-11-19 Thread Cédric Le Goater
Add subsubsections for possible boot methods and introduce a new section on eMMC boot support for the ast2600-evb and rainier-emmc machines, boot partitions assumptions and limitations. Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 99 +- 1

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Paolo Bonzini
Il mar 19 nov 2024, 00:06 Peter Xu ha scritto: > On Mon, Nov 18, 2024 at 05:13:30PM -0500, Peter Xu wrote: > > When used incorrectly, container_get() can silently create containers > even > > if the caller may not intend to do so. Add a rich document describing > the > > helper, as container_get

Re: [PATCH v4 1/6] hw/loongarch/virt: Add CPU topology support

2024-11-19 Thread bibo mao
Hi Ignor, On 2024/11/19 上午12:10, Igor Mammedov wrote: On Tue, 12 Nov 2024 10:17:33 +0800 Bibo Mao wrote: Add topological relationships for Loongarch VCPU and initialize topology member variables. Also physical cpu id calculation method comes from its topo information. Co-developed-by: Xian

Re: Status of some Arm features

2024-11-19 Thread Peter Maydell
On Tue, 19 Nov 2024 at 10:09, Peter Maydell wrote: > > On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier wrote: > > 8.4: > > - FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c) > > This is optional, and we don't implement it yet. (There's an > open ticket for it in Linaro JIRA at > https:/

Re: [PATCH 4/7] docs/devel: add information on how to setup build environments

2024-11-19 Thread Alex Bennée
Daniel P. Berrangé writes: > On Mon, Nov 18, 2024 at 09:23:54AM -0800, Pierrick Bouvier wrote: >> MacOS and Linux are straightforward, but Windows needs a bit more >> details. >> >> Signed-off-by: Pierrick Bouvier >> --- >> docs/about/build-platforms.rst | 4 +- >> docs/devel/build-environ

Re: [PATCH 4/7] docs/devel: add information on how to setup build environments

2024-11-19 Thread Daniel P . Berrangé
On Tue, Nov 19, 2024 at 11:08:12AM +, Alex Bennée wrote: > Daniel P. Berrangé writes: > > > On Mon, Nov 18, 2024 at 09:23:54AM -0800, Pierrick Bouvier wrote: > >> MacOS and Linux are straightforward, but Windows needs a bit more > >> details. > >> > >> Signed-off-by: Pierrick Bouvier > >> -

Re: [PULL 0/8] Block layer patches

2024-11-19 Thread Kevin Wolf
Am 15.11.2024 um 21:16 hat Peter Maydell geschrieben: > On Thu, 14 Nov 2024 at 16:58, Kevin Wolf wrote: > > > > The following changes since commit f0a5a31c33a8109061c2493e475c8a2f4d022432: > > > > Update version for v9.2.0-rc0 release (2024-11-13 21:44:45 +) > > > > are available in the Git

Re: [PATCH v5 1/9] target/riscv: fix henvcfg potentially containing stale bits

2024-11-19 Thread Clément Léger
On 19/11/2024 05:16, Alistair Francis wrote: > On Thu, Nov 14, 2024 at 7:14 PM Clément Léger wrote: >> >> With the current implementation, if we had the current scenario: >> - set bit x in menvcfg >> - set bit x in henvcfg >> - clear bit x in menvcfg >> then, the internal variable env->henvcfg

[PATCH v2 0/3] scripts: mandate use of SPDX-License-Identifier tags in new files

2024-11-19 Thread Daniel P . Berrangé
One of the items raised at the QEMU maintainers meeting at KVM Forum 2024 was adoption of SPDX-License-Identifier for licensing of newly contributed source files, for which there were no dissenting voices. Thus, this series proposes a way to put this into action by extending checkpatch.pl to manda

Re: Status of some Arm features

2024-11-19 Thread Peter Maydell
On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier wrote: > I'm currently reviewing the QEMU Arm documentation, and I have a > question about the status of following features: > > 8.0: > - FEAT_DoubleLock, Double Lock This is actually an "anti-feature" :-) It is optional from v8.0 and it must not be

Re: [PATCH 3/5] qdev: Make device_set_realized() always safe in tests

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 05:13:28PM -0500, Peter Xu wrote: > Currently, a device can be realized even before machine is created, but > only in one of QEMU's qtest, test-global-qdev-props.c. > > Right now, the test_static_prop_subprocess() test (which creates one simple > object without machine crea

Re: [PULL 00/12] s390x and misc patches for QEMU 9.2-rc1

2024-11-19 Thread Peter Maydell
On Mon, 18 Nov 2024 at 17:36, Thomas Huth wrote: > > Hi Peter! > > The following changes since commit abb1565d3d863cf210f18f70c4a42b0f39b8ccdb: > > Merge tag 'pull-tcg-20241116' of https://gitlab.com/rth7680/qemu into > staging (2024-11-16 18:16:46 +) > > are available in the Git repositor

Re: [PULL for -rc1 0/1] NBD patches for 2024-11-18

2024-11-19 Thread Peter Maydell
On Mon, 18 Nov 2024 at 19:38, Eric Blake wrote: > > The following changes since commit abb1565d3d863cf210f18f70c4a42b0f39b8ccdb: > > Merge tag 'pull-tcg-20241116' of https://gitlab.com/rth7680/qemu into > staging (2024-11-16 18:16:46 +) > > are available in the Git repository at: > > http

Re: [PATCH v4 6/6] hw/loongarch/virt: Enable cpu hotplug feature on virt machine

2024-11-19 Thread bibo mao
On 2024/11/19 上午1:03, Igor Mammedov wrote: On Tue, 12 Nov 2024 10:17:38 +0800 Bibo Mao wrote: On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs, there is socket-id/core-id/thread-id property set, arch_id can be caculated from these properties. So that cpu

Re: [PATCH 7/7] docs: add a how to section

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 09:23:57AM -0800, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier > --- > docs/devel/build-system.rst | 2 + > docs/how-to/index.rst | 146 > docs/index.rst | 1 + > 3 files changed, 149 insertions(+) >

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 05:13:30PM -0500, Peter Xu wrote: > When used incorrectly, container_get() can silently create containers even > if the caller may not intend to do so. Add a rich document describing the > helper, as container_get() should only be used in path lookups. > > Add one object_d

Re: [PATCH 3/7] docs/devel: add b4 for patch retrieval

2024-11-19 Thread Marcin Juszkiewicz
W dniu 19.11.2024 o 11:07, Daniel P. Berrangé pisze: On Tue, Nov 19, 2024 at 10:56:36AM +0100, Marcin Juszkiewicz wrote: W dniu 19.11.2024 o 10:14, Daniel P. Berrangé pisze: +b4 shazam $msg-id I'm wondering how b4 knows where to find the mails for $msg-id for QEMU ? It goes for https:

Re: [PATCH] hw/aspeed: Correct minimum access size for all models

2024-11-19 Thread Peter Maydell
On Tue, 19 Nov 2024 at 02:53, Joel Stanley wrote: > > On Mon, 18 Nov 2024 at 20:40, Peter Maydell wrote: > > Have you reviewed all the device read/write function > > implementations for these devices to check whether > > (a) changing the .valid value does the right thing, or > > I read the implem

Re: [PATCH 2/7] docs/devel: add git-publish for patch submitting

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 09:23:52AM -0800, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier > --- > docs/devel/submitting-a-patch.rst | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git a/docs/devel/submitting-a-patch.rst > b/docs/devel/submitting-a-patch.rst > index

Re: [PATCH 3/7] docs/devel: add b4 for patch retrieval

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 09:23:53AM -0800, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier > --- > docs/devel/submitting-a-patch.rst | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/docs/devel/submitting-a-patch.rst > b/docs/devel/submitting-a-patch.rst > index 9536

RE: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

2024-11-19 Thread Duan, Zhenzhong
Clear, will use "x-flts is only available in scalable mode". Thanks Clement. From: CLEMENT MATHIEU--DRIF Sent: Tuesday, November 19, 2024 5:00 PM To: Duan, Zhenzhong ; qemu-devel@nongnu.org Cc: alex.william...@redhat.com; c...@redhat.com; eric.au...@redhat.com; m...@redhat.com; pet...@redhat.com

Re: nested-smmuv3 topic for QEMU/libvirt, Nov 2024

2024-11-19 Thread Eric Auger
Hi Zhenzhong, On 11/19/24 08:07, Duan, Zhenzhong wrote: > Hi Eric, > >> -Original Message- >> From: Eric Auger >> Sent: Tuesday, November 19, 2024 2:00 AM >> Subject: Re: nested-smmuv3 topic for QEMU/libvirt, Nov 2024 >> >> Hi Nicolin, >> >> On 11/7/24 21:31, Nicolin Chen wrote: >>> Hi Er

Re: [PATCH 4/7] docs/devel: add information on how to setup build environments

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 09:23:54AM -0800, Pierrick Bouvier wrote: > MacOS and Linux are straightforward, but Windows needs a bit more > details. > > Signed-off-by: Pierrick Bouvier > --- > docs/about/build-platforms.rst | 4 +- > docs/devel/build-environment.rst | 114 +++

Re: [PATCH 1/5] qom: Add TYPE_CONTAINER macro

2024-11-19 Thread Daniel P . Berrangé
On Mon, Nov 18, 2024 at 05:13:26PM -0500, Peter Xu wrote: > Provide a macro for the container type across QEMU source tree, rather than > hard code it every time. > > Signed-off-by: Peter Xu > --- > include/qom/object.h | 3 ++- > hw/arm/stellaris.c | 2 +- > qom/container.c | 4 ++-- > q

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

2024-11-19 Thread CLEMENT MATHIEU--DRIF
On 19/11/2024 08:28, Duan, Zhenzhong wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Hi Clement, -Original Message- From: CLEMENT MATHIEU--DRIF

[PATCH] ppc/spapr: fix drc index mismatch for partially enabled vcpus

2024-11-19 Thread Harsh Prateek Bora
In case when vcpus are explicitly enabled/disabled in a non-consecutive order within a libvirt xml, it results in a drc index mismatch during vcpu hotplug later because the existing logic uses vcpu id to derive the corresponding drc index which is not correct. Use env->core_index to derive a vcpu's

[PATCH] qdev: Fix set_pci_devfn() to visit option only once

2024-11-19 Thread Kevin Wolf
pci_devfn properties accept either a string or an integer as input. To implement this, set_pci_devfn() first tries to visit the option as a string, and if that fails, it visits it as an integer instead. While the QemuOpts visitor happens to accept this, it is invalid according to the visitor interf

Re: [PATCH 2/7] docs/devel: add git-publish for patch submitting

2024-11-19 Thread Daniel P . Berrangé
On Tue, Nov 19, 2024 at 09:41:40AM +0100, Marcin Juszkiewicz wrote: > W dniu 18.11.2024 o 18:23, Pierrick Bouvier pisze: > > Signed-off-by: Pierrick Bouvier > > --- > > docs/devel/submitting-a-patch.rst | 14 ++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/docs/devel/s

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 02:50:40PM -0500, Steven Sistare wrote: > On 11/14/2024 2:04 PM, Peter Xu wrote: > > On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote: > > > On 11/13/2024 4:58 PM, Peter Xu wrote: > > > > On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: > > > > >

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Steven Sistare
On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: This begs the question, should we allow channels to be specified in hmp migrate commands and for -incoming, in a very simple way? Like with a prefix naming the channel. And eliminate the -cpr

Re: [PATCH 1/5] qom: Add TYPE_CONTAINER macro

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 09:42:45AM +, Daniel P. Berrangé wrote: > > -#define TYPE_OBJECT "object" > > +#define TYPE_OBJECT "object" > > +#define TYPE_CONTAINER "container" > > nitpick - 1 space too many before "TYPE_", and it is not worth > trying to vertically a

[PULL 14/15] target/arm/hvf: Add trace.h header

2024-11-19 Thread Peter Maydell
The documentation for trace events says that every subdirectory which has trace events should have a trace.h header, whose only content is an include of the trace/trace-.h file. When we added the trace events in target/arm/hvf/ we forgot to create this file and instead hvf.c directly includes trac

Re: [PULL 00/15] target-arm queue

2024-11-19 Thread Peter Maydell
Merge tag 'pull-nbd-2024-11-18' of https://repo.or.cz/qemu/ericb into > staging (2024-11-18 20:24:05 +) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20241119 > > for you

[PULL 07/15] tests/qtest/cmsdk-apb-watchdog-test: Test INTEN as counter enable

2024-11-19 Thread Peter Maydell
From: Roque Arcudia Hernandez The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchdog/programmers-model The new tests have t

[PULL 12/15] hw/intc/loongarch_extioi: Use set_bit32() and clear_bit32() for s->isr

2024-11-19 Thread Peter Maydell
In extioi_setirq() we try to operate on a bit array stored as an array of uint32_t using the set_bit() and clear_bit() functions by casting the pointer to 'unsigned long *'. This has two problems: * the alignment of 'uint32_t' is less than that of 'unsigned long' so we pass an insufficiently al

[PATCH 02/15] tests/functional: automatically clean up scratch files after tests

2024-11-19 Thread Daniel P . Berrangé
The build/tests/functional subdirectories are consuming huge amounts of disk space. Split the location for scratch files into a 'scratch' sub-directory, separate from log files, and delete it upon completion of each test. The new env variable QEMU_TEST_KEEP_SCRATCH can be set to preserve this scra

Re: [PATCH 01/15] tests/functional: fix mips64el test to honour workdir

2024-11-19 Thread Philippe Mathieu-Daudé
On 19/11/24 16:05, Daniel P. Berrangé wrote: The missing directory separator resulted in the kernel file being created 1 level higher than expected. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_mips64el_malta.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH 02/15] tests/functional: automatically clean up scratch files after tests

2024-11-19 Thread Thomas Huth
On 19/11/2024 17.21, Alex Bennée wrote: Daniel P. Berrangé writes: The build/tests/functional subdirectories are consuming huge amounts of disk space. Split the location for scratch files into a 'scratch' sub-directory, separate from log files, and delete it upon completion of each test. The

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Paolo Bonzini
Il mar 19 nov 2024, 21:07 Peter Xu ha scritto: > > Ah, that was supposed to be the difference between type_register() and > > type_register_static(). > > Ah... looks like they're the same now? As type_register_static() looks like > a wrapper of type_register(). > And pretty much have always been

Re: [PATCH v7 00/12] Use Intel DSA accelerator to offload zero page checking in multifd live migration.

2024-11-19 Thread Fabiano Rosas
Yichen Wang writes: > v7 > * Rebase on top of f0a5a31c33a8109061c2493e475c8a2f4d022432; > * Fix a bug that will crash QEMU when DSA initialization failed; > * Use a more generalized accel-path to support other accelerators; > * Remove multifd-packet-size in the parameter list; > > v6 > * Rebase o

[PATCH] scsi: fix allocation for s390x loadparm

2024-11-19 Thread Paolo Bonzini
Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in this case the string *does* have to be NUL-termin

[PATCH for-10.0 v2 2/8] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage

2024-11-19 Thread Daniel Henrique Barboza
In create_fdt_sockets() we have the following pattern: if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do stuff ...) } else { (... do other stuff ...) } if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do more stuff ...) } else { (... do more ot

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 04:41:07PM -0500, Steven Sistare wrote: > On 11/19/2024 4:29 PM, Peter Xu wrote: > > On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: > > > On 11/19/2024 3:51 PM, Peter Xu wrote: > > > > On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: > > > > >

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Steven Sistare
On 11/19/2024 4:48 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:41:07PM -0500, Steven Sistare wrote: On 11/19/2024 4:29 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven

Re: [PATCH 09/15] tests/functional: put QEMUMachine logs in testcase log directory

2024-11-19 Thread Alex Bennée
Daniel P. Berrangé writes: > We are not passing the 'log_dir' parameter to QEMUMachine, so the > QEMU stdout/err logs are being placed in a temp directory and thus > deleted after execution. This makes them inaccessible as gitlab > CI artifacts. > > Pass the testcase log directory path into QEMUM

[PATCH for-10.0 v2 8/8] docs: update riscv/virt.rst with kernel-irqchip=split support

2024-11-19 Thread Daniel Henrique Barboza
Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst

[PATCH for-10.0 v2 0/8] riscv: AIA userspace irqchip_split support

2024-11-19 Thread Daniel Henrique Barboza
Hi, This second version was rebased with 'master'. Alistair's acks were included. No other changes were made. All patches acked/reviewed. Changes from v1: - rebased with master @ af4c4fd128 - v1 link: https://lore.kernel.org/qemu-riscv/20241010190337.376987-1-dbarb...@ventanamicro.com/ Daniel

[PATCH for-10.0 v2 7/8] target/riscv/kvm: remove irqchip_split() restriction

2024-11-19 Thread Daniel Henrique Barboza
Remove the 'irqchip_split()' restriction in kvm_arch_init() now that we have support for "-accel kvm,kernel-irqchip=split". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv/kv

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 09:09:16AM +0100, Paolo Bonzini wrote: > Il mar 19 nov 2024, 00:06 Peter Xu ha scritto: > > > On Mon, Nov 18, 2024 at 05:13:30PM -0500, Peter Xu wrote: > > > When used incorrectly, container_get() can silently create containers > > even > > > if the caller may not intend t

[PATCH for-10.0 v2 1/8] hw/intc/riscv_aplic: rename is_kvm_aia()

2024-11-19 Thread Daniel Henrique Barboza
The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Make the helper public because the

[PATCH for-10.0 v2 6/8] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic

2024-11-19 Thread Daniel Henrique Barboza
The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and

[PATCH for-10.0 v2 5/8] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers

2024-11-19 Thread Daniel Henrique Barboza
The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_use_kvm_aia_aplic_imsic(). This

Re: [PATCH 0/8] riscv: AIA userspace irqchip_split support

2024-11-19 Thread Daniel Henrique Barboza
On 11/17/24 11:05 PM, Alistair Francis wrote: On Fri, Oct 11, 2024 at 5:04 AM Daniel Henrique Barboza wrote: Hi, This series adds AIA irqchip_split support, effective when using AIA with aia=aplic-imsic and -accel kvm,kernel-irqchip=split. The main difference between what we currently hav

[PATCH for-10.0 v2 3/8] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()

2024-11-19 Thread Daniel Henrique Barboza
Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c, the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with in-kernel irqchip enabled. It is not checking for a generic AIA support. Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the helper i

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 10:03:22AM +, Daniel P. Berrangé wrote: > The docs are a welcome addition, but at the same time the docs won't get > read most of the time. > > With this in mind, IMHO, it is a conceptually *terrible* design for us to > have a method called "get" which magically *create

[PATCH] Added support for WACOM 2.x/ArtZ/Digitizer II compatibility. It does require the driver (easily available via many of the classic macos archives), but it allows a simple way to have an absolut

2024-11-19 Thread Patrick Eads
From: Patrick Eads init Promising polling initiated and data moving cursor now Reverted delete of dev handler for wacom tablet got the y-axis! getting closer more progress. it appears to not quite be WACOM II/IV, but x-axis is controlled by the first 2-3 bytes really? 12-bits is the key? o

[PULL 01/15] hw/timer/exynos4210_mct: fix possible int overflow

2024-11-19 Thread Peter Maydell
From: Dmitry Frolov The product "icnto * s->tcntb" may overflow uint32_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Frolov Message-id: 20241106083801.219578-2-fro...@swemel.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/

Re: [PATCH 07/15] tests/functional: remove comments talking about avocado

2024-11-19 Thread Thomas Huth
On 19/11/2024 16.05, Daniel P. Berrangé wrote: The first comment is still relevant but should talk about our own test harness instead. The second comment adds no value over reading the code and can be removed. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_acpi_bits.py | 12 +

Re: [PATCH] hvf: remove unused but set variable

2024-11-19 Thread Paolo Bonzini
Queued, thanks. Paolo

Re: [PATCH 10/15] tests/functional: honour requested test VM name in QEMUMachine

2024-11-19 Thread Thomas Huth
On 19/11/2024 16.05, Daniel P. Berrangé wrote: The functional test case class is going to the trouble of passing around a machine name, but then fails to give this QEMUMachine. As a result, QEMUMachine will create a completely random name. Since log file names match the machine name, this results

Re: [PATCH 03/15] tests/functional: remove "AVOCADO" from env variable name

2024-11-19 Thread Alex Bennée
Daniel P. Berrangé writes: > This env variable is a debugging flag to save screendumps in the > mips64el malta tests. > > Signed-off-by: Daniel P. Berrangé Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PULL for 9.2 0/4] updates (virtio-gpu, gdbstub testing, MAINTAINERS)

2024-11-19 Thread Peter Maydell
On Mon, 18 Nov 2024 at 20:42, Alex Bennée wrote: > > The following changes since commit 0fbc798e4f51d6d2bc05f4965b0eae74ba204471: > > Merge tag 'pull-vfio-20241118' of https://github.com/legoater/qemu into > staging (2024-11-18 10:04:04 +) > > are available in the Git repository at: > > h

[RFC PATCH] docs: Add roadmap for heterogeneous emulation

2024-11-19 Thread Philippe Mathieu-Daudé
This document tries to document the steps required to: - Have a single binary to run system emulations - Emulate different architectures in the same process - Have QEMU assemble dynamic machines at runtime Signed-off-by: Philippe Mathieu-Daudé --- This is the document that was discussed at th

[PATCH v2 1/3] scripts: mandate that new files have SPDX-License-Identifier

2024-11-19 Thread Daniel P . Berrangé
Going forward we want all newly created source files to have an SPDX-License-Identifier tag present. Initially mandate this for C, Python, Perl, Shell source files, as well as JSON (QAPI) and Makefiles, while encouraging users to consider it for other file types. Reviewed-by: Brian Cain Reviewed

Re: [PULL v2 0/8] Block layer patches

2024-11-19 Thread Peter Maydell
On Tue, 19 Nov 2024 at 17:28, Kevin Wolf wrote: > > The following changes since commit e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679: > > Merge tag 'pull-target-arm-20241119' of > https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-11-19 > 14:23:34 +00

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Steven Sistare
On 11/14/2024 2:04 PM, Peter Xu wrote: On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote: On 11/13/2024 4:58 PM, Peter Xu wrote: On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: Add the cpr-transfer migration mode. Usage: qemu-system-$arch -machine anon-alloc=me

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: > On 11/19/2024 3:51 PM, Peter Xu wrote: > > On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: > > > This begs the question, should we allow channels to be specified in hmp > > > migrate > > > commands and for -incoming,

[PATCH] linux-user: Fix strace output for s390x mmap()

2024-11-19 Thread Ilya Leoshkevich
print_mmap() assumes that mmap() receives arguments via memory if mmap2() is present. s390x (as opposed to s390) does not fit this pattern: it does not have mmap2(), but mmap() still receives arguments via memory. Fix by special-casing s390x. Cc: qemu-sta...@nongnu.org Fixes: d971040c2d16 ("linux

Re: [PATCH V3 11/16] migration: cpr-transfer mode

2024-11-19 Thread Steven Sistare
On 11/19/2024 4:29 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: This begs the question, should we allow channels to be specified in hmp migrate commands

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 09:30:09PM +0100, Paolo Bonzini wrote: > > > > Do we have known places that we care a lot on object[_class]_dynamic_cast() > > performance? > > The easiest way to check is probably to print the type of every successful > object_dynamic_cast and object_class_dynamic_cast. I

Re: [PATCH 3/5] qdev: Make device_set_realized() always safe in tests

2024-11-19 Thread Peter Xu
On Tue, Nov 19, 2024 at 09:46:35AM +, Daniel P. Berrangé wrote: > On Mon, Nov 18, 2024 at 05:13:28PM -0500, Peter Xu wrote: > > Currently, a device can be realized even before machine is created, but > > only in one of QEMU's qtest, test-global-qdev-props.c. > > > > Right now, the test_static_

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

2024-11-19 Thread Frank Chang
On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis wrote: > On Mon, Oct 21, 2024 at 1:06 PM wrote: > > > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the > property > >

[PATCH v4 5/6] target/riscv: Expose svukte ISA extension

2024-11-19 Thread Fea.Wang
Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f

[PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

2024-11-19 Thread Fea.Wang
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Revie

Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension

2024-11-19 Thread Fea Wang
OK, I will add a new commit for checking the extension in RV32. Thank you. Sincerely, Fea On Tue, Nov 19, 2024 at 11:34 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote: > > > > Add "svukte" in the ISA string when svukte extension is enabled. > > > > Signed-off-by: F

Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule

2024-11-19 Thread Fea Wang
Thanks for the advice. I will fix them in the next patch version. Sincerely, Fea On Tue, Nov 19, 2024 at 11:33 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote: > > > > Follow the Svukte spec, do the memory access address checking > > > > 1. Include instruction fetch

[RFC PATCH v6 0/2] Support RISC-V CSR read/write in Qtest environment

2024-11-19 Thread Ivan Klokov
These patches add functionality for unit testing RISC-V-specific registers. The first patch adds a Qtest backend, and the second implements a simple test. --- v7: - Fix build errors, add Reviewed-by, Acked-by. --- Ivan Klokov (2): target/riscv: Add RISC-V CSR qtest support tests/qtest: QTe

[PATCH] hw/i386/amd_iommu: Allow migration

2024-11-19 Thread Suravee Suthikulpanit
Add migration support for AMD IOMMU model by saving necessary AMDVIState parameters for MMIO registers, device table, command buffer, and event buffers. Signed-off-by: Suravee Suthikulpanit --- hw/i386/amd_iommu.c | 36 +++- 1 file changed, 35 insertions(+), 1 del

[PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

2024-11-19 Thread Fea.Wang
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be supported when the svukte extension is enabled. When senvcfg[UKTE] bit is set, the memory access from U-mode should do the svukte check only except HLV/HLVX/HSV H-mode instructions which depend on hstatus[HUKTE]. Signed-off-by:

[PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32

2024-11-19 Thread Fea.Wang
Based on the spec, svukte depends on SV39, so it should not be enabled in RV32. Signed-off-by: Fea.Wang --- target/riscv/tcg/tcg-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..4273f1f472 100644 --- a/target

[PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule

2024-11-19 Thread Fea.Wang
Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX, HSV and execute from U mode to VU mode 4.

[PATCH v4 1/6] target/riscv: Add svukte extension capability variable

2024-11-19 Thread Fea.Wang
Refer to the draft of svukte extension from: https://github.com/riscv/riscv-isa-manual/pull/1564 Svukte provides a means to make user-mode accesses to supervisor memory raise page faults in constant time, mitigating attacks that attempt to discover the supervisor software's address-space layout.

[PATCH v4 0/6] Introduce svukte ISA extension

2024-11-19 Thread Fea.Wang
The Svukte ISA extension has been approved for fast-track development. https://lf-riscv.atlassian.net/browse/RVS-2977 And there are Linux patches for the Svukte that are under review. https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-rebase-v1-0-7864a88a6...@sifive.com/T/#mf70fcb22cd2987ad268c0

[PATCH v2 2/2] chardev/char-mux: make boolean bit check instead of find_next_bit()

2024-11-19 Thread Roman Penyaev
This patch simplifies (and makes less confusing) bit checks by replacing `find_next_bit()` calls with boolean AND operation. Resolves: Coverity CID 1563776 Signed-off-by: Roman Penyaev Reviewed-by: "Marc-André Lureau" Cc: Peter Maydell Reviewed-by: Clément Mathieu--Drif Cc: qemu-devel@nongnu.o

[PATCH v2 1/2] chardev/char-mux: shift unsigned long to avoid 32-bit overflow

2024-11-19 Thread Roman Penyaev
Allthough the size of MAX_MUX is equal to 4 and likely will never change, this patch changes type of constant to unsigned long to be on the safe side. Also add a static compile check that MAX_MUX never bigger than `sizeof(d->mux_bitset)`. Signed-off-by: Roman Penyaev Reviewed-by: "Marc-André Lur

[PATCH v2 0/2] chardev/char-mux: tweak mux bitset operations

2024-11-19 Thread Roman Penyaev
Patchset tweaks bitset operations by changing a constant to unsigned long, introduces a static compile check and simplifies bitset operations. v1..v2: Rebase on latest master, incorporate review tags. Roman Penyaev (2): chardev/char-mux: shift unsigned long to avoid 32-bit overflow chardev/c

[PATCH v4] hw/riscv: Add Microblaze V generic board

2024-11-19 Thread Sai Pavan Boddu
Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial configuration is going bey

[PATCH 06/15] tests/functional: remove obsolete reference to avocado bug

2024-11-19 Thread Daniel P . Berrangé
Historical bugs in avocado related to zstd support are not relevant to the code now that it uses QEMU's native test harness. Signed-off-by: Daniel P. Berrangé --- tests/functional/qemu_test/tuxruntest.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/functional/qemu_test/tuxruntest.py

Re: [PATCH] scsi: fix allocation for s390x loadparm

2024-11-19 Thread Jared Rossi
On 11/19/24 4:31 PM, Paolo Bonzini wrote: Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in thi

Re: [PATCH 13/15] tests/functional: rewrite console handling to be bytewise

2024-11-19 Thread Paolo Bonzini
On 11/19/24 19:54, Daniel P. Berrangé wrote: +if success is None or success in msg: As an optimization, you could use msg.endswith(success) and msg.endswith(failure), which would avoid the most blatant cases of O(n^2) behavior. More important, I think "if success is None" should not be

[PULL 5/5] scsi: fix allocation for s390x loadparm

2024-11-19 Thread Paolo Bonzini
Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in this case the string *does* have to be NUL-termin

[PULL 1/5] hw/i386/pc: Remove vmport value assertion

2024-11-19 Thread Paolo Bonzini
From: Kamil Szczęk There is no need for this assertion here, as we only use vmport value for equality/inequality checks. This was originally prompted by the following Coverity report: >>> CID 1559533: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "pcms->vmport >= 0" is always true r

[PULL 2/5] hvf: remove unused but set variable

2024-11-19 Thread Paolo Bonzini
From: Pierrick Bouvier fixes associated warning when building on MacOS. Signed-off-by: Pierrick Bouvier Link: https://lore.kernel.org/r/20241023182922.1040964-1-pierrick.bouv...@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86_task.c | 10 +- 1 file changed, 5 insertio

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