On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier <pierrick.bouv...@linaro.org> wrote: > I'm currently reviewing the QEMU Arm documentation, and I have a > question about the status of following features: > > 8.0: > - FEAT_DoubleLock, Double Lock
This is actually an "anti-feature" :-) It is optional from v8.0 and it must not be implemented from v9.0. We implement the handling of it based on the DOUBLELOCK fields in ID_AA64DFR0 and DBGDEVID (so it does the right thing on older named CPU types) and don't advertise it in "max". > 8.2: > - FEAT_ASMv8p2, Armv8.2 changes to the A64 ISA (bfc and rev64 instructions) This isn't a feature for CPU implementations; it's a feature for assemblers and disassemblers, which have to recognize BFC and REV64 mnemonics as being ways to write special-case flavours of the BFM and REV instructions. > 8.4: > - FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c) This is optional, and we don't implement it yet. (There's an open ticket for it in Linaro JIRA at https://linaro.atlassian.net/browse/QEMU-309 ) thanks -- PMM
