[RESEND PATCH 00/10] usb/uhci: Add UHCI sysbus support, and enable for AST machines

[ Trying again, with updated subject ] Some machines (like Aspeed ARM) only support a sysbus UHCI controller. The current UHCI implementation in qemu only supports PCI based UHCI controllers. This patch series separates basic and PCI functionality from the hcd-uhci implementation and then adds uh

[RESEND PATCH 10/10] usb-hub: Fix handling port power control messages

The ClearPortFeature control message fails for PORT_POWER because there is no break; at the end of the case statement, causing it to fall through to the failure handler. Add the missing break; to solve the problem. Signed-off-by: Guenter Roeck --- Change from RFC: New patch hw/usb/dev-hub.c

[RFC PATCH 06/14] s390x/cpumodel: add Concurrent-functions facility support

The Concurrent-functions facility introduces the new instruction Perform Functions with Concurrent Results (PFCR) with few subfunctions. Signed-off-by: Hendrik Brueckner --- linux-headers/asm-s390/kvm.h| 3 ++- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features.h

Re: [edk2-devel] [RFC PATCH v2 1/1] hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW

W dniu 7.11.2024 o 13:04, Jonathan Cameron pisze: On Tue, 5 Nov 2024 18:43:46 +0800 "Yuquan Wang" wrote: This creates a default pxb-cxl (bus_nr=0xc0) bridge with two cxl root ports on sbsa-ref. And the memory layout places 64K space for the cxl host bridge register regions(CHBCR) in the sbsa-r

Ping: [PATCH v2] tests/tcg: Stop using exit() in the gdbstub testcases

On Tue, 2024-10-22 at 13:37 +0200, Ilya Leoshkevich wrote: > GDB 15 does not like exit() anymore: > >     (gdb) python exit(0) >     Python Exception : 0 >     Error occurred in Python: 0 > > Use the GDB's own exit command, like it's already done in a couple > places, everywhere. This is the same

Re: [PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson Signed-off-by: Philippe

[PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE register for each port

Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon di

Re: [RFC PATCH 01/11] rust: qemu_api: do not disable lints outside bindgen-generated code

On 11/12/24 11:10, Junjie Mao wrote: diff --git a/meson.build b/meson.build index 1239f5c48c..8cea09ffe1 100644 --- a/meson.build +++ b/meson.build @@ -4,6 +4,7 @@ project('qemu', ['c'], meson_version: '>=1.5.0', version: files('VERSION')) meson.add_devenv({ 'MESON_BUILD_ROOT' : meso

[RFC PATCH 12/14] s390x/cpumodel: correct PLO feature wording

The PLO functions 0, 4, 8, 12, 16, and 20 use 32-bit registers values. The plo-*gr variants use 64-bit instead and, thus, correct the wording. Signed-off-by: Hendrik Brueckner Reviewed-by: Janosch Frank --- target/s390x/cpu_features_def.h.inc | 12 ++-- 1 file changed, 6 insertions(+),

[RESEND PATCH 09/10] usb-hub: Add support for v2.0 hubs

When adding a high speed USB device to the USB hub supported by qemu, it is added in full speed mode. Here is an example for a storage device. /: Bus 001.Port 001: Dev 001, Class=root_hub, Driver=platform-uhci/2p, 12M |__ Port 002: Dev 002, If 0, Class=Hub, Driver=hub/8p, 12M |__ Port

[PATCH 2/7 for-9.2] Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states"

This reverts commit bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d which broke cpu hotplug in x86 after migration to older QEMU Fixes: bf1ecc8dad606 (w/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states) Signed-off-by: Igor Mammedov --- include/hw/core/cpu.h | 1 - hw/acpi/cpu.c

[RESEND PATCH 07/10] aspeed: Add uhci support for ast2600

Add UHCI support for the ast2600 SoC. With this patch, UHCI support is successfully enabled on the rainier-bmc and ast2600-evb machines. Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 - Use EHCI companion mode hw/arm/aspeed_ast2600.c | 20 ++

[RFC PATCH 03/14] s390x/cpumodel: add msa12 changes

MSA12 changes the KIMD/KLMD instruction format for SHA3/SHAKE. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/gen-features.c | 8 2 files changed, 9 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

Hi Conny, On 11/12/24 17:30, Cornelia Huck wrote: > On Mon, Nov 11 2024, Cornelia Huck wrote: > >> On Mon, Nov 04 2024, Eric Auger wrote: >> >>> Hi Daniel, >>> >>> On 10/28/24 18:04, Daniel P. Berrangé wrote: On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote: > On Mon, 28 Oc

Re: [PATCH] GTM19-448: Fix script to work without realpath

On 11/12/24 10:38, Aleksandar Rakic wrote: The archive-source.sh script depends on realpath command, which was introduced in coreutils-8.15. CentOS-6 build systems use coreutils-4.7, which does not have realpath, so fix the script to use 'readlink -e' to perform the same action. Centos 6 is not

[PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper

For a particular physical address within the EthLite MMIO range, addr_to_port_index() returns which port is accessed. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/x

[PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit

All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/char/xilinx_uartlite.c | 4 hw/intc/xilinx_intc.c | 4

[RESEND PATCH 01/10] usb/uhci: checkpatch cleanup

Fix reported checkpatch issues to prepare for next patches in the series. No functional change. Reviewed-by: Cédric Le Goater Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 - Added Reviewed-by: tag hw/usb/hcd-uhci.c | 90 +-

Re: [PATCH 2/2] target/mips: Convert nanoMIPS LSA opcode to decodetree

On 12/11/24 14:30, Richard Henderson wrote: On 11/11/24 14:44, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper, taking care to substract 1 to the shift field. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé ---

[RFC PATCH 10/14] s390x/cpumodel: add Ineffective-nonconstrained-transaction facility

This facility indicates reduced support for noncontrained transactional-execution. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/cpu_models.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/targ

[RFC PATCH 01/14] s390x/cpumodel: add msa10 subfunctions

MSA10 introduces new AES XTS subfunctions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features_def.h.inc | 6 ++ target/s390x/cpu_models.c | 4 target/s390x/gen-features.c | 20 4 files chan

[RFC PATCH 08/14] s390x/cpumodel: add Miscellaneous-Instruction-Extensions Facility 4

This facility introduces few new instructions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_features_def.h.inc index 0b7be0e6e9..8be2e0e46d 100644 --- a/target/

[RFC PATCH 09/14] s390x/cpumodel: add Vector-Packed-Decimal-Enhancement facility 3

This facility introduces new capabilities for the signed-pack-decimal format. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/cpu_models.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/s390x/cpu_features_def.h.inc b/target/s3

[RFC PATCH 13/14] s390x/cpumodel: Add PLO-extension facility

The PLO-extension facility introduces numerous locking related subfunctions. Signed-off-by: Hendrik Brueckner Reviewed-by: Janosch Frank --- target/s390x/cpu_features_def.h.inc | 39 +++ target/s390x/cpu_models.c | 38 ++ target/s390x/ge

[PATCH v2 2/6] target/mips: Introduce decode tree bindings for nanoMIPS ISA

From: Philippe Mathieu-Daudé Introduce the nanoMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Rikalo Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h

[PATCH v2 1/6] target/mips: Introduce decode tree bindings for microMIPS ISA

From: Philippe Mathieu-Daudé Introduce the microMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/micromips16.decode| 9 + target/mips/tcg/micromips32.dec

[PATCH v2 0/6] target/mips: Convert nanoMIPS LSA opcode to decodetree

Prepare buildsys to decode micro/nanoMIPS opcodes using the decodetree script. Simplify gen_lsa/dsa() and convert micro/nanoMIPS LSA opcode to decodetree. Philippe Mathieu-Daudé (6): target/mips: Introduce decode tree bindings for microMIPS ISA target/mips: Introduce decode tree bindings for n

[PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.

[PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function

Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++-- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg

[PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree

Simply call the generic gen_lsa(), using the plus_1() helper to add 1 to the shift amount. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/micromips32.decode| 8 target/mips/tcg/micromips_translate.c | 10 ++ target/mips/tcg/micromips_translate.c.inc | 5

Re: [PATCH v2 6/6] target/mips: Convert nanoMIPS LSA opcode to decodetree

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips32.decode| 6 ++ target/mips/tcg/nanomips_translate.c

Re: [PATCH v2 1/7] accel/kvm: Keep track of the HWPoisonPage page_size

On 11/12/24 11:30, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When a memory page is added to the hwpoison_page_list, include the page size information.  This size is the backend real page size. To better deal with hugepages, we create a single entry f

Re: [PATCH v2 2/7] system/physmem: poisoned memory discard on reboot

On 11/12/24 12:07, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche We take into account the recorded page sizes to repair the memory locations, calling ram_block_discard_range() to punch a hole in the backend file when necessary and regenerate a usable mem

Re: [PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function

On 11/12/24 09:20, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++-- 4 files changed, 14 ins

Re: [PATCH v2 3/7] accel/kvm: Report the loss of a large memory page

On 11/12/24 12:13, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When an entire large page is impacted by an error (hugetlbfs case), report better the size and location of this large memory hole, so give a warning message when this page is first hit: Mem

Re: [PATCH v2 2/7] system/physmem: poisoned memory discard on reboot

For shared memory we really need it. Private file-backed is weird ... because we don't know if the shared or the private page is problematic ... :( I agree with you, and we have to decide when should we bail out if ram_block_discard_range() doesn't work. According to me, if discard doesn't wor

Re: [PATCH v2 3/7] accel/kvm: Report the loss of a large memory page

On 12.11.24 19:17, William Roche wrote: On 11/12/24 12:13, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: William Roche When an entire large page is impacted by an error (hugetlbfs case), report better the size and location of this large memory hole, so give a warning

Re: [PATCH v2 6/7] hostmem: Handle remapping of RAM

On 12.11.24 19:17, William Roche wrote: On 11/12/24 14:45, David Hildenbrand wrote: On 07.11.24 11:21, “William Roche wrote: From: David Hildenbrand Let's register a RAM block notifier and react on remap notifications. Simply re-apply the settings. Warn only when something goes wrong. Note:

Re: [PATCH 0/2] target/mips: Convert nanoMIPS LSA opcode to decodetree

> Yet another 2 patches extracted from an old branch > I'm rebasing. Trivial decodetree conversion of LSA, > however this introduce the basis to convert nanoMIPS > opcodes. > > Philippe Mathieu-Daudé (2): > target/mips: Introduce decode tree bindings for nanoMIPS ISA > target/mips: Convert nano

[PATCH v3 04/15] acpi/ghes: better handle source_id and notification

GHES has two fields that are stored on HEST error source blocks associated with notifications: - notification type, which is a number defined at the ACPI spec containing several arch-specific synchronous and assynchronous types; - source id, which is a HW/FW defined number, used to distinguish

[PATCH v3 02/15] acpi/ghes: simplify acpi_ghes_record_errors() code

Reduce the ident of the function and prepares it for the next changes. No functional changes. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- hw/acpi/ghes.c | 56 ++ 1 file changed, 29 insertions

[PATCH v3 01/15] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED

This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which has a better name. So, drop the duplication. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- hw/acpi/ghes.c | 7 ++- include/hw/acpi/ghes.h | 3 ++- 2 files changed, 4 ins

QEMU Code of Conduct mediation team

Hi everybody! TL;DR: As mentioned in https://lore.kernel.org/qemu-devel/CAFEAcA8pqjY-VKXPOe9W7J6upVhMeX8jJ=9gmb8e64etqhm...@mail.gmail.com/ there's the idea of having a dedicated group of people that can help to mediate Code of Conduct related problems. If you are interested in joining s

Re: [PATCH v4 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

On 11/8/24 23:56, Moger, Babu wrote: Hi Maxim, Thanks for looking into this. I will fix the bits I mentioned below in upcoming Genoa/Turin model update. I have few comments below. On 11/8/2024 12:15 PM, Maksim Davydov wrote: Hi! I compared EPYC-Genoa CPU model with CPUID output from real

Re: [PATCH v1 2/2] migration: Do not perform RAMBlock dirty sync during the first iteration

On 11.11.24 12:37, Yong Huang wrote: On Mon, Nov 11, 2024 at 6:42 PM David Hildenbrand > wrote: On 11.11.24 11:08, Yong Huang wrote: > > > On Mon, Nov 11, 2024 at 5:27 PM David Hildenbrand mailto:da...@redhat.com> >

Re: [Stable-7.2.15 17/33] target/i386: Walk NPT in guest real mode

Hey Michael, Does this queue also include the fix for the fix ("target/i386: Fix legacy page table walk")? https://lore.kernel.org/qemu-devel/20241106154329.67218-1-g...@amazon.com/ Alex On 09.11.24 07:38, Michael Tokarev wrote: From: Alexander Graf When translating virtual to physical a

Re: [PATCH 1/1] hw/riscv/riscv-iommu.c: Correct the validness check of iova

On 11/8/24 6:57 AM, Jason Chien wrote: From RISCV IOMMU spec section 2.1.3: When SXL is 1, the following rules apply: - If the first-stage is not Bare, then a page fault corresponding to the riginal access type occurs if the IOVA has bits beyond bit 31 set to 1. s/riginal/original - If th

Re: [PATCH RFC 4/5] acpi/generic_event_device: add logic to detect if HEST addr is available

Em Tue, 12 Nov 2024 15:55:57 +0100 Mauro Carvalho Chehab escreveu: > Em Thu, 3 Oct 2024 16:27:28 +0200 > Igor Mammedov escreveu: > > > > +++ b/hw/acpi/ghes.c > > > @@ -513,7 +513,7 @@ void ghes_record_cper_errors(const void *cper, size_t > > > len, > > > } > > > ags = &acpi_ged_state

Re: [PATCH] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache

CCing Tomasz On 11/8/24 8:01 AM, Jason Chien wrote: This commit introduces a translation tag to avoid invalidating an entry that should not be invalidated when IOMMU executes invalidation commands. E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping of single stage translation

Re: [PATCH] device/virtio-nsm: Support string data for extendPCR

Hey Alex, On Tue, Nov 12, 2024, 6:14 PM Alexander Graf wrote: > Hey Dorjoy, > > Thanks a lot for the patch! Would you mind to send to the ML so it can > go through the normal review + apply cycle? :) > > Same comment for the other patches. > I don't understand. I sent them to the mailing list

Re: [PATCH] device/virtio-nsm: Support string data for extendPCR

Hey Dorjoy, On 12.11.24 13:32, Dorjoy Chowdhury wrote: Hey Alex, On Tue, Nov 12, 2024, 6:14 PM Alexander Graf wrote: Hey Dorjoy, Thanks a lot for the patch! Would you mind to send to the ML so it can go through the normal review + apply cycle? :) Same comment for the o

[PATCH v2 4/4] tests/functional: Remove sleep workarounds from Aspeed tests

These were introduced in the avocado tests to workaround read issues when interacting with console. They are no longer necessary and we can use the expected "login:" string now. Signed-off-by: Cédric Le Goater --- tests/functional/test_arm_aspeed.py | 12 +--- 1 file changed, 5 insertio

[PATCH v2 3/4] tests/functional: Convert Aspeed arm SDK tests

Drop the SSH connection which was introduced in the avocado tests to workaround read issues when interacting with console. Signed-off-by: Cédric Le Goater --- tests/avocado/machine_aspeed.py | 124 tests/functional/test_arm_aspeed.py | 67 +++ 2 file

[PATCH v2 0/4] tests/functional: Finish conversion of Aspeed tests

Hello, The first patch is a proposal to fix a long-standing issue when capturing the console output. In some cases, the expected string does not match in the output, causing the test to fail with a timeout. The change introduces a _console_read() routine that processes the console output character

Re: [PATCH 0/3] target/mips: Convert Octeon LX instructions to decodetree

On 11/11/24 14:29, Philippe Mathieu-Daudé wrote: Hi, Few old patches lingering on an old branch I'm trying to rebase... Extract gen_lx() and call it via decodetree. Trivial IMHO. Philippe Mathieu-Daudé (3): target/mips: Extract gen_base_index_addr() helper target/mips: Extract generic ge

Re: [PATCH RFC 4/5] acpi/generic_event_device: add logic to detect if HEST addr is available

Em Thu, 3 Oct 2024 16:27:28 +0200 Igor Mammedov escreveu: > > +++ b/hw/acpi/ghes.c > > @@ -513,7 +513,7 @@ void ghes_record_cper_errors(const void *cper, size_t > > len, > > } > > ags = &acpi_ged_state->ghes_state; > > > > -if (!ags->hest_addr_le) { > > +if (!ags->hest_lookup

Re: [RFC PATCH 3/8] usb/uhci: Move PCI-related code into a separate file

On 11/12/24 15:50, Guenter Roeck wrote: Hi Thomas, On 11/11/24 22:32, Thomas Huth wrote: On 06/09/2024 14.25, Guenter Roeck wrote: Some machines (like Aspeed ARM) only have a sysbus UHCI controller. The current UHCI implementation only supports PCI based UHCI controllers. Move the UHCI-PCI dev

[PATCH v3 07/15] acpi/ghes: Change the type for source_id

As described at: ACPI 6.5 spec at: 18.3.2. ACPI Error Source In particular at GHES/GHESv2 table: Table 18.10 Generic Hardware Error Source Structure HEST source ID is actually a 16-bit value. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- hw/acpi/ghes-s

[PATCH v3 12/15] acpi/ghes: better name the offset of the hardware error firmware

The hardware error firmware is where HEST error structures are stored. Those can be GHESv2, but they can also be other types. Better name the location of the hardware error. No functional changes. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --

Re: [PATCH v6 60/60] docs: Add TDX documentation

On Tue, 2024-11-05 at 01:24 -0500, Xiaoyao Li wrote: > diff --git a/docs/system/confidential-guest-support.rst > b/docs/system/confidential-guest-support.rst > index 0c490dbda2b7..66129fbab64c 100644 > --- a/docs/system/confidential-guest-support.rst > +++ b/docs/system/confidential-guest-support.

[PATCH v3 05/15] acpi/ghes: Fix acpi_ghes_record_errors() argument

Align the header file with the actual implementation of this function, as the first argument is source ID and not notification type. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- Changes from v8: - Non-rename/cleanup changes merged altogethe

Re: [PATCH v3 0/2] target/i386: fix hang when using slow path for ptw_setl

On 10/25/24 10:58, Pierrick Bouvier wrote: Most of the details are available in first patch. Second one is there to ensure we'll have a useful error message if start_exclusive is called from cpu_exec again. I'm a bit puzzled that we never triggered this hang before. Is there something wrong with

Re: [PATCH] linux-user: Add missing mmap include

On 10/28/24 11:18, Patrick Leis wrote: From: Peter Foley error: use of undeclared identifier 'MAP_FIXED_NOREPLACE' Signed-off-by: Patrick Leis Signed-off-by: Peter Foley --- linux-user/user-mmap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/user-mmap.h b/linux-user/us

[PATCH v4 2/2] hw/ssi/pnv_spi: Coverity CID 1558827: Use local var seq_index instead of get_seq_index().

Use a local variable seq_index instead of repeatedly calling get_seq_index() method and open-code next_sequencer_fsm(). Signed-off-by: Chalapathi V --- hw/ssi/pnv_spi.c | 93 +--- 1 file changed, 48 insertions(+), 45 deletions(-) diff --git a/hw/ssi/p

Re: [PATCH v2 0/1] tests/tcg: Test that sigreturn() does not corrupt the signal mask

On 11/8/24 06:50, Ilya Leoshkevich wrote: v1: https://lore.kernel.org/qemu-devel/20241017125811.447961-1-...@linux.ibm.com/ v1 -> v2: Drop patch 1, since it's merged. Add -pthread to the test (Richard). Hi, I noticed that while the sigreturn fix was merged, the test wasn't. Richard

Re: [PATCH] tests/qtest: fix non portable env varibles access

Hi, On Tue, 12 Nov 2024 at 14:45, Дмитрий Фролов wrote: > It looks like this is a clang optimization issue. > > When environ is absent (not mentioned in the source code) > The value of envp is also 0x51400040 (reproducible), > but the behavior may be each time different. > Mostly test fails w

Re: [PATCH v2 2/7] system/physmem: poisoned memory discard on reboot

On 07.11.24 11:21, “William Roche wrote: From: William Roche We take into account the recorded page sizes to repair the memory locations, calling ram_block_discard_range() to punch a hole in the backend file when necessary and regenerate a usable memory. Fall back to unmap/remap the memory loca

[PATCH v3 00/15] Prepare GHES driver to support error injection

During the development of a patch series meant to allow GHESv2 error injections, it was requested a change on how CPER offsets are calculated, by adding a new BIOS pointer and reworking the GHES logic. See: https://lore.kernel.org/qemu-devel/cover.1726293808.git.mchehab+hua...@kernel.org/ Such ch

[PATCH v3 13/15] acpi/ghes: move offset calculus to a separate function

Currently, CPER address location is calculated as an offset of the hardware_errors table. It is also badly named, as the offset actually used is the address where the CPER data starts, and not the beginning of the error source. Move the logic which calculates such offset to a separate function, in

Re: [PATCH] tests/qtest: increase timeouts

On Tue, Nov 12, 2024 at 09:58:04AM -0300, Fabiano Rosas wrote: > Dmitry Frolov writes: > > > More time for some tests needed when qemu is built with > > "--enable-asan --enable-ubsan" > > > > Signed-off-by: Dmitry Frolov > > --- > > tests/qtest/meson.build | 4 ++-- > > 1 file changed, 2 insert

[RFC PATCH 04/14] s390x/cpumodel: add msa13 subfunctions

MSA13 introduces query authentication information (QAI) subfunctions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features_def.h.inc | 12 target/s390x/gen-features.c | 26 ++ 3 files changed, 40

[RFC PATCH 11/14] s390x/cpumodel: Add Sequential-Instruction-Fetching facility

The sequential instruction fetching facility provides few guarantees, for example, to avoid stop machine calls on enabling/disabling kprobes. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/cpu_features_def

[RFC PATCH 07/14] s390x/cpumodel: add Vector Enhancements facility 3

The Vector Enhancements facility 3 introduces new instructions and extends support for doubleword/quadword elements. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features_def.h.inc | 1 + target/s390x/cpu_models.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/s

[RFC PATCH 02/14] s390x/cpumodel: add msa11 subfunctions

MSA11 introduces new HMAC subfunctions. Signed-off-by: Hendrik Brueckner --- target/s390x/cpu_features.c | 2 ++ target/s390x/cpu_features_def.h.inc | 10 ++ target/s390x/cpu_models.c | 8 target/s390x/gen-features.c | 24 4 f

[RFC PATCH 00/14] KVM: s390: CPU model for gen17

Introducing the gen17 CPU model with feature indications comprising of: * Concurrent-function facility with subcodes * More vector extensions * Ineffective-nonconstrained-transaction facility * Even more msa crypto extensions * Additional PLO subfunctions For reference, see also the kernel part:

[PATCH v4 0/2] hw/ssi/pnv_spi: Remove PnvXferBuffer and fix CID 1558827

Hello, Thank You for reviewing patch v3, patch v4 addresses Nick's comments to use fifo8_num_used() and open-code next_sequencer_fsm(). Updates in V4: 1. Use of PnvXferBuffer results in a additonal process overhead due to frequent dynamic allocations and hence use an existing Fifo8 buffer. 2. Use

[PATCH v4 1/2] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure

In PnvXferBuffer dynamically allocating and freeing is a process overhead. Hence used an existing Fifo8 buffer with capacity of 16 bytes. Signed-off-by: Chalapathi V --- include/hw/ssi/pnv_spi.h | 3 + hw/ssi/pnv_spi.c | 237 +-- 2 files changed, 81

Re: [PATCH] device/virtio-nsm: Support string data for extendPCR

Hey Dorjoy, Thanks a lot for the patch! Would you mind to send to the ML so it can go through the normal review + apply cycle? :) Same comment for the other patches. Alex On 09.11.24 13:32, Dorjoy Chowdhury wrote: NSM device in AWS Nitro Enclaves supports extending with both bytestring and

[PATCH for-9.2] target/arm: Drop user-only special case in sve_stN_r

This path is reachable with plugins enabled, and provoked with run-plugin-catch-syscalls-with-libinline.so. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 4 1 file changed, 4 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f1ee

Re: [PATCH v1 1/2] virtio-balloon: Enable free page hinting during PRECOPY_NOTIFY_SETUP

On 09.11.24 05:59, Hyman Huang wrote: PRECOPY_NOTIFY_AFTER_BITMAP_SYNC was interpreted by free page hinting optimization as an indication to begin freeing pages. But there's no assurance that a sync is required when beginning a migration. Therefore, during PRECOPY_NOTIFY_SETUP, as well as PRECOPY

[PATCH v3 15/15] docs: acpi_hest_ghes: fix documentation for CPER size

While the spec defines a CPER size of 4KiB for each record, currently it is set to 1KiB. Fix the documentation and add a pointer to the macro name there, as this may help to keep it updated. Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- docs/spe

Re: [RFC PATCH 01/11] rust: qemu_api: do not disable lints outside bindgen-generated code

Paolo Bonzini writes: > Il mar 12 nov 2024, 03:47 Junjie Mao ha scritto: > > I agree that storing generated stuff in the source directory should not > be encouraged. > > Just want to mention that such changes can lead to trouble to > rust-analyzer. Today there are two ways to inform rust-a

Re: [PATCH v2 3/7] accel/kvm: Report the loss of a large memory page

On 07.11.24 11:21, “William Roche wrote: From: William Roche When an entire large page is impacted by an error (hugetlbfs case), report better the size and location of this large memory hole, so give a warning message when this page is first hit: Memory error: Loosing a large page (size: X) at

[PATCH] tests/qtest: increase timeouts

More time for some tests needed when qemu is built with "--enable-asan --enable-ubsan" Signed-off-by: Dmitry Frolov --- tests/qtest/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index aa93e98418..ead2207f9c 1

Re: [PATCH 2/2] target/mips: Convert nanoMIPS LSA opcode to decodetree

On 11/11/24 14:44, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper, taking care to substract 1 to the shift field. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips32.decode|

[RFC PATCH v6 0/2] Support RISC-V CSR read/write in Qtest environment

These patches add functionality for unit testing RISC-V-specific registers. The first patch adds a Qtest backend, and the second implements a simple test. --- v6: - Refactor code and fix checkpatch errors. --- Ivan Klokov (2): target/riscv: Add RISC-V CSR qtest support tests/qtest: QTest e

[RFC PATCH v6 2/2] tests/qtest: QTest example for RISC-V CSR register

Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test

[RFC PATCH v6 1/2] target/riscv: Add RISC-V CSR qtest support

The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov --- hw/riscv/riscv_hart.c | 55 ++

Re: [PATCH 1/2] target/mips: Introduce decode tree bindings for nanoMIPS ISA

On 11/11/24 14:44, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Introduce the nanoMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ ta

Re: [RFC PATCH 3/8] usb/uhci: Move PCI-related code into a separate file

Hi Thomas, On 11/11/24 22:32, Thomas Huth wrote: On 06/09/2024 14.25, Guenter Roeck wrote: Some machines (like Aspeed ARM) only have a sysbus UHCI controller. The current UHCI implementation only supports PCI based UHCI controllers. Move the UHCI-PCI device code into a separate file so that it

Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule

On 11/12/24 6:14 AM, Fea.Wang wrote: Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX,

Re: [PATCH] tests/qtest: increase timeouts

Dmitry Frolov writes: > More time for some tests needed when qemu is built with > "--enable-asan --enable-ubsan" > > Signed-off-by: Dmitry Frolov > --- > tests/qtest/meson.build | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/tests/qtest/meson.build b/tests/qtest/me

[PATCH v2 2/4] tests/functional: Convert Aspeed aarch64 SDK tests

Drop the SSH connection which was introduced in the avocado tests to workaround read issues when interacting with console. Signed-off-by: Cédric Le Goater Reviewed-by: Thomas Huth --- tests/avocado/machine_aspeed.py | 78 tests/functional/meson.build| 2

[PATCH v2 1/4] tests/functional: Introduce _console_read()

Interaction with the console has been a problem in our avocado tests. In some cases, the expected string does not match in the output, causing the test to fail with a timeout. These were worked around by sleeping before reading the console and even with SSH connections in some places. To fix, proc

[PATCH] firmware: Switch back to struct platform_driver::remove()

After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/firmware to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). A

Re: [PATCH v2 3/4] tests/functional: Convert Aspeed arm SDK tests

On 12/11/2024 14.02, Cédric Le Goater wrote: Drop the SSH connection which was introduced in the avocado tests to workaround read issues when interacting with console. Signed-off-by: Cédric Le Goater --- tests/avocado/machine_aspeed.py | 124 tests/functional

Re: [PATCH v2 5/8] i386: Add CPUID enumeration for RDT

Hi Hendrik, On Thu, Sep 5, 2024 at 1:22 PM Hendrik Wuethrich wrote: > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 4688d140c2..a5c4e3c463 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -42,6 +42,7 @@ > #include "hw/boards.h" > #include "hw/i386/sgx-epc.h" > #endi

[PATCH 00/18] x86: Improve operation under QEMU

U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it is not perfect. With both builds, executing the VESA ROM causes an intermittent hang, at least on some AMD CPUs. With qemu-x86_64 kvm cannot be used since the move to long mode (64-bit) is done in a way that works on real har

[PATCH 03/18] RFC: x86: qemu: Switch to bochs display

The vesa display is widely used on hardware, but it is a bit of a pain with QEMU. It requires executing option ROMs, which either doesn't work with kvm, or is difficult to do in a kvm/QEMU-friendly way. THe bochs display is probably better anyway, so switch to that. It works fine with kvm as it do

Re: [PATCH v2 1/4] tests/functional: Introduce _console_read()

On 12/11/2024 14.52, Cédric Le Goater wrote: Maybe we could use some funky unicode character instead? For example: console_logger.debug('🔎 %s', msg) or: console_logger.debug('✅ %s', msg) How's that ? https://paste.debian.net/1335303/ Fine for me! Thanks, Thomas

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