[PATCH v4 0/2] tpm: Resolve potential blocking-forever issue

In case swtpm was to return a control channel message with an error code it would often return less bytes than the full response. In some cases the current reading of the returned bytes would get stuck since more bytes are expected. Therefore, pass a separate parameter indicating how many bytes to

[PATCH v4 1/2] tpm: Use new ptm_cap_n structure for PTM_GET_CAPABILITY

Use the new ptm_cap_n structure for getting the PTM_GET_CAPABILITY response from swtpm. Previously only 17 bits could possibly have been set in ptm_cap (=uint64_t) in big endian order and those bits are now found in the 2nd 32bit word in the response in the caps field. This data structure makes it

Re: [PATCH v6 03/12] util/dsa: Implement DSA device start and stop logic.

On Wed, Oct 09, 2024 at 04:46:01PM -0700, Yichen Wang wrote: > diff --git a/util/meson.build b/util/meson.build > index 5d8bef9891..3360f62923 100644 > --- a/util/meson.build > +++ b/util/meson.build > @@ -88,6 +88,9 @@ if have_block or have_ga > endif > if have_block >util_ss.add(files('aio-

[PATCH v2] tests/functional: Convert most Aspeed machine tests

This is a simple conversion of the tests with some cleanups and adjustments to match the new test framework. Replace the zephyr image MD5 hashes with SHA256 hashes while at it. The SDK tests depend on a ssh class from avocado.utils which is difficult to replace. To be addressed separately. Signed

[PATCH v10 01/12] exec/memtxattr: add process identifier to the transaction attributes

From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-by: Tomasz Jeznach Reviewed-by: Frank Chang Revie

[PATCH v10 09/12] hw/riscv/riscv-iommu: add ATS support

From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Fr

[PATCH v10 00/12] riscv: QEMU RISC-V IOMMU support

Hi, In this new version we fixed address alignment issues in some command queue commands, pointed out by Jason in v9. No other changes made. Series based on alistair/riscv-to-apply.next. All patches reviewed. Changes from v9: - patch 3: - fixed cmd.dword1 alignment in riscv_iommu_process_cq_t

[PATCH v6 04/14] tcg/riscv: Add basic support for vector

From: Huang Shiyuan The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VE

[PATCH v6 12/14] tcg/riscv: Implement vector shi/s/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-11-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.h | 6 +-- tc

[PATCH v6 14/14] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-13-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH v6 05/14] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-5-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 76 +- 1 file chan

[PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec

Use vrsub.vi to subtract from a constant. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 8 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 9

[PATCH v6 11/14] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-10-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 33 ++

[PATCH v6 00/14] tcg/riscv: Add support for vector

Introduce support for the RISC-V vector extension in the TCG backend. v5: https://lore.kernel.org/qemu-devel/20241007025700.47259-1-zhiwei_...@linux.alibaba.com/ Changes for v6: - Fix problem with TB overflow restart wrt the constant pool. - Fix vsetivli disassembly. - Change set_vtype to

[PATCH v6 07/14] tcg/riscv: Implement vector cmp/cmpsel ops

From: TANG Tiancheng Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signe

[PATCH v6 06/14] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-6-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 3 ++ tcg/riscv/tcg-target-con-str.h | 1 + tcg/

[PATCH v6 08/14] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-8-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 7 +++ 2 files

[PATCH v6 10/14] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-9-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 41 +

[PATCH v6 02/14] disas/riscv: Fix vsetivli disassembly

The first immediate field is unsigned, whereas operand_vimm extracts a signed value. There is no need to mask the result with 'u'; just print the immediate with 'i'. Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector instructions") Signed-off-by: Richard Henderson --- disas/

[PATCH v6 01/14] tcg: Reset data_gen_ptr correctly

This pointer needs to be reset after overflow just like code_buf and code_ptr. Cc: qemu-sta...@nongnu.org Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools") Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/

[PATCH v6 13/14] tcg/riscv: Implement vector roti/v/x ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Message-ID: <20241007025700.47259-12-zhiwei_...@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 6 +++--- tcg/riscv/tcg-target.c.inc | 36 2 fi

Re: [PATCH v2] net/tap-win32: Fix gcc 14 format truncation errors

Am 8. Oktober 2024 20:28:42 UTC schrieb Bernhard Beschow : >The patch fixes the following errors generated by GCC 14.2: > >../src/net/tap-win32.c:343:19: error: '%s' directive output may be truncated >writing up to 255 bytes into a region of size 176 [-Werror=format-truncation=] > 343 |

[PATCH v6 03/14] util: Add RISC-V vector extension probe in cpuinfo

From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the divisio

[PATCH v10 03/12] hw/riscv: add RISC-V IOMMU base emulation

From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V

[PATCH v10 10/12] hw/riscv/riscv-iommu: add DBG support

From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided for it. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PATCH v10 07/12] test/qtest: add riscv-iommu-pci tests

To test the RISC-V IOMMU emulation we'll use its PCI representation. Create a new 'riscv-iommu-pci' libqos device that will be present with CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this device will only be consumed by the RISC-V libqos machine. Start with basic tests: a PC

[PATCH v10 05/12] hw/riscv: add riscv-iommu-pci reference device

From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PATCH v10 02/12] hw/riscv: add riscv-iommu-bits.h

From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the future Linux RISC-V IOMMU driver header, which would become

[PATCH v10 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e

[PATCH v10 06/12] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- hw/r

[PATCH v10 11/12] qtest/riscv-iommu-test: add init queues test

Add an additional test to further exercise the IOMMU where we attempt to initialize the command, fault and page-request queues. These steps are taken from chapter 6.2 of the RISC-V IOMMU spec, "Guidelines for initialization". It emulates what we expect from the software/OS when initializing the IO

[PATCH v10 12/12] docs/specs: add riscv-iommu

Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst | 1 + docs/specs/riscv-iommu.rst | 90 ++

[PATCH v10 04/12] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

The RISC-V IOMMU PCI device we're going to add next is a reference implementation of the riscv-iommu spec [1], which predicts that the IOMMU can be implemented as a PCIe device. However, RISC-V International (RVI), the entity that ratified the riscv-iommu spec, didn't bother assigning a PCI ID for

Re: Host riscv disas is broken

Hi Richard, On 2024/10/17 02:38, Richard Henderson wrote: 2595: if (dec->cfg->ext_zcmop) { 2690:    if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2716:    if (!dec->cfg->ext_zcmt) { 2726:    if (!dec->cfg->ext_zcmp) { 4028:   

[PATCH v4 00/19] s390x: Add Full Boot Order Support

From: Jared Rossi changes v3 -> v4: - Ensure signed-ness of return values is appropriate - Add missing newline character in replacements of sclp_print_int() - Add a missing return in a SCSI error path - Restore break that was incorrectly removed for Virtio CU devices - Remove an extra/early retur

[PATCH v4 02/19] pc-bios/s390-ccw: Use the libc from SLOF and remove sclp prints

From: Jared Rossi We are already using the libc from SLOF for the s390-netboot.img, and this libc implementation is way more complete and accurate than the simple implementation that we currently use for the s390-ccw.img binary. Since we are now always assuming that the SLOF submodule is availabl

[PATCH v4 12/19] pc-bios/s390-ccw: Enable failed IPL to return after error

From: Jared Rossi Remove panic-on-error from IPL functions such that a return code is propagated back to the main IPL calling function (rather than terminating immediately), which facilitates possible error recovery in the future. A select few panics remain, which indicate fatal non-devices erro

[PATCH v4 03/19] pc-bios/s390-ccw: Link the netboot code into the main s390-ccw.img binary

From: Jared Rossi We originally built a separate binary for the netboot code since it was considered as experimental and we could not be sure that the necessary SLOF module had been checked out. Time passed, the code proved its usefulness, and the build system nowadays makes sure that the SLOF mo

[PATCH v4 09/19] pc-bios/s390-ccw: Remove panics from SCSI IPL path

From: Jared Rossi Remove panic-on-error from virtio-scsi IPL specific functions so that error recovery may be possible in the future. Functions that would previously panic now provide a return code. Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/iplb.h | 2 + pc-bios/s390-ccw/boot

Re: [PATCH V1 1/4] hw/acpi: Initialize ACPI Hotplug CPU Status with Support for vCPU `Persistence`

On 10/15/24 5:22 AM, Salil Mehta wrote: Certain CPU architecture specifications [1][2][3] prohibit changes to CPU presence after the kernel has booted. This limitation exists because many system initializations rely on the exact CPU count at boot time and do not expect it to change later. For exa

Re: [PATCH V1 1/4] hw/acpi: Initialize ACPI Hotplug CPU Status with Support for vCPU `Persistence`

On 10/15/24 5:22 AM, Salil Mehta wrote: Certain CPU architecture specifications [1][2][3] prohibit changes to CPU presence after the kernel has booted. This limitation exists because many system initializations rely on the exact CPU count at boot time and do not expect it to change later. For exa

[Stable-9.1.1 42/49] hw/intc/arm_gicv3: Add cast to match the documentation

From: Alexandra Diupina The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICC_AP[0/1]R_EL2 are reserved. Add an explic

[Stable-9.1.1 37/49] target/m68k: Always return a temporary from gen_lea_mode

From: Richard Henderson Returning a raw areg does not preserve the value if the areg is subsequently modified. Fixes, e.g. "jsr (sp)", where the return address is pushed before the branch. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483 Signed-off-by: Richard Henderson Message-Id:

[Stable-9.1.1 33/49] linux-user/flatload: Take mmap_lock in load_flt_binary()

From: Philippe Mathieu-Daudé load_flt_binary() calls load_flat_file() -> page_set_flags(). page_set_flags() must be called with the mmap_lock held, otherwise it aborts: $ qemu-arm -L stm32/lib/ stm32/bin/busybox qemu-arm: ../accel/tcg/user-exec.c:505: page_set_flags: Assertion `have_mmap_l

[Stable-9.1.1 38/49] meson: fix machine option for x86_version

From: Pierrick Bouvier s/mbmi1/mbmi/ When configuring with -Dx86_version >= 3, meson step works, but compilation fails because option -mbmi1 is unknown. Signed-off-by: Pierrick Bouvier Reviewed-by: Alex Bennée Tested-by: Alex Bennée Link: https://lore.kernel.org/r/20241004223715.1275428-1-p

[Stable-9.1.1 00/49] Patch Round-up for stable 9.1.1, freeze on 2024-10-16 (frozen)

The following patches are queued for QEMU stable v9.1.1: https://gitlab.com/qemu-project/qemu/-/commits/staging-9.1 Patch freeze is 2024-10-16 (frozen), and the release is planned for 2024-10-18: https://wiki.qemu.org/Planning/9.1 Please respond here or CC qemu-sta...@nongnu.org on any addi

[Stable-9.1.1 49/49] ui/dbus: fix filtering all update messages

From: Marc-André Lureau Filtering pending messages when a new scanout is given shouldn't discard pending cursor changes, for example. Since filtering happens in a different thread, use atomic set/get. Fixes: fa88b85dea ("ui/dbus: filter out pending messages when scanout") Signed-off-by: Marc-A

[Stable-9.1.1 41/49] hw/intc/arm_gicv3: Add cast to match the documentation

From: Alexandra Diupina The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICH_AP[0/1]R_EL2 are reserved. Add an explic

[Stable-9.1.1 39/49] meson: define qemu_isa_flags

From: Paolo Bonzini Create a separate variable for compiler flags that enable specific instruction set extensions, so that they can be used with cc.compiles/cc.links. Note that -mfpmath=sse is a code generation option but it does not enable new instructions, therefore I did not make it part of q

[Stable-9.1.1 48/49] ui/win32: fix potential use-after-free with dbus shared memory

From: Marc-André Lureau DisplaySurface may be free before the pixman image is freed, since the image is refcounted and used by different objects, including pending dbus messages. Furthermore, setting the destroy function in create_displaysurface_from() isn't appropriate, as it may not be used, a

[Stable-9.1.1 43/49] hw/intc/arm_gicv3_cpuif: Add cast to match the documentation

From: Alexandra Diupina The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICH_AP[0/1]R_EL2 are reserved. Add an explic

[Stable-9.1.1 34/49] linux-user: Fix parse_elf_properties GNU0_MAGIC check

From: Richard Henderson Comparing a string of 4 bytes only works in little-endian. Adjust bulk bswap to only apply to the note payload. Perform swapping of the note header manually; the magic is defined so that it does not need a runtime swap. Fixes: 83f990eb5adb ("linux-user/elfload: Parse NT_

[Stable-9.1.1 45/49] hw/audio/hda: free timer on exit

From: Marc-André Lureau Fixes: 280c1e1cd ("audio/hda: create millisecond timers that handle IO") Signed-off-by: Marc-André Lureau Reviewed-by: Akihiko Odaki Message-ID: <20241008125028.1177932-2-marcandre.lur...@redhat.com> (cherry picked from commit f27206ceedbe2efae37c8d143c5eb2db05251508) S

[Stable-9.1.1 44/49] hw/char/pl011: Use correct masks for IBRD and FBRD

From: Peter Maydell In commit b88cfee90268cad we defined masks for the IBRD and FBRD integer and fractional baud rate divider registers, to prevent the guest from writing invalid values which could cause division-by-zero. Unfortunately we got the mask values the wrong way around: the FBRD registe

[Stable-9.1.1 46/49] hw/audio/hda: fix memory leak on audio setup

From: Marc-André Lureau When SET_STREAM_FORMAT is called, we should clear the existing setup. Factor out common function to close a stream. Direct leak of 144 byte(s) in 3 object(s) allocated from: #0 0x7f91d38f7350 in calloc (/lib64/libasan.so.8+0xf7350) (BuildId: a4ad7eb954b390cf00f07fa1

[Stable-9.1.1 40/49] meson: ensure -mcx16 is passed when detecting ATOMIC128

From: Paolo Bonzini Moving -mcx16 out of CPU_CFLAGS caused the detection of ATOMIC128 to fail, because flags have to be specified by hand in cc.compiles and cc.links invocations (why oh why??). Ensure that these tests enable all the instruction set extensions that will be used to build the emula

[Stable-9.1.1 36/49] tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr

From: Richard Henderson In tcg_out_qemu_ldst_i128, we need a non-zero index register, which we then use as a base register in several address modes. Since we always have TCG_REG_TMP2 available, use that. Cc: qemu-sta...@nongnu.org Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store") Resolv

[Stable-9.1.1 47/49] ui/dbus: fix leak on message filtering

From: Marc-André Lureau A filter function that wants to drop a message should return NULL, in which case it must also unref the message itself. Fixes: fa88b85de ("ui/dbus: filter out pending messages when scanout") Signed-off-by: Marc-André Lureau Reviewed-by: Akihiko Odaki Message-ID: <20241

[Stable-9.1.1 35/49] tcg/ppc: Use TCG_REG_TMP2 for scratch tcg_out_qemu_st

From: Richard Henderson In the fallback when STDBRX is not available, avoid clobbering TCG_REG_TMP1, which might be h.base, which is still in use. Use TCG_REG_TMP2 instead. Cc: qemu-sta...@nongnu.org Fixes: 01a112e2e9 ("tcg/ppc: Reorg tcg_out_tlb_read") Signed-off-by: Richard Henderson Tested-B

Host riscv disas is broken

2595:if (dec->cfg->ext_zcmop) { 2690:if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2716:if (!dec->cfg->ext_zcmt) { 2726:if (!dec->cfg->ext_zcmp) { 4028:if (dec->cfg->ext_zimop) { 5044:if (d

Re: [PATCH v6 03/12] util/dsa: Implement DSA device start and stop logic.

Yichen Wang writes: > From: Hao Xiang > > * DSA device open and close. > * DSA group contains multiple DSA devices. > * DSA group configure/start/stop/clean. > > Signed-off-by: Hao Xiang > Signed-off-by: Bryan Zhang > Signed-off-by: Yichen Wang > --- > include/qemu/dsa.h | 103 ++

Re: [PATCH V1 1/4] hw/acpi: Initialize ACPI Hotplug CPU Status with Support for vCPU `Persistence`

Hi Salil, On 10/14/24 16:22, Salil Mehta wrote: Certain CPU architecture specifications [1][2][3] prohibit changes to CPU presence after the kernel has booted. This limitation exists because many system initializations rely on the exact CPU count at boot time and do not expect it to change later

Re: [PATCH 1/4] hw/net/lan9118: Extract lan9118_phy

Am 15. Oktober 2024 09:27:40 UTC schrieb Peter Maydell : >On Mon, 14 Oct 2024 at 19:50, Bernhard Beschow wrote: >> >> >> >> Am 14. Oktober 2024 12:47:52 UTC schrieb Peter Maydell >> : >> >> +typedef struct Lan9118PhyState { >> >> +uint32_t status; >> >> +uint32_t control; >> >> +u

Re: [PATCH] migration/dirtyrate: Silence warning about strcpy() on OpenBSD

On Wed, Oct 16, 2024 at 05:22:11PM +0100, Daniel P. Berrangé wrote: > On Wed, Oct 16, 2024 at 06:07:12PM +0200, Thomas Huth wrote: > > The linker on OpenBSD complains: > > > > ld: warning: dirtyrate.c:447 (../src/migration/dirtyrate.c:447)(...): > > warning: strcpy() is almost always misused, pl

Re: [External] Re: [PATCH v6 00/12] Use Intel DSA accelerator to offload zero page checking in multifd live migration.

On Tue, Oct 15, 2024 at 03:02:37PM -0700, Yichen Wang wrote: > On Fri, Oct 11, 2024 at 9:32 AM Peter Xu wrote: > > > > On Wed, Oct 09, 2024 at 04:45:58PM -0700, Yichen Wang wrote: > > > > The doc update is still missing under docs/, we may need that for a final > > merge. > > > > I will work with

[PATCH v2 0/5] Consolidate lan9118 phy implementations

hw/net/imx_fec and hw/net/lan9118 implement the same Ethernet PHY with similar but not quite the same code. This series consolidates the implementations into one to fix code duplication. It then continues to make the code more readable by reusing some existing constants. Having a dedicated module

[PATCH v2 3/5] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations

imx_fec models the same PHY as lan9118_phy. The code is almost the same with imx_fec having more logging and tracing. Merge these improvements into lan9118_phy and reuse in imx_fec to fix the code duplication. Some migration state how resides in the new device model which breaks migration compatib

[PATCH v2 5/5] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement

The real device advertises this mode and the device model already advertises 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to make the model more realistic. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- hw/net/lan9118_phy.c | 4 ++-- 1 file changed,

[PATCH v2 2/5] hw/net/lan9118: Extract lan9118_phy

A very similar implementation of the same device exists in imx_fec. Prepare for a common implementation by extracting a device model into its own files. Some migration state has been moved into the new device model which breaks migration compatibility for the following machines: * smdkc210 * realv

[PATCH v2 4/5] hw/net/lan9118_phy: Reuse MII constants

Prefer named constants over magic values for better readability. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- include/hw/net/mii.h | 6 + hw/net/lan9118_phy.c | 59 +++- 2 files changed, 43 insertions(+), 22 deletions(-) diff --git

[PATCH v2 1/5] hw/resettable: Add SOFT reset type

This is a preparation for the next patch. Signed-off-by: Bernhard Beschow --- include/hw/resettable.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index fd862f1e9f..0f25beaf21 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettabl

Re: [PATCH] hw/net: Extend ethernetlite driver with PHY layer

Am 15. Oktober 2024 13:26:22 UTC schrieb Sai Pavan Boddu : >From: Michal Simek > >Add missing optional MDIO lines. Without it U-Boot is not working. > >Signed-off-by: Edgar E. Iglesias >Signed-off-by: Michal Simek Overall the code seems almost identical to the one in axienet. Doesn't it mak

Re: [PATCH v3 3/4] migration: Support periodic ramblock dirty sync

On Wed, Oct 16, 2024 at 03:56:44PM +0800, yong.hu...@smartx.com wrote: > From: Hyman Huang > > When VM is configured with huge memory, the current throttle logic > doesn't look like to scale, because migration_trigger_throttle() > is only called for each iteration, so it won't be invoked for a lo

Re: [PATCH v3 4/4] tests/migration: Add case for periodic ramblock dirty sync

On Wed, Oct 16, 2024 at 03:56:45PM +0800, yong.hu...@smartx.com wrote: > From: Hyman Huang > > Signed-off-by: Hyman Huang Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH v9 03/12] hw/riscv: add RISC-V IOMMU base emulation

On 10/16/24 12:37 AM, Jason Chien wrote: Hi Daniel, On 2024/10/4 下午 11:57, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-n

Re: [PATCH] linux-headers: loongarch: add kvm_para.h and unistd_64.h

On 2024/10/16 下午4:41, gaosong wrote: 在 2024/10/16 下午4:13, maobibo 写道: ping. @Song Could you give some comments since it is LoongArch specific? Regards Bibo Mao On 2024/9/29 下午3:22, Bibo Mao wrote: KVM LBT supports on LoongArch requires the linux-header kvm_para.h, also unistd_64.h is req

[PATCH v4 01/19] hw/s390x/ipl: Provide more memory to the s390-ccw.img firmware

From: Jared Rossi We are going to link the SLOF libc into the s390-ccw.img, and this libc needs more memory for providing space for malloc() and friends. Thus bump the memory size that we reserve for the bios to 3 MiB instead of only 2 MiB. While we're at it, add a proper check that there is real

[PATCH v4 05/19] pc-bios/s390-ccw: Merge netboot.mak into the main Makefile

From: Jared Rossi Now that the netboot code has been merged into the main s390-ccw.img, it also does not make sense to keep the build rules in a separate file. Thus let's merge netboot.mak into the main Makefile. Co-authored by: Thomas Huth Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/netb

[PATCH v4 13/19] include/hw/s390x: Add include files for common IPL structs

From: Jared Rossi Currently, structures defined in both hw/s390x/ipl.h and pc-bios/s390-ccw/iplb.h must be kept in sync, which is prone to error. Instead, create a new directory at include/hw/s390x/ipl/ to contain the definitions that must be shared. Signed-off-by: Jared Rossi Reviewed-by: Thom

[PATCH v4 06/19] docs/system/s390x/bootdevices: Update the documentation about network booting

From: Jared Rossi Remove the information about the separate s390-netboot.img from the documentation. Co-authored by: Thomas Huth Signed-off-by: Jared Rossi --- docs/system/s390x/bootdevices.rst | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/docs/syst

[PATCH v4 04/19] hw/s390x: Remove the possibility to load the s390-netboot.img binary

From: Jared Rossi Since the netboot code has now been merged into the main s390-ccw.img binary, we don't need the separate s390-netboot.img anymore. Remove it and the code that was responsible for loading it. Co-authored by: Thomas Huth Signed-off-by: Jared Rossi --- hw/s390x/ipl.h

[PATCH v4 16/19] s390x: Rebuild IPLB for SCSI device directly from DIAG308

From: Jared Rossi Because virtio-scsi type devices use a non-architected IPLB pbt code they cannot be set and stored normally. Instead, the IPLB must be rebuilt during re-ipl. As s390x does not natively support multiple boot devices, the devno field is used to store the position in the boot orde

[PATCH v4 07/19] pc-bios/s390-ccw: Remove panics from ISO IPL path

From: Jared Rossi Remove panic-on-error from IPL ISO El Torito specific functions so that error recovery may be possible in the future. Functions that would previously panic now provide a return code. Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/bootmap.h | 15 +++ pc-bios/s390-ccw/s3

[PATCH v4 10/19] pc-bios/s390-ccw: Remove panics from DASD IPL path

From: Jared Rossi Remove panic-on-error from DASD IPL specific functions so that error recovery may be possible in the future. Functions that would previously panic now provide a return code. Signed-off-by: Jared Rossi Reviewed-by: Thomas Huth --- pc-bios/s390-ccw/dasd-ipl.h | 2 +- pc-bios

[PATCH v4 08/19] pc-bios/s390-ccw: Remove panics from ECKD IPL path

From: Jared Rossi Remove panic-on-error from ECKD block device IPL specific functions so that error recovery may be possible in the future. Functions that would previously panic now provide a return code. Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/bootmap.h | 1 + pc-bios/s390-ccw/boot

[PATCH v4 15/19] hw/s390x: Build an IPLB for each boot device

From: Jared Rossi Build an IPLB for any device with a bootindex (up to a maximum of 8 devices). The IPLB chain is placed immediately before the BIOS in memory. Because this is not a fixed address, the location of the next IPLB and number of remaining boot devices is stored in the QIPL global var

[PATCH v4 19/19] tests/qtest: Add s390x boot order tests to cdrom-test.c

From: Jared Rossi Add two new qtests to verify that a valid IPL device can successfully boot after failed IPL attempts from one or more invalid devices. cdrom-test/as-fallback-device: Defines the primary boot target as a device that is invalid for IPL and a second boot target that is valid for I

[PATCH v4 14/19] s390x: Add individual loadparm assignment to CCW device

From: Jared Rossi Add a loadparm property to the VirtioCcwDevice object so that different loadparms can be defined on a per-device basis for CCW boot devices. The machine/global loadparm is still supported. If both a global and per-device loadparm are defined, the per-device value will override

[PATCH v2 0/2] linux-headers: loongarch: Add kvm_para.h and unistd_64.h

linux-headers/asm/unistd.h:3:10: fatal error: asm/unistd_64.h: No such file or directory #include Also update linux-headers to v6.12-rc3 --- v1 ... v2: 1. update header files in directory linux-headers to v6.12-rc3 --- Bibo Mao (2): linux-headers: loongarch: Add kvm_para.h and unistd_64.h

[PATCH v2 2/2] linux-headers: Update to Linux v6.12-rc3

This update contains the required header changes for LoongArch KVM LBT feature. Signed-off-by: Bibo Mao --- include/standard-headers/drm/drm_fourcc.h | 43 +++ include/standard-headers/linux/const.h| 17 + include/standard-headers/linux/ethtool.h | 226 + include/s

[PATCH v4 17/19] pc-bios/s390x: Enable multi-device boot loop

From: Jared Rossi Allow attempts to boot from multiple IPL devices. If the first device fails to IPL, select the pre-built IPLB for the next device in the boot order and attempt to IPL from it. Continue this process until IPL is successful or there are no devices left to try. Signed-off-by: Jare

[PATCH v4 18/19] docs/system: Update documentation for s390x IPL

From: Jared Rossi Update docs to show that s390x PC BIOS can support more than one boot device. Signed-off-by: Jared Rossi Reviewed-by: Thomas Huth --- docs/system/bootindex.rst | 7 --- docs/system/s390x/bootdevices.rst | 9 ++--- 2 files changed, 10 insertions(+), 6 deletion

[PATCH v4 11/19] pc-bios/s390-ccw: Remove panics from Netboot IPL path

From: Jared Rossi Remove panic-on-error from Netboot specific functions so that error recovery may be possible in the future. Functions that would previously panic now provide a return code. Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/s390-ccw.h | 2 +- pc-bios/s390-ccw/bootmap.c|

How to use "subprojects/slirp.wrap"?

I want to build qemu with libslirp which built from source code but not from the system. Maybe the "subprojects/slirp.wrap" is the right way, is it? But I can't find more information about how to use it on the internet. Is there some notes about that? Thanks.

[PATCH v2 1/2] linux-headers: loongarch: Add kvm_para.h and unistd_64.h

KVM LBT supports on LoongArch depends on the linux-header file kvm_para.h, also unistd_64.h is required by unistd.h on LoongArch since 6.11, otherwise there will be compiling error such as: linux-headers/asm/unistd.h:3:10: fatal error: asm/unistd_64.h: No such file or directory #include Signed

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