On 08-10-2024 13:29, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
In PnvXferBuffer dynamically allocating and freeing is a
process overhead. Hence used an existing Fifo8 buffer with
capacity of 16 bytes.
Signed-off-by: Chalapathi V
---
include/hw/ssi/pnv_
On Tue, Oct 08, 2024 at 05:05:01PM -0400, Steven Sistare wrote:
> On 10/8/2024 12:26 PM, Peter Xu wrote:
> > On Tue, Oct 08, 2024 at 11:17:46AM -0400, Steven Sistare wrote:
> > > On 10/7/2024 12:28 PM, Peter Xu wrote:
> > > > On Mon, Oct 07, 2024 at 11:49:25AM -0400, Peter Xu wrote:
> > > > > On Mo
Elena Ufimtseva writes:
> On Fri, Sep 13, 2024 at 3:07 PM Fabiano Rosas wrote:
>
>> Fix a segmentation fault in multifd when rb->receivedmap is cleared
>> too early.
>>
>> After commit 5ef7e26bdb ("migration/multifd: solve zero page causing
>> multiple page faults"), multifd started using the rb
On Tue, Oct 8, 2024, 1:03 PM Peter Maydell wrote:
> On Tue, 8 Oct 2024 at 17:50, John Snow wrote:
> >
> >
> >
> > On Tue, Oct 8, 2024, 12:31 PM Peter Maydell
> wrote:
> >>
> >> I made some changes to a block backend so I wanted to run the iotests.
> >> I ran into an unrelated failure of iotest
Comparing a string of 4 bytes only works in little-endian.
Adjust bulk bswap to only apply to the note payload.
Perform swapping of the note header manually; the magic
is defined so that it does not need a runtime swap.
Fixes: 83f990eb5adb ("linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes"
From: Ilya Leoshkevich
Borrow the code for formatting the most frequent WIFEXITED() and
WIFSIGNALED() special cases from from the strace's printstatus().
Output examples:
474729 wait4(-1,0x7f00767ff0a0,0,(nil)) = 474733 (wstatus={WIFEXITED(s) &&
WEXITSTATUS(s) == 1})
475833 wait4(-1,0x
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Message-ID: <20240807124306.52903-4-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
linux-user/strace.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/li
In tcg_out_qemu_ldst_i128, we need a non-zero index register,
which we then use as a base register in several address modes.
Since we always have TCG_REG_TMP2 available, use that.
Cc: qemu-sta...@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Resolves: https://gitlab.com/qem
On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
> As of half an hour ago =) We could put a feature branch up and work
> together, if you have more concrete thoughts on how this would look like
> let me know.
[I'll hijack this thread with one more email, as this is not cpr-relevant]
The probe_access_full_mmu function was designed for this purpose,
and does not report the memory operation event to plugins.
Cc: qemu-sta...@nongnu.org
Fixes: 6d03226b422 ("plugins: force slow path when plugins instrument memory
ops")
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
> From: "Philippe Mathieu-Daudé"
>
> It is unfair to let the PowerNV SPI model to the SSI
> maintainers. Also include the PowerNV ones.
>
> Fixes: 29318db133 ("hw/ssi: Add SPI model")
> Signed-off-by: Philippe Mathieu-Daudé
>
> Signed-off-b
Hello,
This is a resping of Alejandro's series fixing SG Accumulative Hash
Calculations. See [1] for more details.
The goal of this patch series is to fix accumulative hashing support
in the Aspeed HACE module. The issue that stemmed this patch was a
failure to boot an OpenBMC image using the "a
From: Alejandro Zeise
Implements the new hashing API in the gcrypt hash driver.
Supports creating/destroying a context, updating the context
with input data and obtaining an output hash.
Signed-off-by: Alejandro Zeise
[ clg: - Dropped qcrypto_hash_supports() in qcrypto_gcrypt_hash_new()
From: Alejandro Zeise
Implements the new hashing API in the nettle hash driver.
Supports creating/destroying a context, updating the context
with input data and obtaining an output hash.
Signed-off-by: Alejandro Zeise
[ clg: - Dropped qcrypto_hash_supports() in qcrypto_nettle_hash_new() ]
Signe
From: Alejandro Zeise
Implements the new hashing API in the GLib hash driver.
Supports creating/destroying a context, updating the context
with input data and obtaining an output hash.
Signed-off-by: Alejandro Zeise
[ clg: - Dropped qcrypto_hash_supports() in qcrypto_glib_hash_new()
- Re
From: Alejandro Zeise
Remove old hash_bytesv function, as it was replaced by the 4
new functions.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
---
crypto/hashpriv.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/crypto/hashpriv.h b/crypto/hashpriv.h
index dcb3ba6cf
From: Alejandro Zeise
Make the Aspeed HACE module use the new qcrypto accumulative hashing functions
when in scatter-gather accumulative mode. A hash context will maintain a
"running-hash" as each scatter-gather chunk is received.
Previously each scatter-gather "chunk" was cached
so the hash cou
From: Alejandro Zeise
Removes old hash implementation in the gcrypt hash driver.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
[ clg: - Fixed spelling in commit log ]
Signed-off-by: Cédric Le Goater
---
crypto/hash-gcrypt.c | 67
From: Alejandro Zeise
Removes the old hash API functions in the afalg driver,
and modifies the hmac function to use the new helper functions.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
[ clg: - Checkpatch fixes ]
Signed-off-by: Cédric Le Goater
---
crypto/hash-afalg.c | 6
From: Alejandro Zeise
Changes the hash API to support accumulative hashing.
Hash objects are created with "qcrypto_hash_new",
updated with data with "qcrypto_hash_update", and
the hash obtained with "qcrypto_hash_finalize".
These changes bring the hashing API more in line with the
hmac API.
Sig
From: Alejandro Zeise
Removes old hash implementation in the nettle hash driver.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
[ clg: - Fixed spelling in commit log ]
Signed-off-by: Cédric Le Goater
---
crypto/hash-nettle.c | 53
From: Alejandro Zeise
In order to support a new update function, a flag needs to be passed
to the kernel via the socket send call (MSG_MORE) to notify it that
more data is to be expected to calculate the hash correctly.
Add a new iov helper for this purpose.
Signed-off-by: Alejandro Zeise
[ cl
From: Alejandro Zeise
Added an accumulative hashing test. Checks for functionality of
the new hash create, update, finalize and free functions.
Signed-off-by: Alejandro Zeise
[ clg: - Improved test_hash_accumulate() with g_autofree variables ]
Signed-off-by: Cédric Le Goater
---
tests/unit/te
From: Alejandro Zeise
Implements the new hashing API in the gnutls hash driver.
Supports creating/destroying a context, updating the context
with input data and obtaining an output hash.
Signed-off-by: Alejandro Zeise
[ clg: - Dropped qcrypto_hash_supports() in qcrypto_gnutls_hash_new()
From: Alejandro Zeise
Updates the afalg hash driver to support the new accumulative
hashing changes as part of the patch series.
Implements opening/closing of contexts, updating hash data
and finalizing the hash digest.
In order to support the update function, a flag needs to be passed
to the k
From: Alejandro Zeise
Removes old hash implementation in the gnutls hash driver.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
[ clg: - Fixed spelling in commit log ]
Signed-off-by: Cédric Le Goater
---
crypto/hash-gnutls.c | 47
From: Alejandro Zeise
Changes the public hash API implementation to support accumulative hashing.
Implementations for the public functions are added to call the new
driver functions that implement context creation, updating,
finalization, and destruction.
Additionally changes the "shortcut" fun
From: Alejandro Zeise
Removes old hash implement-ion in the GLib hash driver.
Signed-off-by: Alejandro Zeise
Reviewed-by: Daniel P. Berrangé
[ clg: - Fixed spelling in commit log ]
Signed-off-by: Cédric Le Goater
---
crypto/hash-glib.c | 53 --
1 f
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
> In PnvXferBuffer dynamically allocating and freeing is a
> process overhead. Hence used an existing Fifo8 buffer with
> capacity of 16 bytes.
>
> Signed-off-by: Chalapathi V
> ---
> include/hw/ssi/pnv_spi.h | 3 +
> hw/ssi/pnv_spi.c
On 10/8/24 09:57, Cédric Le Goater wrote:
Hello,
This is a resping of Alejandro's series fixing SG Accumulative Hash
Calculations. See [1] for more details.
arf.
[1]
https://lore.kernel.org/all/20240807195122.2827364-1-alejandro.ze...@seagate.com/
C.
The goal of this patch series is to f
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
> Hello,
>
> v3:
> 1. Update the PowerNV maintainer section to include hw/ssi/pnv_spi*
> 2. Use of PnvXferBuffer results in a additonal process overhead due to
> frequent dynamic allocations and hence use an existing Fifo8 buffer.
> 3. Use a
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
> Use a local variable seq_index instead of repeatedly caling
> get_seq_index() method.
>
> Signed-off-by: Chalapathi V
> ---
> hw/ssi/pnv_spi.c | 61
> 1 file changed, 31 insertions(+), 30 d
"Zuo,Boqun" writes:
> On Wed, Sep 25, 2024 8:58 PM Junjie Mao wrote:
>> > As shown below, if a virtio PCI device is attached under a pci-bridge,
>> > the MR of VirtIOPCIRegion does not belong to any address space. So
>> > memory_region_find cannot be used to search for this MR.
>> >
>> > Introd
Hotpluggable vCPUs must be exposed as "online-capable" according to the new UEFI
specification [1][2]. However, marking cold-booted vCPUs as "online-capable"
during boot may cause them to go undetected by legacy operating systems,
potentially leading to compatibility issues. Hence, both 'online-cap
From: Jean-Philippe Brucker
Previously, all `PSCI_CPU_{ON, OFF}` calls were handled directly by KVM.
However, with the introduction of vCPU hotplug, these hypervisor calls are now
trapped to QEMU for policy checks. This shift can lead to inconsistent vCPU
states between KVM and QEMU, particularly
From: Author Salil Mehta
To support vCPU hotplug, we must trap any `HVC`/`SMC` `PSCI_CPU_{ON,OFF}`
hypercalls from the host KVM to QEMU for policy checks. This ensures the
following when a vCPU is brought online:
1. The vCPU is actually plugged in (i.e., present).
2. The vCPU is not disabled.
I
vCPU reset can result in device access to VGIC CPU system registers using the
`IOCTL KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS` interface. When accessing these
registers in the KVM host, it is necessary to acquire a lock on all vCPUs during
the `vgic_v3_attr_regs_access()` operation.
This operation may fai
On 8/10/24 17:28, Bernhard Beschow wrote:
The patch fixes the following errors generated by GCC 14.2:
../src/net/tap-win32.c:343:19: error: '%s' directive output may be truncated
writing up to 255 bytes into a region of size 176 [-Werror=format-truncation=]
343 | "%s\\%s\\Connec
On 8/10/24 21:20, Richard Henderson wrote:
The probe_access_full_mmu function was designed for this purpose,
and does not report the memory operation event to plugins.
Cc: qemu-sta...@nongnu.org
Fixes: 6d03226b422 ("plugins: force slow path when plugins instrument memory
ops")
Signed-off-by: Ri
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2
On Intel platform:
CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for
logical processors in the physical package".
When executing "cpuid -1 -l 1 -r" i
On Tue, 08 Oct 2024, nifan@gmail.com wrote:\n
From: Fan Ni
In the function cmd_firmware_update_get_info for handling Get FW info
command (0x0200h), the vmem, pmem and DC capacity size check were
incorrect. The size should be aligned to 256MiB, not smaller than
256MiB.
Can get rid of a lev
vCPU Hot-unplug will result in QOM CPU object unrealization which will do away
with all the vCPU thread creations, allocations, registrations that happened
as part of the realization process. This change introduces the ARM CPU unrealize
function taking care of exactly that.
Note, initialized KVM v
From: Miguel Luis
Introduce the TCG thread unregistration leg which shall be called in context to
TCG/vCPU unrealize.
Reported-by: Salil Mehta
Signed-off-by: Miguel Luis
Signed-off-by: Salil Mehta
---
accel/tcg/tcg-accel-ops-mttcg.c | 1 +
include/tcg/startup.h | 7 +++
tcg/t
The TCG code cache consists of multiple regions shared among vCPUs in
multi-threaded TCG mode. For cold-plugged vCPUs, these regions are sized and
allocated during initialization in the `tcg_register_thread()` function when the
vCPUs are realized. Later, these regions must be reallocated for hot-pl
The QOM `GICv3CPUState` (and consequently the corresponding KVM VGIC `ICC_*_EL1`
registers) can be either 'accessible' or 'inaccessible', depending on the state
of the associated QOM vCPUs. This `gicc_accessible` state should be saved during
migration at the source and restored at the destination.
On 10/8/2024 12:26 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 11:17:46AM -0400, Steven Sistare wrote:
On 10/7/2024 12:28 PM, Peter Xu wrote:
On Mon, Oct 07, 2024 at 11:49:25AM -0400, Peter Xu wrote:
On Mon, Sep 30, 2024 at 12:40:36PM -0700, Steve Sistare wrote:
Save the memfd for anonymous r
On 10/8/2024 10:33 AM, Vladimir Sementsov-Ogievskiy wrote:
On 30.09.24 22:40, Steve Sistare wrote:
Some devices need new kernel software interfaces
to allow a descriptor to be used in a process that did not originally open it.
Hi Steve!
Could you please describe, which kernel version / featur
Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves[2]
for stripped down TPM functionality like cryptographic attestation.
The requests to and responses from NSM device are CBOR[3] encoded.
This commit adds support for NSM device in QEMU. Although related to
AWS Nitro Enclaves, the v
An EIF (Enclave Image Format)[1] file is used to boot an AWS nitro
enclave[2] virtual machine. The EIF file contains the necessary kernel,
cmdline, ramdisk(s) sections to boot.
Some helper functions have been introduced for extracting the necessary
sections from an EIF file and then writing them t
libcbor dependecy is necessary for adding virtio-nsm and nitro-enclave
machine support in the following commits. libvirt-ci has already been
updated with the dependency upstream and this commit updates libvirt-ci
submodule in QEMU to latest upstream. Also the libcbor dependency has
been added to te
Signed-off-by: Dorjoy Chowdhury
---
MAINTAINERS| 1 +
docs/system/i386/nitro-enclave.rst | 78 ++
2 files changed, 79 insertions(+)
create mode 100644 docs/system/i386/nitro-enclave.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index f78a7cca06.
AWS nitro enclaves[1] is an Amazon EC2[2] feature that allows creating
isolated execution environments, called enclaves, from Amazon EC2
instances which are used for processing highly sensitive data. Enclaves
have no persistent storage and no external networking. The enclave VMs
are based on the Fi
This is v8 submission for AWS Nitro Enclave emulation in QEMU. From the QEMU
side
the implementation for nitro enclaves is complete. v7 is at:
https://lore.kernel.org/qemu-devel/20240922094441.23802-1-dorjoychy...@gmail.com/T/#t
Changes in v8:
- create_default_memdev related changes have been
This is in preparation for the next commit where the nitro-enclave
machine type will need to instead use a memfd backend for the built-in
vhost-user-vsock device to work.
Signed-off-by: Dorjoy Chowdhury
---
backends/hostmem-memfd.c | 2 --
hw/core/machine.c| 71 +
On 10/6/24 19:56, LIU Zhiwei wrote:
+}
tcg_target_call_clobber_regs = -1u;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
I believe all of the vector registers are call-clobbered?
This needs
- tcg_target_call_clobber_regs = -1u;
+ tcg_target_cal
> >> > diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index
> >> > 6a4e38856d..74683e7445 100644
> >> > --- a/hw/pci/pci_bridge.c
> >> > +++ b/hw/pci/pci_bridge.c
> >> > @@ -380,6 +380,7 @@ void pci_bridge_initfn(PCIDevice *dev, const char
> >> *typename)
> >> > sec_bus->map_irq = br->map_i
For unsupported acceleration types and GIC versions, explicitly disable vCPU
hotplug support and limit the number of possible vCPUs to those available at
boot time (i.e., SMP CPUs). This flag will be referenced at various points in
the code to verify the presence of vCPU hotplug functionality on th
PROLOGUE
To assist in review and set the right expectations from this RFC, please first
read the sections *APPENDED AT THE END* of this cover letter:
1. Important *DISCLAIMER* [Section (X)]
2. Work presented at KVMForum Conference (slides available) [Section (V)F]
3. Organization of patc
Factor out vCPU properties code common for {hot,cold}-plugged vCPUs in the
machvirt_init(). This allows code reuse.
Signed-off-by: Salil Mehta
---
hw/arm/virt.c | 219 ++
include/hw/arm/virt.h | 4 +
2 files changed, 139 insertions(+), 84 deletio
This patch adds various utility functions that may be required to fetch or check
the state of possible vCPUs. It also introduces the concept of *disabled* vCPUs,
which are part of the *possible* vCPUs but are not enabled. This state will be
used during machine initialization and later during the pl
This shall be used to store user specified topology{socket,cluster,core,thread}
and shall be converted to a unique 'vcpu-id' which is used as slot-index during
hot(un)plug of vCPU.
Co-developed-by: Keqian Zhu
Signed-off-by: Keqian Zhu
Signed-off-by: Salil Mehta
---
hw/arm/virt.c | 10 +
Introduce the common logic required during the initialization of both cold and
hot-plugged vCPUs. Additionally, initialize the *disabled* state of the vCPUs,
which will be used further during the initialization phases of various other
components like GIC, PMU, ACPI, etc., as part of the virtual mac
In the ARMv8 architecture, the GIC must know all the CPUs it is connected to
during its initialization, and this cannot change afterward. This must be
ensured during the initialization of the VGIC in KVM, which requires all vCPUs
to be created and present during its initialization. This is necessar
Introduce a `gicc_accessible` flag to indicate whether it is safe to access the
GICv3 CPU interface. This flag will determine the availability of the GICv3 CPU
interface based on whether the associated QOM vCPUs are enabled or disabled.
Additionally, implement checks throughout the GICv3 codebase
The GIC must be pre-sized with the possible vCPUs during initialization. This is
essential because:
1. Memory regions and resources associated with GICC/GICR cannot be modified
(i.e., added, deleted, or changed) once the VM has been initialized.
2. Additionally, the `GIC_TYPER` must be initiali
The GICv3 CPU interface must be (re)initialized when a vCPU is either cold- or
hot-plugged. System registers need to be defined and registered with the
associated vCPU. For cold-plugged vCPUs, this occurs during the GICv3
realization phase, while for hot-plugged vCPUs, it happens during the GICv3
u
During GED device creation at Virt Machine initialization, add a new vCPU
hotplug event to the existing set of supported GED device events. Additionally,
initialize the memory map for the vCPU hotplug *control device*, which will
provide an interface to exchange ACPI events between QEMU/VMM and the
ACPI CPU hotplug state (is_present=_STA.PRESENT, is_enabled=_STA.ENABLED) for
all the possible vCPUs MUST be initialized during machine init. This is done
during the creation of the GED device. VMM/Qemu MUST expose/fake the ACPI state
of the disabled vCPUs to the Guest kernel as 'present' (_STA.PRE
ACPI is required to interface QEMU with the guest. Roughly falls into below
cases,
1. Convey the possible vCPUs config at the machine init time to the guest
using various DSDT tables like MADT etc.
2. Convey vCPU hotplug events to guest(using GED)
3. Assist in evaluation of various ACPI methods
On Wed, Oct 09, 2024 at 11:56:38AM +0800, Chuang Xu wrote:
> Date: Wed, 9 Oct 2024 11:56:38 +0800
> From: Chuang Xu
> Subject: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical
> processors in the physical package
> X-Mailer: git-send-email 2.39.3 (Apple Git-146)
>
> When QEMU is
Support for Virtual CPU Hotplug requires a sequence of ACPI handshakes between
QEMU and the guest kernel when a vCPU is plugged or unplugged. Most of the AML
code to support these handshakes already exists. This AML needs to be built
during VM initialization for the ARM architecture as well, if GED
During `machvirt_init()`, QOM ARMCPU objects are pre-created along with the
corresponding KVM vCPUs in the host for all possible vCPUs. This is necessary
due to the architectural constraint that KVM restricts the deferred creation of
KVM vCPUs and VGIC initialization/sizing after VM initialization.
The PMU for all possible vCPUs must be initialized during VM initialization.
Refactor the existing code to accommodate possible vCPUs. This assumes that all
processors being used are identical. It is an architectural constraint of ARM
CPUs that all vCPUs MUST have identical feature sets, at least u
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after the kernel has booted. This is because many system
initializations depend on the exact CPU count at boot time and do not expect it
to change afterward. For example, components like interrupt controllers
From: Jean-Philippe Brucker
The GICC interface on arm64 vCPUs is statically defined in the MADT, and
doesn't require a _MAT entry. Although the GICC is indicated as present
by the MADT entry, it can only be used from vCPU sysregs, which aren't
accessible until hot-add.
Signed-off-by: Jean-Philip
When QEMU builds the MADT table, modifications are needed to include information
about possible vCPUs that are exposed as ACPI-disabled (i.e., `_STA.Enabled=0`).
This new information will help the guest kernel pre-size its resources during
boot time. Pre-sizing based on possible vCPUs will facilita
The ARM CPU architecture does not permit changes to CPU presence after the
kernel has booted. This is an immutable requirement from ARM and represents a
strict architectural constraint [1][2].
The ACPI update [3] reinforces this by specifying that the `_STA.Present` bit
in the ACPI specification c
Add CPU hot-unplug hooks and update hotplug hooks with additional sanity checks
for use in hotplug paths.
Note: The functional contents of the hooks (currently left with TODO comments)
will be gradually filled in subsequent patches in an incremental approach to
patch and logic building, which woul
Virtual CPU hot-(un)plug events must be communicated to the GIC. Introduce a
notification mechanism to ensure these events are properly relayed to the GIC,
allowing it to update the accessibility of the GIC CPU interface and adjust the
vCPU-to-GIC CPU interface association accordingly.
This approa
Refactors the existing GIC create code to extract common code to wire the
vcpu<->gic interrupts. This function could be used with cold-plug case and also
used when vCPU is hot-plugged. It also introduces a new function to unwire the
vcpu<->gic interrupts for the vCPU hot-unplug cases.
Co-developed
Updates the firmware config with the next boot cpus information and also
registers the reset callback to be called when guest reboots to reset the cpu.
Co-developed-by: Keqian Zhu
Signed-off-by: Keqian Zhu
Signed-off-by: Salil Mehta
---
hw/arm/boot.c | 2 +-
hw/arm/virt.c | 18
During any vCPU hot-(un)plug operation, the running guest VM must be notified
about the addition of a new vCPU or the removal of an existing vCPU. This
notification is handled via an ACPI GED event, which is eventually demultiplexed
into a vCPU hotplug event, and then further into a specific hot-(u
The ARM extensions configuration *must* match the existing vCPUs already
initialized in KVM at VM initialization. ARM does not allow any per-vCPU
features to be changed once the system has fully initialized. This is an
immutable constraint of the ARM CPU architecture.
Signed-off-by: Salil Mehta
-
On Oct 1 06:58, Ayush Mishra wrote:
> Adding support for new 32 bit NPDGL and NPDAL fields to address the
> needs of larger granularities.
>
> Signed-off-by: Ayush Mishra
> ---
> v1 -> v2: Added macros for NSFEAT in /include/block/nvme.h as suggested
> by Klaus.
>
LGTM.
I'll add a name to th
On Sep 25 06:14, Arun Kumar wrote:
> add support for i/o command set independent namespace data
> structure(cns=8h and cns=1fh)
>
> Signed-off-by: Klaus Jensen
> Signed-off-by: Arun Kumar
Looks good.
Reviewed-by: Klaus Jensen
> ---
> hw/nvme/ctrl.c | 31 +++
Hi Jonathan,
On Tue, Oct 08, 2024 at 11:30:38AM +0100, Jonathan Cameron wrote:
> Date: Tue, 8 Oct 2024 11:30:38 +0100
> From: Jonathan Cameron
> Subject: Re: [RFC v2 00/12] Introduce Hybrid CPU Topology via Custom
> Topology Tree
> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32)
>
On 10/8/24 07:45, Peter Maydell wrote:
On Sat, 5 Oct 2024 at 21:06, Richard Henderson
wrote:
Zero is the safe do-nothing value for callers to use.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/ptw.c| 2 +-
target/arm/tcg/m_helper.c | 8
On 08-10-2024 13:14, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
From: "Philippe Mathieu-Daudé"
It is unfair to let the PowerNV SPI model to the SSI
maintainers. Also include the PowerNV ones.
Fixes: 29318db133 ("hw/ssi: Add SPI model")
Signed-off-by: Phi
On Tue, 8 Oct 2024 at 17:50, John Snow wrote:
>
>
>
> On Tue, Oct 8, 2024, 12:31 PM Peter Maydell wrote:
>>
>> I made some changes to a block backend so I wanted to run the iotests.
>> I ran into an unrelated failure of iotest 297. The bulk of this
>> seems to be because the iotest tries to run o
On Tue, Oct 8, 2024 at 4:27 AM Mark Cave-Ayland
wrote:
>
> On 08/10/2024 02:18, Octavian Purdila wrote:
>
> > Add fifo32_peek() that returns the first element from the queue
> > without popping it.
> >
> > Signed-off-by: Octavian Purdila
> > ---
> > include/qemu/fifo32.h | 28 ++
When we have a tlb miss, defer the alignment check to
the new tlb_fill_align hook. Move the existing alignment
check so that we only perform it with a tlb hit.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 88 --
1 file changed, 45 inserti
This function is specific to MemOp, not TCG in general.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 23 +++
include/tcg/tcg.h| 23 ---
2 files c
Pass memop through get_phys_addr_twostage with its
recursion with get_phys_addr_nogpc.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-
Determine cache attributes, and thence Device vs Normal memory,
earlier in the function. We have an existing regime_is_stage2
if block into which this can be slotted.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 49 -
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/ptw.c| 2 +-
target/arm/tcg/m_helper.c | 8
target/arm/tcg/tlb_helper.
Add a new callback to handle softmmu paging. Return the page
details directly, instead of passing them indirectly to
tlb_set_page. Handle alignment simultaneously with paging so
that faults are handled with target-specific priority.
Route all calls the two hooks through a tlb_fill_align
function
In Chapter 5, Interruptions, the group 3 exceptions lists
"Unaligned data reference trap" has higher priority than
"Data memory break trap".
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Rename to use "memop_" prefix, like other functions
that operate on MemOp.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 4 ++--
accel/tcg/cputlb.c | 4 ++--
accel/tcg/
In Chapter 5, Interruptions, the group 3 exceptions lists
"Data memory access rights trap" in priority order ahead of
"Data memory protection ID trap".
Swap these checks in hppa_get_physical_address.
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 12 +
There should be no "just in case"; the page is already
in the tlb, and known to be not readable.
Reviewed-by: Helge Deller
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cputl
1 - 100 of 281 matches
Mail list logo
